[all-commits] [llvm/llvm-project] f43593: [X86] combineVectorSizedSetCCEquality - allow 256/...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f4359301c033694d36865c7560714164d2050240
      https://github.com/llvm/llvm-project/commit/f4359301c033694d36865c7560714164d2050240
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2025-10-14 (Tue, 14 Oct 2025)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/setcc-wide-types.ll

  Log Message:
  -----------
  [X86] combineVectorSizedSetCCEquality - allow 256/512-bit vector icmp_ne/eq zero comparisons (#163373)

We avoid creating vector movmsk/ptest comparisons with zero if we can
just use scalar OR instead, but this doesn't make sense for 256-bit or
larger vectors which creates a more complex OR chain.

This more closely matches what we do for icmp_ne/eq against non-zero
values.

I'm hoping that we can eventually allow even larger vectors to be
handled with a OR/AND chains - but for now this just allows us to handle
legal 256/512-bit vector widths.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications