[all-commits] [llvm/llvm-project] 6cec36: [RISCV] Support XSfmm LLVM IR and CodeGen (#143069)

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cec3622f63c565b8fb42b63539a797d5d786be9
      https://github.com/llvm/llvm-project/commit/6cec3622f63c565b8fb42b63539a797d5d786be9
  Author: Brandon Wu <songwu0813 at gmail.com>
  Date:   2025-10-14 (Tue, 14 Oct 2025)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
    M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td
    A llvm/test/CodeGen/RISCV/rvv/sifive-O0-ATM-ATK.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e4m3.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e4m3_e5m2.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e4m3.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_e5m2_e5m2.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_f_f.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_s.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_s_u.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_s.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_mm_u_u.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte16.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte32.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte64.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vlte8.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettk.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettm.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vsettnt.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste16.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste32.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste64.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vste8.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtdiscard.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_t_v.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtmv_v_t.ll
    A llvm/test/CodeGen/RISCV/rvv/sifive_sf_vtzero_t.ll

  Log Message:
  -----------
  [RISCV] Support XSfmm LLVM IR and CodeGen (#143069)

stack on: https://github.com/llvm/llvm-project/pull/143068

Co-authored-by: Piyou Chen <piyou.chen at sifive.com>



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