[all-commits] [llvm/llvm-project] 1c00a0: [RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW ...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c00a001f605eb87b54d47ce9d7992f7021474b4
      https://github.com/llvm/llvm-project/commit/1c00a001f605eb87b54d47ce9d7992f7021474b4
  Author: Jim Lin <jim at andestech.com>
  Date:   2025-10-14 (Tue, 14 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
    M llvm/test/CodeGen/RISCV/i64-icmp.ll
    M llvm/test/CodeGen/RISCV/select-to-and-zext.ll
    M llvm/test/CodeGen/RISCV/setcc-logic.ll
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Merge ADDI and SIGN_EXTEND_INREG to ADDIW during selectSETCC. (#162614)

That we can merge ADDI with its LHS to ADDIW if its LHS is a
SIGN_EXTEND_INREG.



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