[all-commits] [llvm/llvm-project] cd33c6: [SPARC] Weaken emitted barriers for atomic ops (#1...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Wed Oct 8 11:14:51 PDT 2025
Branch: refs/heads/users/vitalybuka/spr/nfcspecialcaselist-move-longestmatch-logic-from-warningsspecialcaselist-into-specialcaselist
Home: https://github.com/llvm/llvm-project
Commit: cd33c6b68e7010679517416e87a8abd860bdc747
https://github.com/llvm/llvm-project/commit/cd33c6b68e7010679517416e87a8abd860bdc747
Author: Koakuma <koachan at protonmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
A llvm/test/CodeGen/SPARC/atomics-ordering.ll
M llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
Log Message:
-----------
[SPARC] Weaken emitted barriers for atomic ops (#154950)
Weaken barriers for atomic ops to the form that's just enough to enforce
memory model constraints.
In particular, we try to avoid emitting expensive #StoreLoad barriers
whenever possible.
The barriers emitted conform to V9's RMO and V8's PSO memory model, and
is compatible with GCC's lowering.
A quick test with `pgbench` on a T4-1 shows some small (up to about 4%),
but consistent speedup.
Commit: cb53a2de37460e2d59f6828d3c5f1e35ac512dde
https://github.com/llvm/llvm-project/commit/cb53a2de37460e2d59f6828d3c5f1e35ac512dde
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
Log Message:
-----------
AMDGPU: Account for read/write register intrinsics for AGPR usage (#161988)
Fix the special case intrinsics that can directly reference a physical
register. There's no reason to use this.
Commit: 760a1142feee734d044ab546914407f6b8d96062
https://github.com/llvm/llvm-project/commit/760a1142feee734d044ab546914407f6b8d96062
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M flang-rt/lib/runtime/character.cpp
Log Message:
-----------
[flang][NFC] Revise crash msg for GeneralCharFunc (#162292)
Commit: 1a5494ca4a7d2e6884e17c064e5215b34fbe4b40
https://github.com/llvm/llvm-project/commit/1a5494ca4a7d2e6884e17c064e5215b34fbe4b40
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
Log Message:
-----------
AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158272)
This removes special case processing in TargetInstrInfo::getRegClass to
fixup register operands which depending on the subtarget support AGPRs,
or require even aligned registers.
This regresses assembler diagnostics, which currently work by hackily
accepting invalid cases and then post-rejecting a validly parsed
instruction.
On the plus side this now emits a comment when disassembling unaligned
registers for targets with the alignment requirement.
Commit: 34fda634f7066bab28031eda0ebb637ccd1478a8
https://github.com/llvm/llvm-project/commit/34fda634f7066bab28031eda0ebb637ccd1478a8
Author: Thurston Dang <thurston at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CodeGenFunction.h
Log Message:
-----------
Revert "[Clang][CodeGen] Emit !alloc_token for new expressions" (#162412)
Reverts llvm/llvm-project#162099
Reason: this commit depends on #162098, which I am reverting due to
build breakage (see
https://github.com/llvm/llvm-project/pull/162098#issuecomment-3379070211).
Commit: d9a568034ff817060dc0a83dc3ea160b058a5935
https://github.com/llvm/llvm-project/commit/d9a568034ff817060dc0a83dc3ea160b058a5935
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M lld/wasm/InputChunks.cpp
Log Message:
-----------
[lld][WebAssembly] update error to continue for R_WASM_FUNCTION_INDEX_I32 (#162403)
with some builds we're getting
`[libcxx/include/optional:874](libcxx/include/optional): libc++
Hardening assertion this->has_value() failed: optional operator* called
on a disengaged value` since error() adds the errmsg into the stream and
continues, but given it's an unsupported relocation type it eventually
crashes.
Given that I see that we're already using Fatal() in some of the other
places where it hits unsupported relocation type, my uneducated guess is
that this should be fine.
Commit: c74fa20c955bae00d70d72b48f85b0143d3a1f3d
https://github.com/llvm/llvm-project/commit/c74fa20c955bae00d70d72b48f85b0143d3a1f3d
Author: Thurston Dang <thurston at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/CodeGen/CodeGenFunction.cpp
Log Message:
-----------
Revert "[Clang][CodeGen] Introduce the AllocToken SanitizerKind" (#162413)
Reverts llvm/llvm-project#162098
Reason: buildbot breakage (see
https://github.com/llvm/llvm-project/pull/162098#issuecomment-3379070211)
Commit: 06faca2fec8747adbfcbbaf6a874c96c9cf434ed
https://github.com/llvm/llvm-project/commit/06faca2fec8747adbfcbbaf6a874c96c9cf434ed
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] Port 879f8616ef93
Commit: 0540f04019717b529461db9762170c34176b1ff6
https://github.com/llvm/llvm-project/commit/0540f04019717b529461db9762170c34176b1ff6
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/utils/gn/secondary/bolt/lib/Passes/BUILD.gn
Log Message:
-----------
[gn build] Port c7d776b06897
Commit: 96e0bbc1df41ede2a13820b8582ee003c18eebc4
https://github.com/llvm/llvm-project/commit/96e0bbc1df41ede2a13820b8582ee003c18eebc4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
Log Message:
-----------
AMDGPU: Fix parsing wrong operand format for read_register/write_register (#162414)
Apparently the IR verifier doesn't enforce the correct structure.
Also I do not know why we have this extra level of wrapper in the
intrinsic,
it just makes it harder to get at the string. I also do not know why
kokkos is using these intrinsics, but it shouldn't.
Commit: d01e1c1061864c795c74e552abfbeb98b0b28a50
https://github.com/llvm/llvm-project/commit/d01e1c1061864c795c74e552abfbeb98b0b28a50
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Use getNegative instead of subtracting from zero. NFC (#162313)
Commit: 783c1a7617052cf4c520a487c03813ff38f65667
https://github.com/llvm/llvm-project/commit/783c1a7617052cf4c520a487c03813ff38f65667
Author: James Y Knight <jyknight at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
AMDGPU: skip AMDGPUAttributor pass on R600 some more. (#162418)
This is a follow-up for #162207, where I neglected to skip the second
use of AMDGPUAttributor for R600 targets. This use is covered by the
test lld/test/ELF/lto/r600.ll.
Commit: 4ddc0f3ffd9c609b584db2d089aaec2cec820c06
https://github.com/llvm/llvm-project/commit/4ddc0f3ffd9c609b584db2d089aaec2cec820c06
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
Log Message:
-----------
[AMDGPU] Add the missing enabling check of AMDGPUAttributor (#162420)
Commit: bd1561d5f160a949c0bbf9bfbda3558eb62f98d7
https://github.com/llvm/llvm-project/commit/bd1561d5f160a949c0bbf9bfbda3558eb62f98d7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
Log Message:
-----------
[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995)
GISel doesn't distinquish integer and FP loads and stores. We only
know which it is after register bank selection. This results in
s16/s32 loads/stores on the GPR register bank that need to be
selected. This required extra isel patterns not needed for SDAG
and adding i16 and i32 to the GPR register class. Having i16/i32
on the GPR register class makes type interfence in tablegen less
effective, requiring explicit casts to be added to patterns. It also
increases the size of RISCVGenDAGISel.inc by 2K.
This patch removes the extra isel patterns and replaces it with custom
instruction selection similar to what is done on AArch64. A future
patch will remove i16 and i32 from the GPR register class.
Commit: 3bec46ff95888c537dabbf19895d48e3f0eb7b35
https://github.com/llvm/llvm-project/commit/3bec46ff95888c537dabbf19895d48e3f0eb7b35
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir
M llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s
Log Message:
-----------
[RISCV] Reorder ins/outs of atomic instruction to match their assembly order. NFC (#162411)
I think it is more intuitive for the operand order to match the assembly
order than to be sorted by operand name.
I also changed some isel patterns to always use XLenVT for pointer
operands. This shouldn't be a functional change.
Commit: a1f9ad2a38a6a5a8b38918e0d18c6b5672e44892
https://github.com/llvm/llvm-project/commit/a1f9ad2a38a6a5a8b38918e0d18c6b5672e44892
Author: Thurston Dang <thurston at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
Log Message:
-----------
[SPARC] Fix-forward #154950 by returning true if SP::V8BAR is handled (#162424)
Use-after-poison happens because after SP::V8BAR is handled, it erases
MI, which therefore should not be inspected by `ExpandPostRA::run()`.
This fixes a buildbot-reported issue from #154950
(https://lab.llvm.org/buildbot/#/builders/24/builds/13433).
Commit: a29d7a1f04ce2ba50300398fc5670b499e5d89d9
https://github.com/llvm/llvm-project/commit/a29d7a1f04ce2ba50300398fc5670b499e5d89d9
Author: David Green <david.green at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
Log Message:
-----------
[GlobalISel] fdiv to fmul transform (#144305)
This is a port of the SDAG DAGCombiner::combineRepeatedFPDivisors
combine that looks for multiple fdiv operations with the same divisor
and converts them to a single reciprocal fdiv and multiple fmuls. It is
currently a fairly faithful port, with some additions to make sure that
the newly created fdiv dominates all new uses. Compared to the SDAG
version it also drops some logic about splat uses which assumes no
vector fdivs and some logic about x/sqrt(x) which does not yet apply to
GISel.
Commit: df3de1399bfae1bc99b68690926369ae9863d945
https://github.com/llvm/llvm-project/commit/df3de1399bfae1bc99b68690926369ae9863d945
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Remove redundant tests (#159804)
We ended up with a duplicate test case post #150284 - this PR removes
that. I am also renaming the corresponding test function name, which is
no longer valid (*).
(*) `@extract_from_0d_splatlike_broadcast_regression` implies that all
the tested vectors are rank-0, but that is not the case.
Commit: cac5bfac11ab352d9e96adeeebce4860ec86e032
https://github.com/llvm/llvm-project/commit/cac5bfac11ab352d9e96adeeebce4860ec86e032
Author: Ryan Cowan <ryan.cowan at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir
M llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fcvt-fixed.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize s16 G_FCONSTANT to avoid widening to G_CONSTANT (#161205)
When widening a `G_FCONSTANT` it is converted to a `G_CONSTANT` to avoid
loss in accuracy (see
https://github.com/llvm/llvm-project/issues/56454). This means that some
folds such as `G_FPEXT(G_FCONSTANT)` fail to work when the scalar has
been widened.
This PR legalizes `s16`s by default in line with how s16 `G_CONSTANT`s
are treated.
Commit: 89e2d58ec8189e77c34e39b1e8c9992315ad682f
https://github.com/llvm/llvm-project/commit/89e2d58ec8189e77c34e39b1e8c9992315ad682f
Author: flovent <flbven at protonmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-pointer-as-pointers.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
Log Message:
-----------
[clang-tidy] Fix false positives about references in `misc-const-correctness` (#160971)
It's not legal to cast const pointer type to it's non-const reference
type implicitly, and will cause compile error.
And for explicit cast, it's legal but the pointer is mutable through
this reference.
Commit: d45b427ed476529a6cc52566c03839ad976ac37f
https://github.com/llvm/llvm-project/commit/d45b427ed476529a6cc52566c03839ad976ac37f
Author: Alexandre Eichenberger <alexe at us.ibm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
Log Message:
-----------
[MLIR] Define memory effects for `memref.prefetch` operation (#151261)
Currently `memref.prefetch` has no memory side effects, which are
necessary for some optimizations.
This PR adds the needed side effect, as recommended in
https://discourse.llvm.org/t/modeling-volatility-with-memory-effects/67946
This PR was created after a discussion on this specific topic here
https://discourse.llvm.org/t/memref-prefetch-op-has-no-memory-side-effects-decoration-in-the-def-td-file/87482
---------
Signed-off-by: Alexandre Eichenberger <alexe at us.ibm.com>
Commit: 7296734394ce5e8b4041216872741fec83396616
https://github.com/llvm/llvm-project/commit/7296734394ce5e8b4041216872741fec83396616
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/scalable-predication.ll
Log Message:
-----------
[VPlan] Mark ActiveLaneMask as not having mem effects (#162330)
VPInstruction::ActiveLaneMask does not read or write memory. This allows
us to clean up some dead recipes.
Commit: 772071bb75772ddff43c9525f2b66077fd873c04
https://github.com/llvm/llvm-project/commit/772071bb75772ddff43c9525f2b66077fd873c04
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Improve code using VPIRPhi::getIRPhi (NFC) (#162270)
Commit: 1ab69d7004fe8b404c1f83d306838442f549e1ee
https://github.com/llvm/llvm-project/commit/1ab69d7004fe8b404c1f83d306838442f549e1ee
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[CMake] Suppress -Wpass-failed warning (#160472)
libstdc++15 makes use of an unroll pragma inside std::find_if(). This
produces a warning if clang fails to unroll the loop. As this pragma is
outside of our control, suppress the warning. Missed transforms are not
something we care about in this context.
Related to https://github.com/llvm/llvm-project/issues/157666.
Commit: f59736758113c568908c6b9293622c530d6ab827
https://github.com/llvm/llvm-project/commit/f59736758113c568908c6b9293622c530d6ab827
Author: jeanPerier <jperier at nvidia.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
M flang/test/HLFIR/declare-codegen.fir
M flang/test/HLFIR/invalid.fir
Log Message:
-----------
[flang][HLFIR] add skip_rebox option to hlfir.declare (#162305)
hlfir.declare with a fir.box input always lead to a fir.rebox being
created to ensure the lower bounds and attributes are set correctly in
the local descriptor for the entity. This is really needed for
hlfir.declare using fir.box function argument that do not come with any
guarantees with regards to the lower bounds.
Sometimes however, this fir.rebox just adds a lot of noise in the SSA
chain, especially at the LLVM level and it is known that the input
descriptor is already correct.
I am making this patch in the context of OpenACC where I want to remap
the variables inside the compute region, creating a fir.rebox on the
way. This fir.rebox cannot be optimized away by FIR because of the
OpenACC ops in the SSA chain.
This patch adds a flag to indicate the the fir.box is known to have the
correct lower bounds and attributes so that it can have a simpler code
generation to FIR.
Commit: 100db538565c80164b05b1c3a5bebeaa0e772fc4
https://github.com/llvm/llvm-project/commit/100db538565c80164b05b1c3a5bebeaa0e772fc4
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Log Message:
-----------
[InstCombine][nfc] Remove dead invoke inst check in foldOpIntoPhi (#161871)
There's a check above the pred block is terminated with an unconditional
branch, so this code is unreachable.
Commit: 71586a6a736f03d5a373c51490598c8c0cb16625
https://github.com/llvm/llvm-project/commit/71586a6a736f03d5a373c51490598c8c0cb16625
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/test/Conversion/ConvertToEmitC/tosa.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-out-params.mlir
M mlir/test/Transforms/buffer-results-to-out-params-add-result-attr.mlir
M mlir/test/Transforms/buffer-results-to-out-params-hosit-static-allocs.mlir
M mlir/test/Transforms/buffer-results-to-out-params.mlir
Log Message:
-----------
[mlir][bufferize] Make buffer-results-to-out-params support only functions that are neither public nor extern (#162441)
The callers of public or extern functions are unknown, so their function
signatures cannot be changed.
Commit: 4967bc17dfbfdd6fe38b4444a2e9379c6474ce55
https://github.com/llvm/llvm-project/commit/4967bc17dfbfdd6fe38b4444a2e9379c6474ce55
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
Log Message:
-----------
[DAGCombiner] Remove NoSignedZerosFPMath in visitFNEG (#162052)
Remove the `NoSignedZerosFPMath` use in `visitFNEG`. Now the only use of
`NoSignedZerosFPMath` is in `foldFPToIntToFP`, but adding fast-math
flags support for `uitofp` may introduce breaking changes.
Commit: 889bfd91728a8ca8d27d3f0e5605464201bf5b3e
https://github.com/llvm/llvm-project/commit/889bfd91728a8ca8d27d3f0e5605464201bf5b3e
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A bolt/docs/PacRetDesign.md
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlus.h
M bolt/include/bolt/Core/MCPlusBuilder.h
A bolt/include/bolt/Passes/InsertNegateRAStatePass.h
A bolt/include/bolt/Passes/MarkRAStates.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryBasicBlock.cpp
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/Exceptions.cpp
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/lib/Passes/CMakeLists.txt
A bolt/lib/Passes/InsertNegateRAStatePass.cpp
A bolt/lib/Passes/MarkRAStates.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/negate-ra-state-disallow.s
A bolt/test/AArch64/negate-ra-state-incorrect.s
A bolt/test/AArch64/negate-ra-state-reorder.s
A bolt/test/AArch64/negate-ra-state.s
A bolt/test/AArch64/pacret-split-funcs.s
A bolt/test/runtime/AArch64/negate-ra-state.cpp
A bolt/test/runtime/AArch64/pacret-function-split.cpp
Log Message:
-----------
Reapply "[BOLT][AArch64] Handle OpNegateRAState to enable optimizing binaries with pac-ret hardening" (#162353) (#162435)
Reapply "[BOLT][AArch64] Handle OpNegateRAState to enable optimizing
binaries with pac-ret hardening (#120064)" (#162353)
This reverts commit c7d776b06897567e2d698e447d80279664b67d47.
#120064 was reverted for breaking builders.
Fix: changed the mismatched type in MarkRAStates.cpp to `auto`.
---
Original message:
OpNegateRAState is an AArch64-specific DWARF CFI used to change the value
of the RA_SIGN_STATE pseudoregister. The RA_SIGN_STATE register records
whether the current return address has been signed with PAC.
OpNegateRAState requires special handling in BOLT because its placement
depends on the function layout. Since BOLT reorders basic blocks during
optimization, these CFIs must be regenerated after layout is finalized.
This patch introduces two new passes:
- MarkRAStates (runs before optimizations): assigns a signedness annotation to each
instruction based on OpNegateRAState CFIs in the input binary.
- InsertNegateRAStates (runs after optimizations): reads the annotations and emits
new OpNegateRAState CFIs where RA state changes between instructions.
Design details are described in: `bolt/docs/PacRetDesign.md`.
Commit: 008294c0ccec9df76e236133b1013ba7a54ba7d5
https://github.com/llvm/llvm-project/commit/008294c0ccec9df76e236133b1013ba7a54ba7d5
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/utils/gn/secondary/bolt/lib/Passes/BUILD.gn
Log Message:
-----------
[gn build] Port 889bfd91728a
Commit: 53a397a9cb8acaa61d29dfa13a03ad17fb51755c
https://github.com/llvm/llvm-project/commit/53a397a9cb8acaa61d29dfa13a03ad17fb51755c
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/switch-to-arithmetic-inlining.ll
Log Message:
-----------
[PhaseOrdering] Add test for failure to inline simplifiable switch
The large switch simplifies to a single umin, but only after
inlining, so the trivial call in test2() does not get inlined.
Commit: 301ecc6da9b1633ab9256d32ca23c53146e7d652
https://github.com/llvm/llvm-project/commit/301ecc6da9b1633ab9256d32ca23c53146e7d652
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A llvm/test/CodeGen/SPIRV/llc-pipeline.ll
Log Message:
-----------
[NFC][SPIRV] Add a test documenting the passes in the SPIRV backend (#162057)
Commit: 20f41ed8c195eff6199dc77bdd20f7226cfdae0f
https://github.com/llvm/llvm-project/commit/20f41ed8c195eff6199dc77bdd20f7226cfdae0f
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
M llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopc.s
M llvm/test/MC/AMDGPU/literals.s
M llvm/test/MC/AMDGPU/vop3-literal.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt
Log Message:
-----------
[AMDGPU][MC] Avoid creating lit64() operands unless asked or needed. (#161191)
There should normally be no need to generate implicit lit64()
modifiers on the assembler side. It's the encoder's responsibility
to recognise literals that are implicitly 64 bits wide.
The exceptions are where we rewrite floating-point operand values
as integer ones, which would not be assembled back to the original
values unless wrapped into lit64().
Respect explicit lit() modifiers for non-inline values as
necessary to avoid regressions in MC tests. This change still
doesn't prevent use of inline constants where lit()/lit64 is
specified; subject to a separate patch.
On disassembling, only create lit64() operands where necessary for
correct round-tripping.
Add round-tripping tests where useful and feasible.
Commit: a5e6b07521dbd673bdadb9cf334dce9d574477e0
https://github.com/llvm/llvm-project/commit/a5e6b07521dbd673bdadb9cf334dce9d574477e0
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Log Message:
-----------
[AArch64][SME] Add common helper for expanding conditional pseudos (NFC) (#155398)
Factors out some common slightly tricky code. Hopefully makes adding new
pseudos simpler.
Commit: ad00610831164b22e936aba010a96d46beb497d8
https://github.com/llvm/llvm-project/commit/ad00610831164b22e936aba010a96d46beb497d8
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
Log Message:
-----------
[DFAJumpThreading][NFC] Clear cleanPhiNodes and phi-related code (#162423)
Commit: ff9cdbdb1af25d77014707754e8d4ec72f4b75dd
https://github.com/llvm/llvm-project/commit/ff9cdbdb1af25d77014707754e8d4ec72f4b75dd
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/include/clang/Basic/CMakeLists.txt
M clang/lib/Sema/SemaARM.cpp
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_rax1.c
A clang/test/Sema/AArch64/arm_sme_streaming_compatible_sme.c
A clang/test/Sema/AArch64/arm_sme_streaming_compatible_sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_LP_sme-f16f16_OR_sme-f8f16_RP.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-b16b16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f64f64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f8f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f8f32.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-i16i64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-lutv2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-f64f64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-i16i64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-b16b16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f64f64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f8f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f8f32.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-i16i64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-b16b16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-f8f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-f8f32.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p1.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p1_OR_sme2_RP___sme_AND_LP_sve2p1_OR_sme2_RP.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p1_OR_sme2p1_RP___sme_AND_LP_sve2p1_OR_sme2p1_RP.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p1_OR_sme_RP___sme.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_bf16___sme_AND_bf16.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_i8mm___sme_AND_i8mm.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-aes___sme_AND_ssve-aes.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-b16b16___sme_AND_sme2_AND_sve-b16b16.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-bitperm___sme_AND_ssve-bitperm.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-sha3___sme_AND_sve-sha3_AND_sme2p1.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_faminmax___sme_AND_sme2_AND_faminmax.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8___sme_AND_sme2_AND_fp8.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8dot2___sme_AND_ssve-fp8dot2.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8dot4___sme_AND_ssve-fp8dot4.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8fma___sme_AND_ssve-fp8fma.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_lut___sme_AND_sme2_AND_lut.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2___sme.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p1___sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme_AND_sme2_AND_ssve-fexpa.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme_AND_sme2p2.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_bf16.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_f32mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_f64mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_i8mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve-sm4.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p1.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2_AND_faminmax.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2_AND_fp8.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2_AND_sve-b16b16.c
R clang/test/Sema/aarch64-streaming-sme-or-nonstreaming-sve-builtins.c
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
A clang/utils/aarch64_builtins_test_generator.py
Log Message:
-----------
[Clang][Sema] Extend test coverage for SVE/SME builtin usage. (#156908)
Adds SEMA tests to verify correct SVE/SME builtin usage based on the
calling function's type (i.e. normal, streaming or streaming
compatible).
For invalid uses the tests verify the expected diagnostic is emitted.
This exposed an issue whereby some builtins are incorrectly callable by
streaming compatible functions, which this PR fixes.
The tests are autogenerated based on the builtin definitions (e.g.
arm_sve.td). This is achieved by extending SVEEmitter, which can now
emit a JSON file containing builtin usage information that can be fed to
aarch64_builtins_test_generator.py that is also part of this PR.
Everything currently in `clang/test/Sema/AArch64` is the result of:
```
clang/utils/aarch64_builtins_test_generator.py --gen-streaming-guard-tests <LLVM_BUILD_DIR>/tools/clang/include/clang/Basic/arm_sve_builtins.json --out-dir clang/test/Sema/AArch64/
clang/utils/aarch64_builtins_test_generator.py --gen-streaming-guard-tests <LLVM_BUILD_DIR>/tools/clang/include/clang/Basic/arm_sme_builtins.json --out-dir clang/test/Sema/AArch64/
```
Commit: fd5bc6033e521b946f04cb9c473d9cca3da2da9b
https://github.com/llvm/llvm-project/commit/fd5bc6033e521b946f04cb9c473d9cca3da2da9b
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizeImplicitBinding.cpp
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
Log Message:
-----------
[SPIRV][SPIRVLegalizeImplicitBinding] Implement getPassName (#162058)
Commit: 631707d566660c142060d2339b98fec3f389ea33
https://github.com/llvm/llvm-project/commit/631707d566660c142060d2339b98fec3f389ea33
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/test/MC/AMDGPU/literals.s
Log Message:
-----------
[AMDGPU][NFC] Update MC/AMDGPU/literals.s using the script. (#162135)
Commit: 2d8769151f507f342257a5921fb268166e35d72d
https://github.com/llvm/llvm-project/commit/2d8769151f507f342257a5921fb268166e35d72d
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
Log Message:
-----------
[NFC][MC] Fix build error. (#162442)
Fixes `llvm-mc-assemble-fuzzer.cpp:207:66: error: no viable conversion
from 'MCInstPrinter *' to 'std::unique_ptr<MCInstPrinter>'`
Commit: 4d45718b478940cd11ac80dd64db8408bb21dbca
https://github.com/llvm/llvm-project/commit/4d45718b478940cd11ac80dd64db8408bb21dbca
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[IVDescriptors] Add isFPMinMaxNumRecurrenceKind helper (NFC).
Add helper to check for FMinNum and FMaxNum recurrence kinds, as
suggested in https://github.com/llvm/llvm-project/pull/161735.
Commit: a6d1a52b8da9cb3c351a086180f8b871f0fd2a6e
https://github.com/llvm/llvm-project/commit/a6d1a52b8da9cb3c351a086180f8b871f0fd2a6e
Author: Hanchenng Wu <42194432+HanchengWu at users.noreply.github.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/include/mlir/Interfaces/RuntimeVerifiableOpInterface.td
M mlir/include/mlir/Transforms/Passes.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Dialect/Linalg/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/Tensor/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Interfaces/RuntimeVerifiableOpInterface.cpp
M mlir/lib/Transforms/GenerateRuntimeVerification.cpp
M mlir/test/Dialect/Linalg/runtime-verification.mlir
Log Message:
-----------
[MLIR] Reuse AsmState to enable fast generate-runtime-verification pass; add location-only pass option (#160331)
The pass generate-runtime-verification generates additional runtime op
verification checks.
Currently, the pass is extremely expensive. For example, with a
mobilenet v2 ssd network(converted to mlir), running this pass alone in
debug mode will take 30 minutes. The same observation has been made to
other networks as small as 5 Mb.
The culprit is this line "op->print(stream, flags);" in function
"RuntimeVerifiableOpInterface::generateErrorMessage" in File
mlir/lib/Interfaces/RuntimeVerifiableOpInterface.cpp.
As we are printing the op with all the names of the operands in the
middle end, we are constructing a new SSANameState for each
op->print(...) call. Thus, we are doing a new SSA analysis for each
error message printed.
Perf profiling shows that 98% percent of the time is spent in the
constructor of SSANameState.
This change refactored the message generator. We use a toplevel
AsmState, and reuse it with all the op-print(stream, asmState). With a
release build, this change reduces the pass exeuction time from ~160
seconds to 0.3 seconds on my machine.
This change also adds verbose options to generate-runtime-verification
pass.
verbose 0: print only source location with error message.
verbose 1: print the full op, including the name of the operands.
Commit: 2d12eaa68db4dcddfc74bed906bc26ae6b874cc1
https://github.com/llvm/llvm-project/commit/2d12eaa68db4dcddfc74bed906bc26ae6b874cc1
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/test/MC/AMDGPU/literals.s
Log Message:
-----------
[AMDGPU][MC][NFC] Run the literal tests for GFX11+. (#162136)
Commit: 7da07c081c081edb9f6706cb8ec298c3cee8ec17
https://github.com/llvm/llvm-project/commit/7da07c081c081edb9f6706cb8ec298c3cee8ec17
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/gdbclientutils.py
Log Message:
-----------
[lldb][test] Remove class level packetLog in MockGDBServerResponder (#162453)
Added in 1902ffd9a4914d4cd03e200ca9050bf3b1564c19 but appears to be
leftover code from some older design.
I can't find any code that reads packetLog via the class itself, or
checks whether it is None.
No tests failed on AArch64 Linux after removing it.
Commit: 8e3eeb854b662beca3e0476199ea6d253dc89752
https://github.com/llvm/llvm-project/commit/8e3eeb854b662beca3e0476199ea6d253dc89752
Author: Joshua Peterson <petersonjm1 at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M lldb/source/Target/Language.cpp
M lldb/unittests/Target/LanguageTest.cpp
Log Message:
-----------
[lldb] Fix off-by-one error in ToDwarfSourceLanguage (#162315)
The ToDwarfSourceLanguage function incorrectly excluded languages that
equal eLanguageTypeLastStandardLanguage. The comparison used `<` instead
of `<=`, causing the last standard language to fall through to the
default case and return std::nullopt.
This broke language plugins that use eLanguageTypeLastStandardLanguage
(currently Mojo at 0x0033) as their language code, preventing proper
DWARF language conversion and breaking REPL functionality.
The fix changes the comparison from `<` to `<=` to include the last
standard language in the automatic conversion to DWARF source language.
This is a regression from commit
7f51a2a47d2e706d04855b0e41690ebafa2b3238 which introduced the
ToDwarfSourceLanguage function.
Commit: 7f03b22dce1f4dae9db3ec8919db7dbd98202e0b
https://github.com/llvm/llvm-project/commit/7f03b22dce1f4dae9db3ec8919db7dbd98202e0b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
Log Message:
-----------
[SLP]Enable SDiv/UDiv support as main op in copyables (#161892)
Allow SDiv/UDiv as a main operation in copyables support
Commit: eac3788b4e2dd305a84f09ebc6fffc050ee84a68
https://github.com/llvm/llvm-project/commit/eac3788b4e2dd305a84f09ebc6fffc050ee84a68
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
Log Message:
-----------
[orc-rt] Rename unit tests for consistency. NFCI.
Related tests use "TransparentConversion" rather than
"TransparentSerialization".
Commit: 3d4da1ee816f53a48e2b645c17069a80fabfb07b
https://github.com/llvm/llvm-project/commit/3d4da1ee816f53a48e2b645c17069a80fabfb07b
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
M llvm/test/MC/AMDGPU/literals.s
Log Message:
-----------
[AMDGPU][MC] Do not inline lit()/lit64() operands. (#162137)
For now treat the modifiers synonymous to each other.
The disassembler side is to be addressed separately.
Commit: 5260920bdcb4f984d167812dd8cd859e51c31b4b
https://github.com/llvm/llvm-project/commit/5260920bdcb4f984d167812dd8cd859e51c31b4b
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
Log Message:
-----------
[AMDGPU][MC][NFC] Fix GFX1250 VOP1 True16 tests. (#162285)
Completes resolving
<https://github.com/llvm/llvm-project/issues/161381>.
Commit: bb36630ecd94c1b7b9f8e3aba31ed2215d43c5b2
https://github.com/llvm/llvm-project/commit/bb36630ecd94c1b7b9f8e3aba31ed2215d43c5b2
Author: SahilPatidar <patidarsahil2001 at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M compiler-rt/lib/orc/coff_platform.cpp
M compiler-rt/lib/orc/coff_platform.h
M compiler-rt/lib/orc/dlfcn_wrapper.cpp
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
Log Message:
-----------
[ORC][Runtime] Add dlupdate for coff (#115448)
With the help of @lhames, This pull request introduces the dlupdate
function in the ORC runtime. dlupdate enables incremental execution of
new initializers introduced in the REPL environment. Unlike traditional
dlopen, which manages initializers, code mapping, and library reference
counts, dlupdate focuses exclusively on running new initializers.
Commit: 482cd5fe067b0d16abd65acdc693b8d178bb1098
https://github.com/llvm/llvm-project/commit/482cd5fe067b0d16abd65acdc693b8d178bb1098
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[OpenMP][docs] Update OpenMP 6.0 OMP_AVAILABLE_DEVICES status (#162440)
The trait support being implemented for OMP_DEFAULT_DEVICES can also be
used for OMP_AVAILABLE_DEVICES, which makes it reasonable to wait to
avoid duplicate effort.
Commit: c7fbe388938b2c9ee78a3160fedebd9bebe5d20d
https://github.com/llvm/llvm-project/commit/c7fbe388938b2c9ee78a3160fedebd9bebe5d20d
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll
Log Message:
-----------
[SCEV] Pass loop pred branch as context instruction to getMinTrailingZ. (#160941)
When computing the backedge taken count, we know that the expression
must be valid just before we enter the loop. Using the terminator of the
loop predecessor as context instruction for getConstantMultiple,
getMinTrailingZeros allows using information from things like alignment
assumptions.
When a context instruction is used, the result is not cached, as it is
only valid at the specific context instruction.
Compile-time looks neutral:
http://llvm-compile-time-tracker.com/compare.php?from=9be276ec75c087595ebb62fe11b35c1a90371a49&to=745980f5e1c8094ea1293cd145d0ef1390f03029&stat=instructions:u
No impact on llvm-opt-benchmark
(https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2867), but leads to
additonal unrolling in ~90 files across a C/C++ based corpus including
LLVM on AArch64 using libc++ (which emits alignment assumptions for
things like std::vector::begin).
PR: https://github.com/llvm/llvm-project/pull/160941
Commit: 805451faedabf0e227b51683d43ebe3093115e58
https://github.com/llvm/llvm-project/commit/805451faedabf0e227b51683d43ebe3093115e58
Author: Keshav Vinayak Jha <31160700+keshavvinayak01 at users.noreply.github.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[MLIR][Vector] Added ToElementsOp::fold for broadcast->to_elements pattern rewrite. (#160318)
Adds `::fold` for the new `vector.to_elements` op, folding `broadcast`
into `to_elements` or no-op wherever possible.
---------
Signed-off-by: keshavvinayak01 <keshavvinayakjha at gmail.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
Commit: 4c8275470465528c469436d37b9aaf71d6598899
https://github.com/llvm/llvm-project/commit/4c8275470465528c469436d37b9aaf71d6598899
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SimplifyCFGOptions.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Other/new-pm-print-pipeline.ll
M llvm/test/Transforms/PhaseOrdering/switch-to-arithmetic-inlining.ll
M llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll
Log Message:
-----------
[SimplifyCFG] Allow some switch optimizations early in the pipeline (#158242)
While we do not want to form actual lookup tables early, we do want to
perform some optimizations, as they may enable inlining of the much
simpler form.
Builds on https://github.com/llvm/llvm-project/pull/156477, which
originally included this change as well. This PR makes two changes on
top of it:
* Do not perform the optimization early if it requires adding a mask
check. These make the resulting IR less analyzable.
* Add a new SimplifyCFG option that controls switch-to-arithmetic
conversion separately from switch-to-lookup conversion. Enable the new
flag at the end of the function simplification pipeline. This means that
we attempt the arithmetic conversion before inlining, but avoid it in
the early pipeline, where it may lose information.
Commit: 81589a39bff58e5a750ea7b656f66cf941803e3b
https://github.com/llvm/llvm-project/commit/81589a39bff58e5a750ea7b656f66cf941803e3b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
Log Message:
-----------
[AMDGPU] Regenerate test checks for mad24 tests (#162455)
Commit: f53b6249c24005d1a6208cd9e355595eb6519dc0
https://github.com/llvm/llvm-project/commit/f53b6249c24005d1a6208cd9e355595eb6519dc0
Author: maxbartel <bartel at roofline.ai>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgRelayoutOps.td
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/test/Dialect/Linalg/decompose-pack.mlir
Log Message:
-----------
[MLIR][Linalg] Fix empty tensor assumptions for linalg.pack decomposition (#160246)
The original code seemed to assume that the tiling dimensions for the
tensor.empty op before applying the transposing were always the last
dimensions. However, pack allows you to choose any dimension to tile.
The easiest way I found to solve this is to prefill the SmallVector with
1s of size (srcRank - numberOfTiles) and then appending the tile sizes.
This way I could also get rid of the first loop in the code.
Commit: 7910ed22320c5f298c4645ffa9072238c95bc7d6
https://github.com/llvm/llvm-project/commit/7910ed22320c5f298c4645ffa9072238c95bc7d6
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
A llvm/test/Transforms/InstCombine/fold-selective-shift.ll
Log Message:
-----------
[InstCombine] Canonicalise packed-integer-selecting shifts (#162147)
This patch resolves recent regressions related to [issue
#92891](https://github.com/llvm/llvm-project/issues/92891).
It specifically enables the following types of reductions.
```llvm
define i16 @src(i32 %mask, i32 %upper, i32 range(i32 0, 65536) %lower) {
%upper.shl = shl nuw i32 %upper, 16
%pack = or disjoint i32 %upper.shl, %lower
%mask.bit = and i32 %mask, 16
%sel = lshr i32 %pack, %mask.bit
%trunc = trunc i32 %sel to i16
ret i16 %trunc
}
; =>
define i16 @tgt(i32 %mask, i32 %upper, i32 range(i32 0, 65536) %lower) {
%mask.bit = and i32 %mask, 16
%mask.bit.z = icmp eq i32 %mask.bit, 0
%sel = select i1 %mask.bit.z, i32 %lower, i32 %upper
%trunc = trunc i32 %sel to i16
ret i16 %trunc
}
```
Alive2 proofs: [gJ9MpP](https://alive2.llvm.org/ce/z/gJ9MpP)
Commit: c3aa1584e0981d5bbd26c076c3a2298ccf34e3ca
https://github.com/llvm/llvm-project/commit/c3aa1584e0981d5bbd26c076c3a2298ccf34e3ca
Author: Vlad Lazar <lazar_2004 at list.ru>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
A mlir/test/Conversion/SCFToEmitC/while.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
A mlir/test/Target/Cpp/do.mlir
Log Message:
-----------
[mlir][emitc] Add emitc.do op to the dialect (#143008)
This patch adds:
- Emission of the corresponding ops in the CppEmitter
- Conversion from the SCF dialect to the EmitC dialect for the ops
- Corresponding tests
Commit: d7eade1379606b984026ec06ea8d8eaa8a6e10ce
https://github.com/llvm/llvm-project/commit/d7eade1379606b984026ec06ea8d8eaa8a6e10ce
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M flang/test/Examples/omp-atomic.f90
M flang/test/Examples/omp-declarative-directive.f90
M flang/test/Examples/omp-device-constructs.f90
M flang/test/Examples/omp-in-reduction-clause.f90
M flang/test/Examples/omp-nowait.f90
M flang/test/Examples/omp-order-clause.f90
M flang/test/Examples/omp-sections.f90
Log Message:
-----------
[Flang][OpenMP] Fix hardcoded library extension in tests (#162290)
Commit: 30415608d7cbe2a9eaae361e359b5b1891f192c9
https://github.com/llvm/llvm-project/commit/30415608d7cbe2a9eaae361e359b5b1891f192c9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A llvm/test/Transforms/GVN/ptrtoaddr.ll
Log Message:
-----------
[GVN] Add ptrtoaddr test (NFC)
Commit: 801b1dc9cc17ed8b135348add7f95efbd096981d
https://github.com/llvm/llvm-project/commit/801b1dc9cc17ed8b135348add7f95efbd096981d
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/test/Transforms/GVN/ptrtoaddr.ll
Log Message:
-----------
[GVN] Add support for ptrtoaddr
Commit: 0db5ba0ce6c36c78f93ebfe992c0f9ed807328bb
https://github.com/llvm/llvm-project/commit/0db5ba0ce6c36c78f93ebfe992c0f9ed807328bb
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M libc/config/linux/app.h
M libc/src/__support/OSUtil/linux/CMakeLists.txt
A libc/src/__support/OSUtil/linux/auxv.h
M libc/src/__support/threads/callonce.h
M libc/src/__support/threads/linux/CMakeLists.txt
R libc/src/__support/threads/linux/callonce.cpp
M libc/src/__support/threads/linux/callonce.h
M libc/src/pthread/pthread_once.cpp
M libc/src/sys/auxv/linux/CMakeLists.txt
M libc/src/sys/auxv/linux/getauxval.cpp
M libc/src/threads/call_once.cpp
M libc/startup/linux/CMakeLists.txt
M libc/startup/linux/do_start.cpp
Log Message:
-----------
[libc] Refactor AUXV handling with new auxv.h header library (#162326)
Closes https://github.com/llvm/llvm-project/issues/153666
This patch introduces a new centralized AUXV (auxiliary vector) handling
mechanism for LLVM libc on Linux, replacing the previous scattered
implementation across multiple files.
## Key Changes:
### New Files:
- **libc/src/__support/OSUtil/linux/auxv.h**: New header library
providing
a clean interface for AUXV access with:
- `auxv::Entry` struct for AUXV entries (type and value)
- `auxv::Vector` class with iterator support for traversing AUXV
- `auxv::get()` function for retrieving specific AUXV values
- Thread-safe initialization with fallback mechanisms (prctl and
/proc/self/auxv)
### Modified Files:
1. **libc/src/__support/OSUtil/linux/CMakeLists.txt**:
- Added `auxv` header library declaration with proper dependencies:
- libc.hdr.fcntl_macros
- libc.src.__support.OSUtil.osutil
- libc.src.__support.common
- libc.src.__support.CPP.optional
- libc.src.__support.threads.callonce
2. **libc/config/linux/app.h**:
- Removed `AuxEntry` struct (moved to auxv.h as `auxv::Entry`)
- Removed `auxv_ptr` from `AppProperties` struct
- Simplified application properties structure
3. **libc/src/sys/auxv/linux/getauxval.cpp**:
- Completely refactored to use new auxv.h interface
- Removed ~200 lines of complex initialization code
- Simplified to just call `auxv::get()` function
- Removed dependencies to external symbols (mman, prctl, fcntl, read,
close, open)
4. **libc/src/sys/auxv/linux/CMakeLists.txt**:
- Updated dependencies to use new auxv header library
- Removed dependencies to external symbols (prctl, mman, fcntl, unistd,
etc.)
5. **libc/startup/linux/do_start.cpp**:
- Updated to use new `auxv::Vector` interface
- Changed from pointer-based to iterator-based AUXV traversal
- Updated field names (`aux_entry->id` → `aux_entry.type`,
`aux_entry->value` → `aux_entry.val`)
- Added call to `auxv::Vector::initialize_unsafe()` for early AUXV setup
6. **libc/startup/linux/CMakeLists.txt**:
- Added dependency on `libc.src.__support.OSUtil.linux.auxv`
Commit: be301a6a3df2a6acf1323965d21ac4c7ad390f00
https://github.com/llvm/llvm-project/commit/be301a6a3df2a6acf1323965d21ac4c7ad390f00
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/in_addr.h
A libc/include/llvm-libc-types/in_addr_t.h
Log Message:
-----------
[libc] add `in_addr{, _t}` type (#162452)
These types will be used in `arpa/inet.h` and `netinet/in.h`.
Commit: d0da85745dac153705bf1e2c465a8f487068085e
https://github.com/llvm/llvm-project/commit/d0da85745dac153705bf1e2c465a8f487068085e
Author: don <122427011+donneypr at users.noreply.github.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][x86][bytecode] Replace interp__builtin_parity/clrsb/bitreverse/ffs with static bool interp__builtin_elementwise_int_unaryop callback (#162346)
Fixes #160288
Commit: 7815df19deaadceaa55aaa578361afaebfd3cb87
https://github.com/llvm/llvm-project/commit/7815df19deaadceaa55aaa578361afaebfd3cb87
Author: Marco Elver <elver at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/test/Preprocessor/print-header-json.c
Log Message:
-----------
[Clang] Fix brittle print-header-json.c test (#162484)
A recent change adding a new sanitizer kind (via Sanitizers.def) was
reverted in c74fa20c955b ("Revert "[Clang][CodeGen] Introduce the
AllocToken SanitizerKind" (#162413)"). The reason was this ASan report,
when running the test cases in
clang/test/Preprocessor/print-header-json.c:
```
==clang==483265==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x7d82b97e8b58 at pc 0x562cd432231f bp 0x7fff3fad0850 sp 0x7fff3fad0848
READ of size 16 at 0x7d82b97e8b58 thread T0
#0 0x562cd432231e in __copy_non_overlapping_range<const unsigned long *, const unsigned long *> zorg-test/libcxx_install_asan_ubsan/include/c++/v1/string:2144:38
#1 0x562cd432231e in void std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char>>::__init_with_size[abi:nn220000]<unsigned long const*, unsigned long const*>(unsigned long const*, unsigned long const*, unsigned long) zorg-test/libcxx_install_asan_ubsan/include/c++/v1/string:2685:18
#2 0x562cd41e2797 in __init<const unsigned long *, 0> zorg-test/libcxx_install_asan_ubsan/include/c++/v1/string:2673:3
#3 0x562cd41e2797 in basic_string<const unsigned long *, 0> zorg-test/libcxx_install_asan_ubsan/include/c++/v1/string:1174:5
#4 0x562cd41e2797 in clang::ASTReader::ReadString(llvm::SmallVectorImpl<unsigned long> const&, unsigned int&) clang/lib/Serialization/ASTReader.cpp:10171:15
#5 0x562cd41fd89a in clang::ASTReader::ParseLanguageOptions(llvm::SmallVector<unsigned long, 64u> const&, llvm::StringRef, bool, clang::ASTReaderListener&, bool) clang/lib/Serialization/ASTReader.cpp:6475:28
#6 0x562cd41eea53 in clang::ASTReader::ReadOptionsBlock(llvm::BitstreamCursor&, llvm::StringRef, unsigned int, bool, clang::ASTReaderListener&, std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char>>&) clang/lib/Serialization/ASTReader.cpp:3069:11
#7 0x562cd4204ab8 in clang::ASTReader::ReadControlBlock(clang::serialization::ModuleFile&, llvm::SmallVectorImpl<clang::ASTReader::ImportedModule>&, clang::serialization::ModuleFile const*, unsigned int) clang/lib/Serialization/ASTReader.cpp:3249:15
#8 0x562cd42097d2 in clang::ASTReader::ReadASTCore(llvm::StringRef, clang::serialization::ModuleKind, clang::SourceLocation, clang::serialization::ModuleFile*, llvm::SmallVectorImpl<clang::ASTReader::ImportedModule>&, long, long, clang::ASTFileSignature, unsigned int) clang/lib/Serialization/ASTReader.cpp:5182:15
#9 0x562cd421ec77 in clang::ASTReader::ReadAST(llvm::StringRef, clang::serialization::ModuleKind, clang::SourceLocation, unsigned int, clang::serialization::ModuleFile**) clang/lib/Serialization/ASTReader.cpp:4828:11
#10 0x562cd3d07b74 in clang::CompilerInstance::findOrCompileModuleAndReadAST(llvm::StringRef, clang::SourceLocation, clang::SourceLocation, bool) clang/lib/Frontend/CompilerInstance.cpp:1805:27
#11 0x562cd3d0b2ef in clang::CompilerInstance::loadModule(clang::SourceLocation, llvm::ArrayRef<clang::IdentifierLoc>, clang::Module::NameVisibilityKind, bool) clang/lib/Frontend/CompilerInstance.cpp:1956:31
#12 0x562cdb04eb1c in clang::Preprocessor::HandleHeaderIncludeOrImport(clang::SourceLocation, clang::Token&, clang::Token&, clang::SourceLocation, clang::detail::SearchDirIteratorImpl<true>, clang::FileEntry const*) clang/lib/Lex/PPDirectives.cpp:2423:49
#13 0x562cdb042222 in clang::Preprocessor::HandleIncludeDirective(clang::SourceLocation, clang::Token&, clang::detail::SearchDirIteratorImpl<true>, clang::FileEntry const*) clang/lib/Lex/PPDirectives.cpp:2101:17
#14 0x562cdb043366 in clang::Preprocessor::HandleDirective(clang::Token&) clang/lib/Lex/PPDirectives.cpp:1338:14
#15 0x562cdafa84bc in clang::Lexer::LexTokenInternal(clang::Token&, bool) clang/lib/Lex/Lexer.cpp:4512:7
#16 0x562cdaf9f20b in clang::Lexer::Lex(clang::Token&) clang/lib/Lex/Lexer.cpp:3729:24
#17 0x562cdb0d4ffa in clang::Preprocessor::Lex(clang::Token&) clang/lib/Lex/Preprocessor.cpp:896:11
#18 0x562cd77da950 in clang::ParseAST(clang::Sema&, bool, bool) clang/lib/Parse/ParseAST.cpp:163:7
[...]
0x7d82b97e8b58 is located 0 bytes after 3288-byte region [0x7d82b97e7e80,0x7d82b97e8b58)
allocated by thread T0 here:
#0 0x562cca76f604 in malloc zorg-test/llvm-project/compiler-rt/lib/asan/asan_malloc_linux.cpp:67:3
#1 0x562cd1cce452 in safe_malloc llvm/include/llvm/Support/MemAlloc.h:26:18
#2 0x562cd1cce452 in llvm::SmallVectorBase<unsigned int>::grow_pod(void*, unsigned long, unsigned long) llvm/lib/Support/SmallVector.cpp:151:15
#3 0x562cdbe1768b in grow_pod llvm/include/llvm/ADT/SmallVector.h:139:11
#4 0x562cdbe1768b in grow llvm/include/llvm/ADT/SmallVector.h:525:41
#5 0x562cdbe1768b in reserve llvm/include/llvm/ADT/SmallVector.h:665:13
#6 0x562cdbe1768b in llvm::BitstreamCursor::readRecord(unsigned int, llvm::SmallVectorImpl<unsigned long>&, llvm::StringRef*) llvm/lib/Bitstream/Reader/BitstreamReader.cpp:230:10
#7 0x562cd41ee8ab in clang::ASTReader::ReadOptionsBlock(llvm::BitstreamCursor&, llvm::StringRef, unsigned int, bool, clang::ASTReaderListener&, std::__1::basic_string<char, std::__1::char_traits<char>, std::__1::allocator<char>>&) clang/lib/Serialization/ASTReader.cpp:3060:49
#8 0x562cd4204ab8 in clang::ASTReader::ReadControlBlock(clang::serialization::ModuleFile&, llvm::SmallVectorImpl<clang::ASTReader::ImportedModule>&, clang::serialization::ModuleFile const*, unsigned int) clang/lib/Serialization/ASTReader.cpp:3249:15
#9 0x562cd42097d2 in clang::ASTReader::ReadASTCore(llvm::StringRef, clang::serialization::ModuleKind, clang::SourceLocation, clang::serialization::ModuleFile*, llvm::SmallVectorImpl<clang::ASTReader::ImportedModule>&, long, long, clang::ASTFileSignature, unsigned int) clang/lib/Serialization/ASTReader.cpp:5182:15
#10 0x562cd421ec77 in clang::ASTReader::ReadAST(llvm::StringRef, clang::serialization::ModuleKind, clang::SourceLocation, unsigned int, clang::serialization::ModuleFile**) clang/lib/Serialization/ASTReader.cpp:4828:11
#11 0x562cd3d07b74 in clang::CompilerInstance::findOrCompileModuleAndReadAST(llvm::StringRef, clang::SourceLocation, clang::SourceLocation, bool) clang/lib/Frontend/CompilerInstance.cpp:1805:27
#12 0x562cd3d0b2ef in clang::CompilerInstance::loadModule(clang::SourceLocation, llvm::ArrayRef<clang::IdentifierLoc>, clang::Module::NameVisibilityKind, bool) clang/lib/Frontend/CompilerInstance.cpp:1956:31
#13 0x562cdb04eb1c in clang::Preprocessor::HandleHeaderIncludeOrImport(clang::SourceLocation, clang::Token&, clang::Token&, clang::SourceLocation, clang::detail::SearchDirIteratorImpl<true>, clang::FileEntry const*) clang/lib/Lex/PPDirectives.cpp:2423:49
#14 0x562cdb042222 in clang::Preprocessor::HandleIncludeDirective(clang::SourceLocation, clang::Token&, clang::detail::SearchDirIteratorImpl<true>, clang::FileEntry const*) clang/lib/Lex/PPDirectives.cpp:2101:17
#15 0x562cdb043366 in clang::Preprocessor::HandleDirective(clang::Token&) clang/lib/Lex/PPDirectives.cpp:1338:14
#16 0x562cdafa84bc in clang::Lexer::LexTokenInternal(clang::Token&, bool) clang/lib/Lex/Lexer.cpp:4512:7
#17 0x562cdaf9f20b in clang::Lexer::Lex(clang::Token&) clang/lib/Lex/Lexer.cpp:3729:24
#18 0x562cdb0d4ffa in clang::Preprocessor::Lex(clang::Token&) clang/lib/Lex/Preprocessor.cpp:896:11
#19 0x562cd77da950 in clang::ParseAST(clang::Sema&, bool, bool) clang/lib/Parse/ParseAST.cpp:163:7
[...]
SUMMARY: AddressSanitizer: heap-buffer-overflow clang/lib/Serialization/ASTReader.cpp:10171:15 in clang::ASTReader::ReadString(llvm::SmallVectorImpl<unsigned long> const&, unsigned int&)
```
The reason is this particular RUN line:
```
// RUN: env CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILTERING=direct-per-file CC_PRINT_HEADERS_FILE=%t.txt %clang -fsyntax-only -I %S/Inputs/print-header-json -isystem %S/Inputs/print-header-json/system -fmodules -fimplicit-module-maps -fmodules-cache-path=%t %s -o /dev/null
```
which was added in 8df194f6a933 ("[Clang] Support includes translated to
module imports in -header-include-filtering=direct-per-file (#156756)").
The problem is caused by an incremental build reusing stale cached
module files (.pcm) that are no longer binary-compatible with the
updated compiler. Adding a new sanitizer option altered the implicit
binary layout of the serialized LangOptions data structure. The build +
test system is oblivious to such changes. When the new compiler
attempted to read the old module file (from the previous test
invocation), it misinterpreted the data due to the layout mismatch,
resulting in a heap-buffer-overflow. Unfortunately Clang's PCM format
does not encode nor detect version mismatches here; a more graceful
failure mode would be preferable.
For now, fix the test to be more robust with incremental build + test.
Commit: 55c7c4e6232d8aca182cdd6e48ad4211bba27e97
https://github.com/llvm/llvm-project/commit/55c7c4e6232d8aca182cdd6e48ad4211bba27e97
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A llvm/test/Transforms/NewGVN/ptrtoaddr.ll
Log Message:
-----------
[NewGVN] Add test for ptrtoaddr (NFC)
Commit: bcec41e5e6e67ad2a5e194fe3b64d125543ca461
https://github.com/llvm/llvm-project/commit/bcec41e5e6e67ad2a5e194fe3b64d125543ca461
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/test/Transforms/NewGVN/ptrtoaddr.ll
Log Message:
-----------
[NewGVN] Add support for ptrtoaddr
Commit: ee192315b2db387ce6fd2af08fc5f619178b2439
https://github.com/llvm/llvm-project/commit/ee192315b2db387ce6fd2af08fc5f619178b2439
Author: Bhasawut Singhaphan <bhasawut at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512vlbwintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/tmmintrin.h
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512vlbw-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/X86/ssse3-builtins.c
Log Message:
-----------
[Headers][X86] Enable constexpr handling for MMX/SSE/AVX/AVX512 PMADDWD/PMADDUBSW intrinsics (#161563)
This PR updates the PMADDWD/PMADDUBSW builtins to support constant
expression handling, by extending the VectorExprEvaluator::VisitCallExpr
that handles interp__builtin_ia32_pmadd builtins.
Closes #155392
Commit: ea78bfae78f63f0a963a9099054411db6c0eecae
https://github.com/llvm/llvm-project/commit/ea78bfae78f63f0a963a9099054411db6c0eecae
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
A llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll
Log Message:
-----------
[FastISel] Add support for ptrtoaddr
Handle it the same as ptrtoint. For ptrtoaddr the resulting integer
size is guaranteed to match the address size. For the case where
address size and pointer size match, this will be a no-op. For the
case where the address size is smaller than the pointer size, this
will be a truncate (but this is not testable with in-tree targets).
Commit: 8c3d929f0e0e8bfa535f7958a49695f9142742f2
https://github.com/llvm/llvm-project/commit/8c3d929f0e0e8bfa535f7958a49695f9142742f2
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M libc/src/__support/OSUtil/linux/auxv.h
Log Message:
-----------
[libc] use PR_GET_AUXV only if UAPI provides it (#162492)
Commit: 8ba73840e7f94539ff39f78408e030d21b8f3d6f
https://github.com/llvm/llvm-project/commit/8ba73840e7f94539ff39f78408e030d21b8f3d6f
Author: Marco Elver <elver at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/CodeGen/CodeGenFunction.cpp
Log Message:
-----------
[Clang][CodeGen] Introduce the AllocToken SanitizerKind (#162098)
[ Reland after 7815df19deaa ("[Clang] Fix brittle print-header-json.c test") ]
Introduce the "alloc-token" sanitizer kind, in preparation of wiring it
up. Currently this is a no-op, and any attempt to enable it will result
in failure:
clang: error: unsupported option '-fsanitize=alloc-token' for target
'x86_64-unknown-linux-gnu'
In this step we can already wire up the `sanitize_alloc_token` IR
attribute where the instrumentation is enabled. Subsequent changes will
complete wiring up the AllocToken pass.
---
This change is part of the following series:
1. https://github.com/llvm/llvm-project/pull/160131
2. https://github.com/llvm/llvm-project/pull/156838
3. https://github.com/llvm/llvm-project/pull/162098
4. https://github.com/llvm/llvm-project/pull/162099
5. https://github.com/llvm/llvm-project/pull/156839
6. https://github.com/llvm/llvm-project/pull/156840
7. https://github.com/llvm/llvm-project/pull/156841
8. https://github.com/llvm/llvm-project/pull/156842
Commit: ecadd9073ac161a3c0ca77c62065098b1bf6461c
https://github.com/llvm/llvm-project/commit/ecadd9073ac161a3c0ca77c62065098b1bf6461c
Author: Marco Elver <elver at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CodeGenFunction.h
Log Message:
-----------
[Clang][CodeGen] Emit !alloc_token for new expressions (#162099)
[ Reland after 7815df19deaa ("[Clang] Fix brittle print-header-json.c test") ]
For new expressions, the allocated type is syntactically known and we
can trivially emit the !alloc_token metadata. A subsequent change will
wire up the AllocToken pass and introduce appropriate tests.
---
This change is part of the following series:
1. https://github.com/llvm/llvm-project/pull/160131
2. https://github.com/llvm/llvm-project/pull/156838
3. https://github.com/llvm/llvm-project/pull/162098
4. https://github.com/llvm/llvm-project/pull/162099
5. https://github.com/llvm/llvm-project/pull/156839
6. https://github.com/llvm/llvm-project/pull/156840
7. https://github.com/llvm/llvm-project/pull/156841
8. https://github.com/llvm/llvm-project/pull/156842
Commit: caacfffc71931797c85d8176ba7eb78195d4072f
https://github.com/llvm/llvm-project/commit/caacfffc71931797c85d8176ba7eb78195d4072f
Author: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M openmp/runtime/README.txt
Log Message:
-----------
[OpenMP] Add IBM Z as supported architecture in the runtime README
This architecture has been supported since
1111ef025762d9b7ecc3cafc576083987ae63fe6,
but the README file had not been updated.
Commit: 6ccb487392e6c6d16bc1f302d5215d5b87da0937
https://github.com/llvm/llvm-project/commit/6ccb487392e6c6d16bc1f302d5215d5b87da0937
Author: Marek Sedláček <mar3k.sedlacek at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
R llvm/test/Transforms/LoopRotate/multiple-deopt-exits.ll
R llvm/test/Transforms/LoopRotate/multiple-exits.ll
Log Message:
-----------
[LoopRotate] Remove canRotateDeoptimizingLatchExit and multi-rotate (#162482)
This patch removes canRotateDeoptimizingLatchExit check from loop roate
and connected multi rotation option for loop roate (-loop-rotate-multi
option).
The heuristic in canRotateDeoptimizingLatchExit returns true if any of
the loop exits are non-deoptimizing. This means if the loop has multiple
deopt exits, then without multi-rotate, we may still end up having deopt
exit at the latch. This multi-rotate option is introduced but it is off
by default.
We have not seen any improvements downstream as well, where
we have frequent number of deoptimizations in IR. Since the original
heuristic without the multi-rotate effectively ends up being "rotate
under some conditions", but the loop may still not be in the form we
want, we should remove the heuristic and multi-rotate framework entirely
Note that the diff is big, but it's just removal of while loop and
indentation change.
After this patch I would like to continue here and propose adding a
computability check for exit count, but that will be in a separate PR.
Requests for review: @annamthomas @fhahn @davemgreen
Co-authored-by: Marek Sedlacek <msedlacek at azul.com>
Commit: 348ffe8276c2fa0ea2f3df7ca449f4b2b49ec68b
https://github.com/llvm/llvm-project/commit/348ffe8276c2fa0ea2f3df7ca449f4b2b49ec68b
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M .github/workflows/release-asset-audit.py
Log Message:
-----------
[CI] Add dyung and c-rhodes to the Release Asset List (#162478)
We have a list of people authorized to create release assets to prevent
someone adding a release asset to a release without someone getting
alerted. Add dyung and c-rhodes now that they are also release managers.
Fixes #162463 (maybe after backport).
Commit: b7921f8292a9d7d18c472043ac3f0c2b5e20fd5f
https://github.com/llvm/llvm-project/commit/b7921f8292a9d7d18c472043ac3f0c2b5e20fd5f
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/Bitset.h
Log Message:
-----------
[ADT] Modernize Bitset (NFC) (#162430)
This patch modernizes BitWord and BITWORD_SIZE with "using" and
"static constexpr", respectively.
Commit: d6d0664da199d4f93d1d2ab1b68139b326d83e1e
https://github.com/llvm/llvm-project/commit/d6d0664da199d4f93d1d2ab1b68139b326d83e1e
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/docs/CFIVerify.rst
Log Message:
-----------
[llvm] Proofread CFIVerify.rst (#162431)
Commit: 0f3ca19483b1f1069144530badfbd66adc5c56b6
https://github.com/llvm/llvm-project/commit/0f3ca19483b1f1069144530badfbd66adc5c56b6
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/NVGPU/TransformOps/NVGPUTransformOps.cpp
M mlir/lib/Dialect/NVGPU/Transforms/MmaSyncTF32Transform.cpp
M mlir/lib/Dialect/NVGPU/Utils/MMAUtils.cpp
Log Message:
-----------
[NFC][MLIR][NVGPU] Cleanup namespace usage (#162158)
Eliminate `nvgpu::` prefix in several places.
Commit: 6c4bd66114bc3a284f45112cb2ba57de2aee4f7e
https://github.com/llvm/llvm-project/commit/6c4bd66114bc3a284f45112cb2ba57de2aee4f7e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Remove i32 and i16 from GPR register class. NFC (#162425)
Reduces RISCVGenDAGISel.inc by ~2000 bytes.
I had to adjust some casts to avoid a tablegen error about an immediate
being too large. The error was suppressed before because the type wasn't
"concrete" early enough.
Commit: 2690bb6db6ea583d402bb97ea44c5a1ff930ace7
https://github.com/llvm/llvm-project/commit/2690bb6db6ea583d402bb97ea44c5a1ff930ace7
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
A llvm/test/MC/AArch64/armv9a-sysp-diagnostics.s
Log Message:
-----------
[AArch64][llvm] Reject assembler for invalid TLBIP instructions (#162090)
Some invalid assembler is currently allowed for `tlbip` sys alias
instructions, since there's only a single table in tablegen for both
`tlbi` and `tlbip` instructions. However, the latter is only a subset of
the former, so invalid machine code is generated for `tlbip`
instructions which don't actually exist.
Define a `TLBI_and_TLBIP` and `TLBI_only` enum (wish tablegen had first
class enum support), so that only valid `tlbip` instructions are created
in the `TLBIPEntry` table, and instructions which are not valid are
correctly rejected. Add new testcases for this.
(See the Arm ARM DDI 0487 L.b pages C5-802 to 809 where valid `tlbi` and
`tlbip` instructions are defined).
For example, before this change, both of the following are accepted.
Subsequent to this change, `tlbip` is correctly rejected:
```
% llvm-mc -triple=aarch64 <<< "tlbi alle1" --show-encoding
tlbi alle1 // encoding: [0x9f,0x87,0x0c,0xd5]
% llvm-mc -triple=aarch64 -mattr=+d128 <<< "tlbip alle1, x0, x1"
<stdin>:1:7: error: invalid operand for TLBIP instruction
tlbip alle1
^
```
Commit: 8c9c91f3918087a1a84e60ac807434d01a41d4c1
https://github.com/llvm/llvm-project/commit/8c9c91f3918087a1a84e60ac807434d01a41d4c1
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M libc/startup/gpu/amdgpu/start.cpp
M libc/startup/gpu/nvptx/start.cpp
M llvm/tools/llvm-gpu-loader/amdhsa.cpp
M llvm/tools/llvm-gpu-loader/llvm-gpu-loader.h
M llvm/tools/llvm-gpu-loader/nvptx.cpp
Log Message:
-----------
[libc] Make GPU `_end` kernel only call exit callbacks (#162371)
Summary:
We use the infrastructure to stand up a pretend hosted environment on
the GPU. Part of that is calling exit codes and handling the callback.
Exiting from inside a GPU region is problematic as it actually relies on
a lot of GPU magic behind the scenes. This is at least *correct* now as
we use `quick_exit` on the CPU when the GPU calls `exit`. However,
calling `quick_exit` will interfere with instrumentation or benchmarking
that expects a nice teardown order. For normal execution we should do
the friendly option and let the loader utility clean everything up
manually.
Commit: a43fb2b11473a5f2025e016794243cba0c1e5ddd
https://github.com/llvm/llvm-project/commit/a43fb2b11473a5f2025e016794243cba0c1e5ddd
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-array-recipes-int.cpp
Log Message:
-----------
[OpenACC] Fix issue with array-section type generation (#162499)
When an array section bound was in a list of bound-types we improperly
generated the list of types of the bounds because
getPointeeOrElementType gets the LOWEST level of type (that is, digs
through ALL array types to get to the base-est of types) when what
we really wanted was 1 layer of pointer/array removed.
This patch fixes it and adds a test that showed the problem by
re-ordering the existing ones. This wasn't previously obvious by chance,
since the 'array-index-only' variants ended up generating the recipe,
and not the bounds.
Commit: 91f4db77b07368b47d32eb4d384fda2b2e5c9617
https://github.com/llvm/llvm-project/commit/91f4db77b07368b47d32eb4d384fda2b2e5c9617
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
A llvm/test/DebugInfo/X86/instr-ref-opt-bisect2.ll
Log Message:
-----------
[SDAG] Use useDebugInstrRef instead of shouldUseDebugInstrRef (#160686)
`shouldUseDebugInstrRef` can return different value than
`useDebugInstrRef`, since the first depends on opt level which can
change. Inconsistent usage can lead to errors later.
I believe that using `should...` instead of `use...` here is a result of
a minor error during this:
https://github.com/llvm/llvm-project/pull/94149/files#diff-8ec547e1244562c5837ed180dd9bed61b3cd960ef90bb6002ea2db41a67ed693
Notice how before the change `InstrRef` is assigned value from
`should...` *before* the opt change. Now, it's done after -- opt change
happens here:
```c
bool SelectionDAGISelLegacy::runOnMachineFunction(MachineFunction &MF) {
...
// Decide what flavour of variable location debug-info will be used, before
// we change the optimisation level.
MF.setUseDebugInstrRef(MF.shouldUseDebugInstrRef());
....
return Selector->runOnMachineFunction(MF);
}
```
Then `runOnMachineFunction` uses `should...`, which after opt change may
return different value than it did previously.
Commit: 0d6c5e088a777837215c22bac45f1df49604aec2
https://github.com/llvm/llvm-project/commit/0d6c5e088a777837215c22bac45f1df49604aec2
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M bolt/test/perf2bolt/AArch64/perf2bolt-spe.test
Log Message:
-----------
[BOLT][AArch64] Fix perf2bolt-spe test (#162312)
Lit recently started failing on some machines when using a subshell. The
test used a subshell to handle kernels where SPE's brstack option is
unavailable (<6.14), but it appears to work without it now.
Tested with perf 6.8 and 6.17.
Commit: 01ac00b6d7c678840f66c456bf37ada24f3d0427
https://github.com/llvm/llvm-project/commit/01ac00b6d7c678840f66c456bf37ada24f3d0427
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
R llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
Log Message:
-----------
AMDGPU: Render non-0 values for amdgpu-agpr-alloc
(#162300)
This now tries to compute a lower bound on the number of registers
for individual inline asm uses. Also starts using AACallEdges
to handling indirect calls.
Commit: 9ac8cd636808ef201860a40d0def37eec7caa0f3
https://github.com/llvm/llvm-project/commit/9ac8cd636808ef201860a40d0def37eec7caa0f3
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/unittests/BinaryFormat/DwarfTest.cpp
Log Message:
-----------
[llvm][Dwarf] Add DW_LNAME_ string/enum getters (#162434)
These are going to be used in a follow-up patch. And they are generally
useful for consumers (we have these for most other attributes).
Commit: 5200acc94aa720a2e5333f3934c4043990cef2a4
https://github.com/llvm/llvm-project/commit/5200acc94aa720a2e5333f3934c4043990cef2a4
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/CodeGen/dwarf-version.c
Log Message:
-----------
[clang][Driver] Add -gdwarf-6 option (#162454)
Now that we slowly started adding support for upcoming DWARFv6
attributes add `-gdwarf-6` as a supported flag.
Commit: 7cc1243f70ac6fdb5f45a81c9fe5e9a73653c8f6
https://github.com/llvm/llvm-project/commit/7cc1243f70ac6fdb5f45a81c9fe5e9a73653c8f6
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir
Log Message:
-----------
[MLIR][XeVM] Add XeVM 1D block operations to OpenCL calls conversion. (#161702)
XeVM 1D block load store operations are converted to OpenCL subgroup operations
described here:
https://registry.khronos.org/OpenCL/extensions/intel/cl_intel_subgroup_local_block_io.html
Commit: 6308cd871c955490575134e66da8a8d575674724
https://github.com/llvm/llvm-project/commit/6308cd871c955490575134e66da8a8d575674724
Author: Jackson Stogel <jtstogel at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M libc/src/__support/File/linux/lseekImpl.h
Log Message:
-----------
[libc] Fix integer overflow for large offsets in lseek. (#162394)
Currently, the return value `LIBC_NAMESPACE::syscall_impl<int>(SYS_lseek, fd, offset, whence)` will
overflow when seeking on files >4GB.
Commit: 497d648fcc096eff968cbfc32c37c96661d14158
https://github.com/llvm/llvm-project/commit/497d648fcc096eff968cbfc32c37c96661d14158
Author: weiwei chen <weiwei.chen at modular.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
Log Message:
-----------
[AMDGPU] Make sort ordering in `AMDGPURewriteAGPRCopyMFMAImpl::eliminateSpillsOfReassignedVGPRs()` strict weak. (#162493)
- [x] `sort` needs the comparator with strictly weak ordering, however
current logic doesn't meet the
[**Antisymmetry**](https://tanjim131.github.io/2020-05-22-strict-weak-ordering/#:~:text=Almost%20all%20C++%20STL%20containers,the%20person%20with%20greater%20height.)
requirement with
```
sort 0x561ecd3d3db0,0x561eaba91d10 25
weight 0.000000e+00,0.000000e+00
size 650370,662754
slot 732,733
```
Make the comparator logic strict weak order.
Fixes #162490
Commit: 750e64d07188dbb829c30489ef318ac8d6ce4869
https://github.com/llvm/llvm-project/commit/750e64d07188dbb829c30489ef318ac8d6ce4869
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/lib/Driver/ToolChains/UEFI.cpp
M clang/test/Driver/fuse-ld.c
M clang/test/Driver/uefi-constructed-args.c
Log Message:
-----------
[UEFI] Add driver path to program paths list (#162387)
UEFI toolchain driver implementation does not set the path where tools
such as lld-link can be found. This patch fixes that.
Commit: 0c087bd4f9157fd2677850ee22be55dff03bc1f7
https://github.com/llvm/llvm-project/commit/0c087bd4f9157fd2677850ee22be55dff03bc1f7
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
A mlir/test/Dialect/OpenACC/pointer-like-interface-alloc.mlir
A mlir/test/Dialect/OpenACC/pointer-like-interface-copy.mlir
A mlir/test/Dialect/OpenACC/pointer-like-interface-free.mlir
M mlir/test/lib/Dialect/CMakeLists.txt
A mlir/test/lib/Dialect/OpenACC/CMakeLists.txt
A mlir/test/lib/Dialect/OpenACC/TestOpenACC.cpp
A mlir/test/lib/Dialect/OpenACC/TestPointerLikeTypeInterface.cpp
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir][acc] Extend PointerLikeType to provide alloc, dealloc, copy (#162328)
A variable in an acc data clause operation must have a type that
implements either PointerLikeType or a MappableType interface. These
interfaces provide the contract that allows acc dialect and its
transform passes to interact with a source dialect.
One of these requirements is ability to generate code that creates
memory for a private copy and ability to initialize that copy from
another variable. Thus, update the PointerLikeType API to provide the
means to create allocation, deallocation, and copy. This will be used as
a way to fill in privatization and firstprivatization recipes.
This new API was implemented for memref along with testing to exercise
it via the implementation of a testing pass.
Commit: 6cba572d9efefa433a18540f71fefb1392ffea2a
https://github.com/llvm/llvm-project/commit/6cba572d9efefa433a18540f71fefb1392ffea2a
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/unittests/CodeGen/InstrRefLDVTest.cpp
M llvm/unittests/CodeGen/LexicalScopesTest.cpp
M llvm/unittests/CodeGen/MachineBasicBlockTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/DebugInfoTest.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/IR/VerifierTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
Log Message:
-----------
[llvm][DebugInfo][NFC] Abstract DICompileUnit::SourceLanguage to allow alternate DWARF SourceLanguage encoding (#162255)
This patch sets up `DICompileUnit` to support the DWARFv6
`DW_AT_language_name` and `DW_AT_language_version` attributes (which are
set to replace `DW_AT_language`). This patch changes the
`DICompileUnit::SourceLanguage` field type to a `DISourceLanguageName`
that encapsulates the notion of "versioned vs. unversioned name". A
"versioned" name is one that has an associated version stored separately
in `DISourceLanguageName::Version`.
This patch just changes all the clients of the `getSourceLanguage` API
to the expect a `DISourceLanguageName`. Currently they all just `assert`
(via `DISourceLanguageName::getUnversionedName`) that we're dealing with
"unversioned names" (i.e., the pre-DWARFv6 language codes). In follow-up
patches (e.g., draft is at
https://github.com/llvm/llvm-project/pull/162261), when we start
emitting versioned language codes, the `getUnversionedName` calls can
then be adjusted to `getName`.
**Implementation considerations**
* We could have added a new member to `DICompileUnit` alongside the
existing `SourceLanguage` field. I don't think this would have made the
transition any simpler (clients would still need to be aware of
"versioned" vs. "unversioned" language names). I felt that encapsulating
this inside a `DISourceLanguageName` was easier to reason about for
maintainers.
* Currently DISourceLanguageName is a `12` byte structure. We could
probably pack all the info inside a `uint64_t` (16-bits for the name,
32-bits for the version, 1-bit for answering the `hasVersionedName`).
Just to keep the prototype simple I used a `std::optional`. But since
the guts of the structure are hidden, we can always change the layout to
a more compact representation instead.
**How to review**
* The new `DISourceLanguageName` structure is defined in
`DebugInfoMetadata.h`. All the other changes fall out from changing the
`DICompileUnit::SourceLanguage` from `unsigned` to
`DISourceLanguageName`.
Commit: 030d8e66498d6818300b1a8678861a016bd37e10
https://github.com/llvm/llvm-project/commit/030d8e66498d6818300b1a8678861a016bd37e10
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/unittests/BinaryFormat/DwarfTest.cpp
Log Message:
-----------
[llvm][Dwarf] Add LanguageDescription API that accounts for version (#162048)
Currently `llvm::dwarf::LanguageDescription` returns a stringified
`DW_LNAME`. It would be useful to have an API that returns the language
name for a particular `DW_LNAME_`/version pair. LLDB's use case is that
it wants to emit diagnostics with human readable descriptions of the
language we got from debug-info (see
https://github.com/llvm/llvm-project/pull/161688). We could maintain a
side-table in LLDB but thought this might be generally useful and should
live next to the existing `LanguageDescription` API.
Commit: eb1ce38fd1fc750080a0ee5fe1e16dd457d9c437
https://github.com/llvm/llvm-project/commit/eb1ce38fd1fc750080a0ee5fe1e16dd457d9c437
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/global-init.cpp
Log Message:
-----------
[CIR] Finish global ctor init lowering (#162130)
Implement support for creating a global ctor list during the
cir::LoweringPrepare pass, and add tests for lowering global
constructor-based initialization to LLVM IR.
Commit: 98ce4348703dbb2e2386426ff7e67c2e025d4bfb
https://github.com/llvm/llvm-project/commit/98ce4348703dbb2e2386426ff7e67c2e025d4bfb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
[VPlan] Skip VPBlendRecipe in isUsedByLoadStoreAddress.
VPBlendRecipes are introduced as part of if-conversion, potentially adding
a def-use chain from a load used in a compare to another load/store. In
the scalar IR, there is no connection via def-use chains, so the legacy
cost model won't consider the load used by memory operation.
Skipping blends brings the VPlan-based cost-computation in line with the
legacy cost model after https://github.com/llvm/llvm-project/pull/162157.
Commit: 466f691f965a5d4a78fef7560377b0a478636d6e
https://github.com/llvm/llvm-project/commit/466f691f965a5d4a78fef7560377b0a478636d6e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/lib/Support/SpecialCaseList.cpp
M llvm/unittests/Support/SpecialCaseListTest.cpp
Log Message:
-----------
[SpecialCaseList] Remove ./ from file path (#162437)
This extends approach used in WarningsSpecialCaseList
on other types of SpecialCaseList.
SpecialCaseList will remove leading "./" from the Query
for prefixes which looks like file names.
Now affected prefixes are "src", "!src", "mainfile", "source".
To avoid breaking users, this behavior is enabled for
files starting "#!special-case-list-v3".
Commit: 8e62acec9e0228118e2a5a982ca2eaa7b213a049
https://github.com/llvm/llvm-project/commit/8e62acec9e0228118e2a5a982ca2eaa7b213a049
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M lldb/source/Core/IOHandler.cpp
M lldb/test/API/driver/quit_speed/TestQuitWithProcess.py
Log Message:
-----------
[lldb] Ignore trailing spaces on quit confirmation (#162263)
Commit: b8beb97b4f577f87f204be78b77ee12e7e232340
https://github.com/llvm/llvm-project/commit/b8beb97b4f577f87f204be78b77ee12e7e232340
Author: Aaron Ballman <aaron at aaronballman.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M clang/www/c_status.html
Log Message:
-----------
Add papers from the Aug 2025 WG14 meeting in Brno; NFC
Commit: a6bcaf2561f4cdcbe9d36616737d7b8306b0eb5f
https://github.com/llvm/llvm-project/commit/a6bcaf2561f4cdcbe9d36616737d7b8306b0eb5f
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M .github/workflows/release-asset-audit.py
A bolt/docs/PacRetDesign.md
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlus.h
M bolt/include/bolt/Core/MCPlusBuilder.h
A bolt/include/bolt/Passes/InsertNegateRAStatePass.h
A bolt/include/bolt/Passes/MarkRAStates.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryBasicBlock.cpp
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/Exceptions.cpp
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/lib/Passes/CMakeLists.txt
A bolt/lib/Passes/InsertNegateRAStatePass.cpp
A bolt/lib/Passes/MarkRAStates.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
A bolt/test/AArch64/negate-ra-state-disallow.s
A bolt/test/AArch64/negate-ra-state-incorrect.s
A bolt/test/AArch64/negate-ra-state-reorder.s
A bolt/test/AArch64/negate-ra-state.s
A bolt/test/AArch64/pacret-split-funcs.s
M bolt/test/perf2bolt/AArch64/perf2bolt-spe.test
A bolt/test/runtime/AArch64/negate-ra-state.cpp
A bolt/test/runtime/AArch64/pacret-function-split.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-pointer-as-pointers.cpp
M clang/docs/OpenMPSupport.rst
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Options.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACC.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/UEFI.cpp
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512vlbwintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/mmintrin.h
M clang/lib/Headers/tmmintrin.h
M clang/lib/Sema/SemaARM.cpp
M clang/test/CIR/CodeGen/global-init.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-array-recipes-int.cpp
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_rax1.c
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512vlbw-builtins.c
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/X86/ssse3-builtins.c
M clang/test/CodeGen/dwarf-version.c
M clang/test/Driver/fuse-ld.c
M clang/test/Driver/uefi-constructed-args.c
M clang/test/Preprocessor/print-header-json.c
A clang/test/Sema/AArch64/arm_sme_streaming_compatible_sme.c
A clang/test/Sema/AArch64/arm_sme_streaming_compatible_sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_LP_sme-f16f16_OR_sme-f8f16_RP.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-b16b16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f64f64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f8f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-f8f32.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-i16i64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme-lutv2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-f64f64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-i16i64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-b16b16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f64f64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f8f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-f8f32.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-mop4_AND_sme-i16i64.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-b16b16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-f8f16.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2_AND_sme-tmop_AND_sme-f8f32.c
A clang/test/Sema/AArch64/arm_sme_streaming_only_sme_AND_sme2p1.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p1_OR_sme2_RP___sme_AND_LP_sve2p1_OR_sme2_RP.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p1_OR_sme2p1_RP___sme_AND_LP_sve2p1_OR_sme2p1_RP.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_LP_sve2p1_OR_sme_RP___sme.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_bf16___sme_AND_bf16.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_i8mm___sme_AND_i8mm.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-aes___sme_AND_ssve-aes.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-b16b16___sme_AND_sme2_AND_sve-b16b16.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-bitperm___sme_AND_ssve-bitperm.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve-sha3___sme_AND_sve-sha3_AND_sme2p1.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_faminmax___sme_AND_sme2_AND_faminmax.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8___sme_AND_sme2_AND_fp8.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8dot2___sme_AND_ssve-fp8dot2.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8dot4___sme_AND_ssve-fp8dot4.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_fp8fma___sme_AND_ssve-fp8fma.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2_AND_lut___sme_AND_sme2_AND_lut.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2___sme.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve_AND_sve2p1___sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme_AND_sme2_AND_ssve-fexpa.c
A clang/test/Sema/AArch64/arm_sve_feature_dependent_sve___sme_AND_sme2p2.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_bf16.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_f32mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_f64mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_i8mm.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve-sm4.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2.c
A clang/test/Sema/AArch64/arm_sve_non_streaming_only_sve_AND_sve2p1.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme-f16f16.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2_AND_faminmax.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2_AND_fp8.c
A clang/test/Sema/AArch64/arm_sve_streaming_only_sme_AND_sme2_AND_sve-b16b16.c
R clang/test/Sema/aarch64-streaming-sme-or-nonstreaming-sve-builtins.c
M clang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
M clang/utils/TableGen/SveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
A clang/utils/aarch64_builtins_test_generator.py
M clang/www/c_status.html
M compiler-rt/lib/orc/coff_platform.cpp
M compiler-rt/lib/orc/coff_platform.h
M compiler-rt/lib/orc/dlfcn_wrapper.cpp
M flang-rt/lib/runtime/character.cpp
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
M flang/test/Examples/omp-atomic.f90
M flang/test/Examples/omp-declarative-directive.f90
M flang/test/Examples/omp-device-constructs.f90
M flang/test/Examples/omp-in-reduction-clause.f90
M flang/test/Examples/omp-nowait.f90
M flang/test/Examples/omp-order-clause.f90
M flang/test/Examples/omp-sections.f90
M flang/test/HLFIR/declare-codegen.fir
M flang/test/HLFIR/invalid.fir
M libc/config/linux/app.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/in_addr.h
A libc/include/llvm-libc-types/in_addr_t.h
M libc/src/__support/File/linux/lseekImpl.h
M libc/src/__support/OSUtil/linux/CMakeLists.txt
A libc/src/__support/OSUtil/linux/auxv.h
M libc/src/__support/threads/callonce.h
M libc/src/__support/threads/linux/CMakeLists.txt
R libc/src/__support/threads/linux/callonce.cpp
M libc/src/__support/threads/linux/callonce.h
M libc/src/pthread/pthread_once.cpp
M libc/src/sys/auxv/linux/CMakeLists.txt
M libc/src/sys/auxv/linux/getauxval.cpp
M libc/src/threads/call_once.cpp
M libc/startup/gpu/amdgpu/start.cpp
M libc/startup/gpu/nvptx/start.cpp
M libc/startup/linux/CMakeLists.txt
M libc/startup/linux/do_start.cpp
M lld/wasm/InputChunks.cpp
M lldb/packages/Python/lldbsuite/test/gdbclientutils.py
M lldb/source/Core/IOHandler.cpp
M lldb/source/Target/Language.cpp
M lldb/test/API/driver/quit_speed/TestQuitWithProcess.py
M lldb/unittests/Target/LanguageTest.cpp
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/CFIVerify.rst
M llvm/include/llvm/ADT/Bitset.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/Support/SpecialCaseList.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Transforms/Utils/SimplifyCFGOptions.h
M llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/ExecutionEngine/Orc/LLJIT.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/SpecialCaseList.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
M llvm/lib/Target/SPIRV/SPIRVEmitNonSemanticDI.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizeImplicitBinding.cpp
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-fconstant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp16-fconstant.mir
M llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll
M llvm/test/CodeGen/AArch64/f16-instructions.ll
M llvm/test/CodeGen/AArch64/fcvt-fixed.ll
M llvm/test/CodeGen/AArch64/fdiv-combine.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd-strict.ll
M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmul-strict.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-attributor-min-agpr-alloc.ll
R llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
M llvm/test/CodeGen/AMDGPU/fsub.ll
M llvm/test/CodeGen/AMDGPU/mad_int24.ll
M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomic-cmpxchg-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir
M llvm/test/CodeGen/SPARC/atomicrmw-uinc-udec-wrap.ll
A llvm/test/CodeGen/SPARC/atomics-ordering.ll
A llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/CodeGen/X86/ptrtoaddr-fast-isel.ll
A llvm/test/DebugInfo/X86/instr-ref-opt-bisect2.ll
A llvm/test/MC/AArch64/armv9a-sysp-diagnostics.s
M llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s
M llvm/test/MC/AMDGPU/gfx1250_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_valu_lit64.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop2_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_sop2.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopc.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
M llvm/test/MC/AMDGPU/gfx950-unsupported.s
M llvm/test/MC/AMDGPU/literals.s
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
M llvm/test/MC/AMDGPU/vop3-literal.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_salu_lit64.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_valu_lit64.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopc.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/Other/new-pm-print-pipeline.ll
M llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
A llvm/test/Transforms/GVN/ptrtoaddr.ll
A llvm/test/Transforms/InstCombine/fold-selective-shift.ll
R llvm/test/Transforms/LoopRotate/multiple-deopt-exits.ll
R llvm/test/Transforms/LoopRotate/multiple-exits.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/scalable-predication.ll
A llvm/test/Transforms/NewGVN/ptrtoaddr.ll
A llvm/test/Transforms/PhaseOrdering/switch-to-arithmetic-inlining.ll
M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
M llvm/test/Transforms/SimplifyCFG/switch-transformations-no-lut.ll
M llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s
M llvm/tools/llvm-gpu-loader/amdhsa.cpp
M llvm/tools/llvm-gpu-loader/llvm-gpu-loader.h
M llvm/tools/llvm-gpu-loader/nvptx.cpp
M llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
M llvm/unittests/BinaryFormat/DwarfTest.cpp
M llvm/unittests/CodeGen/InstrRefLDVTest.cpp
M llvm/unittests/CodeGen/LexicalScopesTest.cpp
M llvm/unittests/CodeGen/MachineBasicBlockTest.cpp
M llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
M llvm/unittests/IR/DebugInfoTest.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/IR/VerifierTest.cpp
M llvm/unittests/Support/SpecialCaseListTest.cpp
M llvm/unittests/Transforms/Utils/CloningTest.cpp
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/Linalg/IR/LinalgRelayoutOps.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Interfaces/RuntimeVerifiableOpInterface.td
M mlir/include/mlir/Transforms/Passes.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/Linalg/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/NVGPU/TransformOps/NVGPUTransformOps.cpp
M mlir/lib/Dialect/NVGPU/Transforms/MmaSyncTF32Transform.cpp
M mlir/lib/Dialect/NVGPU/Utils/MMAUtils.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/Tensor/Transforms/RuntimeOpVerification.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Interfaces/RuntimeVerifiableOpInterface.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Transforms/GenerateRuntimeVerification.cpp
M mlir/test/Conversion/ConvertToEmitC/tosa.mlir
A mlir/test/Conversion/SCFToEmitC/while.mlir
M mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-out-params.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/Linalg/decompose-pack.mlir
M mlir/test/Dialect/Linalg/runtime-verification.mlir
A mlir/test/Dialect/OpenACC/pointer-like-interface-alloc.mlir
A mlir/test/Dialect/OpenACC/pointer-like-interface-copy.mlir
A mlir/test/Dialect/OpenACC/pointer-like-interface-free.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
A mlir/test/Target/Cpp/do.mlir
M mlir/test/Transforms/buffer-results-to-out-params-add-result-attr.mlir
M mlir/test/Transforms/buffer-results-to-out-params-hosit-static-allocs.mlir
M mlir/test/Transforms/buffer-results-to-out-params.mlir
M mlir/test/lib/Dialect/CMakeLists.txt
A mlir/test/lib/Dialect/OpenACC/CMakeLists.txt
A mlir/test/lib/Dialect/OpenACC/TestOpenACC.cpp
A mlir/test/lib/Dialect/OpenACC/TestPointerLikeTypeInterface.cpp
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
M openmp/runtime/README.txt
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
Log Message:
-----------
rebase
Created using spr 1.3.6
Compare: https://github.com/llvm/llvm-project/compare/b9d1dcddec20...a6bcaf2561f4
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