[all-commits] [llvm/llvm-project] 6267e7: Bazel: fix after "[llvm-driver] Remove llvm-profda...

Tue Oct 7 20:55:35 PDT 2025

  Branch: refs/heads/users/vitalybuka/spr/nfcspecialcaselist-use-bumpptrallocator-to-own-strings
  Home:   https://github.com/llvm/llvm-project
  Commit: 6267e7176d0225bb79ec1456aa66b7041b694e11
      https://github.com/llvm/llvm-project/commit/6267e7176d0225bb79ec1456aa66b7041b694e11
  Author: James Y Knight <jyknight at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
    M utils/bazel/llvm-project-overlay/llvm/driver.bzl

  Log Message:
  -----------
  Bazel: fix after "[llvm-driver] Remove llvm-profdata from the driver (#162191)"

  Commit: 2f4275b195af536dd81f9eb0dee17169a5a3063b
      https://github.com/llvm/llvm-project/commit/2f4275b195af536dd81f9eb0dee17169a5a3063b
  Author: James Y Knight <jyknight at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

  Log Message:
  -----------
  AMDGPU: skip AMDGPUAttributor and AMDGPUImageIntrinsicOptimizerPass on R600. (#162207)

These passes call `getSubtarget<GCNSubtarget>`, which doesn't work on
R600 targets, as that uses an `R600Subtarget` type, instead.
Unfortunately, `TargetMachine::getSubtarget<ST>` does an unchecked
static_cast to `ST&`, which makes it easy for this error to go
undetected.

The modifications here were verified by running check-llvm with an
assert added to getSubtarget. However, that asssert requires that RTTI
is enabled, which LLVM doesn't use, so I've reverted the assert before
sending this fix upstream.

These errors have been present for some time, but were detected after
#162040 caused an uninitialized memory read to be reported by asan/msan.

  Commit: 051fa18cb4e3dd69754e0f6e0c5733960c0aaa60
      https://github.com/llvm/llvm-project/commit/051fa18cb4e3dd69754e0f6e0c5733960c0aaa60
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-10-08 (Wed, 08 Oct 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
    M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
    M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
    M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
    M llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll
    M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
    M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
    M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
    M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll

  Log Message:
  -----------
  AMDGPU: Stop inferring amdgpu-agpr-alloc on irrelevant targets (#161957)

This only matters for subtargets with configurable AGPR allocation.

  Commit: 278a99e8e9f0baf17b99f4989d2bfa3777fa4d6f
      https://github.com/llvm/llvm-project/commit/278a99e8e9f0baf17b99f4989d2bfa3777fa4d6f
  Author: Mircea Trofin <mtrofin at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
    M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll
    M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
    M llvm/utils/profcheck-xfail.txt

  Log Message:
  -----------
  [DFAJT][profcheck] Propagate `select` -> `br` profile metadata (#162213)

Issue #147390

  Commit: 93097b2d47c87bf5eee0a2612d961c7a01831eab
      https://github.com/llvm/llvm-project/commit/93097b2d47c87bf5eee0a2612d961c7a01831eab
  Author: Maksim Levental <maksim.levental at gmail.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .ci/all_requirements.txt
    M mlir/cmake/modules/AddMLIRPython.cmake
    M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
    M mlir/docs/Dialects/Linalg/OpDSL.md
    M mlir/examples/standalone/pyproject.toml
    M mlir/examples/standalone/python/CMakeLists.txt
    A mlir/examples/standalone/python/StandaloneExtensionPybind11.cpp
    A mlir/examples/standalone/python/mlir_standalone/dialects/standalone_pybind11.py
    M mlir/examples/standalone/test/python/smoketest.py
    A mlir/include/mlir/Bindings/Python/PybindAdaptors.h
    M mlir/python/CMakeLists.txt
    M mlir/python/mlir/dialects/python_test.py
    M mlir/python/requirements.txt
    M mlir/test/python/dialects/python_test.py
    M mlir/test/python/lib/CMakeLists.txt
    A mlir/test/python/lib/PythonTestModulePybind11.cpp
    M mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  Revert "[MLIR][Python] use `FetchContent_Declare` for nanobind and remove pybind (#161230)" (#162309)

This reverts commit 84a214856ad989f37af19f5e8aaa9ec2346dde6f.

This gives us more time to work out the alternative and also people to
migrate

  Commit: a280db60c8cc8f10225fee3e2385ff1704528b6e
      https://github.com/llvm/llvm-project/commit/a280db60c8cc8f10225fee3e2385ff1704528b6e
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
    M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/minmax.ll

  Log Message:
  -----------
  [AMDGPU] Use true16 loads with +real-true16 and sram-ecc (#161256)

When sram-ecc is enabled 16-bit loads clobber full 32-bit VGPR.
A load into a just 16-bit VGPR is not possible. Do a 16-bit
extending load and extract a 16-bit subreg in this situation.

Also fixes lack of 16-bit store patterns with this combination.

Fixes: SC1-6072

  Commit: f43721a4185c75b2800e59c102778916dca31c5c
      https://github.com/llvm/llvm-project/commit/f43721a4185c75b2800e59c102778916dca31c5c
  Author: Andrey Ali Khan Bolshakov <bolsh.andrey at yandex.ru>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/AST/DeclPrinter.cpp
    M clang/test/AST/ast-print-record-decl.c
    M clang/unittests/AST/DeclPrinterTest.cpp

  Log Message:
  -----------
  [clang][AST] Pretty-print default template template args (#162134)

  Commit: 09f0f38f3622eacf4320ba5ac28972012d1e818c
      https://github.com/llvm/llvm-project/commit/09f0f38f3622eacf4320ba5ac28972012d1e818c
  Author: jiang1997 <jieke at live.cn>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp
    M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
    M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
    M clang/lib/CIR/CodeGen/CIRGenFunction.h
    M clang/test/CIR/CodeGen/new.cpp

  Log Message:
  -----------
  [CIR] Add limited support for array new (#161095)

This change adds initial support for array new expressions where the
array size is constant and the element does not require a cookie.

Ported from ClangIR incubator PR [#1286
](https://github.com/llvm/clangir/pull/1286).
This is the first PR in a series intended to close #160383.

  Commit: f0ae4b3bd2daac4ba5aea616b9481e59e0b63293
      https://github.com/llvm/llvm-project/commit/f0ae4b3bd2daac4ba5aea616b9481e59e0b63293
  Author: James Y Knight <jyknight at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
    M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel

  Log Message:
  -----------
  Bazel: fix after "[Offload] Rename and move clang-offload-packager -> llvm-offload-binary (#161438)"

  Commit: a0668a4915f70a920e0e691df5f4cf0946146b4a
      https://github.com/llvm/llvm-project/commit/a0668a4915f70a920e0e691df5f4cf0946146b4a
  Author: Andy Kaylor <akaylor at nvidia.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
    M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    A clang/test/CIR/IR/dynamic-cast.cir
    A clang/test/CIR/IR/invalid-dyn-cast.cir

  Log Message:
  -----------
  [CIR] Upstream DynamicCastOp (#161734)

This adds the dialect handling for CIR_DynamicCastOp and
CIR_DynamicCastInfoAttr. Support for generating these operations from
source will be added in a later change.

  Commit: f015c7fababe25766b5108adc392826969524658
      https://github.com/llvm/llvm-project/commit/f015c7fababe25766b5108adc392826969524658
  Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/include/llvm/ADT/EquivalenceClasses.h

  Log Message:
  -----------
  [NFC] Typo in EquivalenceClasses.h: determinstic->deterministic (#162314)

  Commit: ea02eda911960623bc6f79796e7757439ffdfa3b
      https://github.com/llvm/llvm-project/commit/ea02eda911960623bc6f79796e7757439ffdfa3b
  Author: Thurston Dang <thurston at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp

  Log Message:
  -----------
  [sanitizer][test] Print result in getpwnam_r_invalid_user.cpp (#162217)

This test has been flaky failing on sanitizer-ppc64le-linux since at
least 9 days ago
(https://lab.llvm.org/buildbot/#/builders/72/builds/15257), but the
exact cause is unclear because the only output is that `assert(res == 0
|| res == ENOENT);` failed.

To aid debugging, this patch prints out the result of the `getpwnam_r`
call.

  Commit: 3fca16eee05f4ea5694755f83cf7cfb19f597b88
      https://github.com/llvm/llvm-project/commit/3fca16eee05f4ea5694755f83cf7cfb19f597b88
  Author: Anchu Rajendran S <asudhaku at amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M flang/test/Lower/OpenMP/atomic-control-options.f90

  Log Message:
  -----------
  [flang][mlir] Cleaning up the atomic-control testcase (#162149)

The testcase tests atomicupdate header which is not required for testing
atomic control attributes. This induces failures due to unrelated
changes (like changes in atomic update clauses). This PR removes the
unrelated test to keep it minimal.

  Commit: 88d9f699530c7c349ae266faad47687da2ee745e
      https://github.com/llvm/llvm-project/commit/88d9f699530c7c349ae266faad47687da2ee745e
  Author: Rahul Joshi <rjoshi at nvidia.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/include/llvm/Analysis/HeatUtils.h
    M llvm/lib/Analysis/HeatUtils.cpp

  Log Message:
  -----------
  [NFC][LLVM] Code cleanup in Analysis/HeatUtils (#162283)

Follow LLVM Coding Standards for variable names, and remove `namespace
llvm` surrounding all the code.

  Commit: 3b14414cbdb8bd37ff861862a99a47104b87765b
      https://github.com/llvm/llvm-project/commit/3b14414cbdb8bd37ff861862a99a47104b87765b
  Author: nerix <nerixdev at outlook.de>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
    M lldb/test/Shell/SymbolFile/NativePDB/break-by-function.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/break-by-line.cpp
    A lldb/test/Shell/SymbolFile/NativePDB/c-calling-conventions.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/stack_unwinding01.cpp
    M lldb/test/Shell/SymbolFile/PDB/function-nested-block.test
    M lldb/test/Shell/SymbolFile/PDB/variables.test

  Log Message:
  -----------
  Reland "[LLDB][NativePDB] Create functions with mangled name" (#161678)

Relands #149701 which was reverted in
https://github.com/llvm/llvm-project/commit/185ae5cdc695248b58ae017508cc764c19bee5b7
because it broke demangling of Itanium symbols on i386.

The last commit in this PR adds the fix for this (discussed in #160930).
On x86 environments, the prefix of `__cdecl` functions will now be
removed to match DWARF. I opened #161676 to discuss this for the other
calling conventions.

  Commit: 675be0df29d305edd6137de7efcb85035028f731
      https://github.com/llvm/llvm-project/commit/675be0df29d305edd6137de7efcb85035028f731
  Author: Nico Weber <thakis at chromium.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/utils/gn/secondary/clang/test/BUILD.gn
    M llvm/utils/gn/secondary/llvm/test/BUILD.gn
    A llvm/utils/gn/secondary/llvm/tools/llvm-offload-binary/BUILD.gn

  Log Message:
  -----------
  [gn] port 2499fe1ac40f (llvm-offload-binary)

2499fe1ac40f did remove clang-offload-packager from the GN build,
but it didn't add the new tool. This commit does that.

  Commit: 6bbd7eaf0aa0b75b73d843d9f56ab6d7226018ef
      https://github.com/llvm/llvm-project/commit/6bbd7eaf0aa0b75b73d843d9f56ab6d7226018ef
  Author: Utkarsh Saxena <usx at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/include/clang/Analysis/Analyses/LifetimeSafety.h
    M clang/lib/Analysis/LifetimeSafety.cpp
    A clang/lib/Analysis/LifetimeSafety.md
    M clang/test/Analysis/LifetimeSafety/benchmark.py
    M clang/test/Sema/warn-lifetime-safety.cpp
    M clang/unittests/Analysis/LifetimeSafetyTest.cpp

  Log Message:
  -----------
  [LifetimeSafety] Introduce a liveness-based lifetime policy (#159991)

This PR replaces the forward `ExpiredLoansAnalysis` with a backward
`LiveOriginAnalysis` that tracks which origins are live at each program
point, along with confidence levels (Definite or Maybe). The new
approach:

- Tracks liveness of origins rather than expiration of loans
- Uses a backward dataflow analysis to determine which origins are live
at each point.
- Provides more precise confidence levels for use-after-free warnings
and avoids previous false-positives

The `LifetimeChecker` now checks for use-after-free by examining if an
origin is live when a loan expires, rather than checking if a loan is
expired when an origin is used.

More details describing the design flaw in using `ExpiredLoans` is
mentioned in
https://github.com/llvm/llvm-project/issues/156959#issuecomment-3281917701

Fixes: https://github.com/llvm/llvm-project/issues/156959

(With this, we can build LLVM with no false-positives 🎉 )

<details>

<summary>
Benchmark report
</summary>

# Lifetime Analysis Performance Report
> Generated on: 2025-09-24 13:08:03 

---

## Test Case: Pointer Cycle in Loop

**Timing Results:**

| N (Input Size) | Total Time | Analysis Time (%) | Fact Generator (%) |
Loan Propagation (%) | Live Origins (%) |

|:---------------|-----------:|------------------:|-------------------:|---------------------:|------------------:|
| 50 | 54.12 ms | 80.80% | 0.00% | 80.42% | 0.00% |
| 75 | 150.22 ms | 91.54% | 0.00% | 91.19% | 0.00% |
| 100 | 317.12 ms | 94.90% | 0.00% | 94.77% | 0.00% |
| 200 | 2.40 s | 98.58% | 0.00% | 98.54% | 0.03% |
| 300 | 9.85 s | 99.25% | 0.00% | 99.24% | 0.01% |

**Complexity Analysis:**

| Analysis Phase    | Complexity O(n<sup>k</sup>) | 
|:------------------|:--------------------------|
| Total Analysis    | O(n<sup>3.47</sup> ± 0.06) |
| FactGenerator     | (Negligible)              |
| LoanPropagation   | O(n<sup>3.47</sup> ± 0.06) |
| LiveOrigins       | (Negligible)              |

---

## Test Case: CFG Merges

**Timing Results:**

| N (Input Size) | Total Time | Analysis Time (%) | Fact Generator (%) |
Loan Propagation (%) | Live Origins (%) |

|:---------------|-----------:|------------------:|-------------------:|---------------------:|------------------:|
| 400 | 105.22 ms | 72.61% | 0.68% | 71.38% | 0.52% |
| 1000 | 610.74 ms | 88.88% | 0.33% | 88.32% | 0.23% |
| 2000 | 2.50 s | 95.32% | 0.21% | 94.99% | 0.11% |
| 5000 | 17.20 s | 98.20% | 0.14% | 98.01% | 0.05% |

**Complexity Analysis:**

| Analysis Phase    | Complexity O(n<sup>k</sup>) | 
|:------------------|:--------------------------|
| Total Analysis    | O(n<sup>2.14</sup> ± 0.00) |
| FactGenerator     | O(n<sup>1.59</sup> ± 0.05) |
| LoanPropagation   | O(n<sup>2.14</sup> ± 0.00) |
| LiveOrigins       | O(n<sup>1.19</sup> ± 0.04) |

---

## Test Case: Deeply Nested Loops

**Timing Results:**

| N (Input Size) | Total Time | Analysis Time (%) | Fact Generator (%) |
Loan Propagation (%) | Live Origins (%) |

|:---------------|-----------:|------------------:|-------------------:|---------------------:|------------------:|
| 50 | 141.95 ms | 91.14% | 0.00% | 90.99% | 0.00% |
| 100 | 1.09 s | 98.17% | 0.00% | 98.13% | 0.00% |
| 150 | 3.87 s | 99.28% | 0.00% | 99.27% | 0.00% |
| 200 | 9.81 s | 99.61% | 0.00% | 99.60% | 0.00% |

**Complexity Analysis:**

| Analysis Phase    | Complexity O(n<sup>k</sup>) | 
|:------------------|:--------------------------|
| Total Analysis    | O(n<sup>3.23</sup> ± 0.02) |
| FactGenerator     | (Negligible)              |
| LoanPropagation   | O(n<sup>3.23</sup> ± 0.02) |
| LiveOrigins       | (Negligible)              |

---

## Test Case: Switch Fan-out

**Timing Results:**

| N (Input Size) | Total Time | Analysis Time (%) | Fact Generator (%) |
Loan Propagation (%) | Live Origins (%) |

|:---------------|-----------:|------------------:|-------------------:|---------------------:|------------------:|
| 500 | 155.10 ms | 72.03% | 0.47% | 67.49% | 4.06% |
| 1000 | 568.40 ms | 85.60% | 0.24% | 80.53% | 4.83% |
| 2000 | 2.25 s | 93.00% | 0.13% | 86.99% | 5.88% |
| 4000 | 9.06 s | 96.62% | 0.10% | 89.68% | 6.84% |

**Complexity Analysis:**

| Analysis Phase    | Complexity O(n<sup>k</sup>) | 
|:------------------|:--------------------------|
| Total Analysis    | O(n<sup>2.07</sup> ± 0.01) |
| FactGenerator     | O(n<sup>1.52</sup> ± 0.13) |
| LoanPropagation   | O(n<sup>2.06</sup> ± 0.01) |
| LiveOrigins       | O(n<sup>2.23</sup> ± 0.00) |

---

<details>

  Commit: d09d63a7d53a0cda602944c5336ad8b8c10cd687
      https://github.com/llvm/llvm-project/commit/d09d63a7d53a0cda602944c5336ad8b8c10cd687
  Author: Joseph Huber <huberjn at outlook.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll
    M llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp

  Log Message:
  -----------
  [Offload] Let binary utility take empty arguments (#162317)

Summary:
There's no real reason to restrict people if they don't want to use
`triple`. It's important for the normal pipeline but I can see people
using these for other purposes.

  Commit: c16d25282e7169cb8a19d9fa385cf7220dd65ac5
      https://github.com/llvm/llvm-project/commit/c16d25282e7169cb8a19d9fa385cf7220dd65ac5
  Author: nerix <nerixdev at outlook.de>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/test/Shell/SymbolFile/NativePDB/c-calling-conventions.cpp

  Log Message:
  -----------
  [LLDB] Require target-x86/x86_64 for MSVC C mangling test (#162335)

Fixes the test failure from
https://github.com/llvm/llvm-project/pull/161678#issuecomment-3377949862.

  Commit: 93f2e0a4433f5f7ede3aeccda0a44c8482c3022d
      https://github.com/llvm/llvm-project/commit/93f2e0a4433f5f7ede3aeccda0a44c8482c3022d
  Author: Aiden Grossman <aidengrossman at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .ci/cache_lit_timing_files.py

  Log Message:
  -----------
  [CI] Make cache_lit_timing_files.py Script Gracefully Fail (#162316)

This is a performance optimization and does not impact test fidelity.
There have been some flakes where this script will fail to download
files, exit with code 1, causing the job to fail before it even starts
running tests. This is undesirable as the tests will only run 10-15%
slower without this, so catch the exceptions and emit a warning we can
track later in the rare case we cannot download the timing files.

This fixes #162294.

  Commit: 0cee4db636ae802e6d2ecf2e53c4538f3354736e
      https://github.com/llvm/llvm-project/commit/0cee4db636ae802e6d2ecf2e53c4538f3354736e
  Author: Marco Elver <elver at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/include/clang/Basic/Sanitizers.def
    M clang/lib/CodeGen/CodeGenFunction.cpp

  Log Message:
  -----------
  [Clang][CodeGen] Introduce the AllocToken SanitizerKind (#162098)

Introduce the "alloc-token" sanitizer kind, in preparation of wiring it
up. Currently this is a no-op, and any attempt to enable it will result
in failure:

clang: error: unsupported option '-fsanitize=alloc-token' for target
'x86_64-unknown-linux-gnu'

In this step we can already wire up the `sanitize_alloc_token` IR
attribute where the instrumentation is enabled. Subsequent changes will
complete wiring up the AllocToken pass.

---

This change is part of the following series:
  1. https://github.com/llvm/llvm-project/pull/160131
  2. https://github.com/llvm/llvm-project/pull/156838
  3. https://github.com/llvm/llvm-project/pull/162098
  4. https://github.com/llvm/llvm-project/pull/162099
  5. https://github.com/llvm/llvm-project/pull/156839
  6. https://github.com/llvm/llvm-project/pull/156840
  7. https://github.com/llvm/llvm-project/pull/156841
  8. https://github.com/llvm/llvm-project/pull/156842

  Commit: d0d18a80e52749a95e18acc39772fc3a21108e66
      https://github.com/llvm/llvm-project/commit/d0d18a80e52749a95e18acc39772fc3a21108e66
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td

  Log Message:
  -----------
  [RISCV] Remove -rc1 from Zacas/Zabha version comment. NFC (#162331)

  Commit: 631719d0d9ce7616f82aef22bab59ab82eb7cec2
      https://github.com/llvm/llvm-project/commit/631719d0d9ce7616f82aef22bab59ab82eb7cec2
  Author: Marco Elver <elver at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/lib/CodeGen/CGExpr.cpp
    M clang/lib/CodeGen/CGExprCXX.cpp
    M clang/lib/CodeGen/CodeGenFunction.h

  Log Message:
  -----------
  [Clang][CodeGen] Emit !alloc_token for new expressions (#162099)

For new expressions, the allocated type is syntactically known and we
can trivially emit the !alloc_token metadata. A subsequent change will
wire up the AllocToken pass and introduce appropriate tests.

---

This change is part of the following series:
  1. https://github.com/llvm/llvm-project/pull/160131
  2. https://github.com/llvm/llvm-project/pull/156838
  3. https://github.com/llvm/llvm-project/pull/162098
  4. https://github.com/llvm/llvm-project/pull/162099
  5. https://github.com/llvm/llvm-project/pull/156839
  6. https://github.com/llvm/llvm-project/pull/156840
  7. https://github.com/llvm/llvm-project/pull/156841
  8. https://github.com/llvm/llvm-project/pull/156842

  Commit: e166816af0fc53723866608e1ff79f0a75ebcfdb
      https://github.com/llvm/llvm-project/commit/e166816af0fc53723866608e1ff79f0a75ebcfdb
  Author: Ryosuke Niwa <rniwa at webkit.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
    M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm

  Log Message:
  -----------
  [WebKit Checkers] Treat a boxed value as a safe pointer origin (#161133)

  Commit: 872c4319dfc52886bbac03955ba1b7fe3ce83efc
      https://github.com/llvm/llvm-project/commit/872c4319dfc52886bbac03955ba1b7fe3ce83efc
  Author: Ryosuke Niwa <rniwa at webkit.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
    M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
    M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm

  Log Message:
  -----------
  [WebKit Checkers] Recognize NSApp as a safe global variable (#160990)

Treat accessing NSApp without retaining it as safe

  Commit: c5e343022cedd107559411378e6e008ef87b3caf
      https://github.com/llvm/llvm-project/commit/c5e343022cedd107559411378e6e008ef87b3caf
  Author: Joseph Huber <huberjn at outlook.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/docs/ClangLinkerWrapper.rst
    M clang/docs/index.rst

  Log Message:
  -----------
  [Clang][Docs] Fix leftoever references to moved documenation

  Commit: 11fb8358fab2796e6cdc5f85d24cc33696317b11
      https://github.com/llvm/llvm-project/commit/11fb8358fab2796e6cdc5f85d24cc33696317b11
  Author: Joseph Huber <huberjn at outlook.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M libc/src/__support/RPC/rpc_server.h

  Log Message:
  -----------
  [libc] Make LIBC_EXIT RPC code use quick exit

Summary:
This RPC call does the final exiting. The callbacks were handled on the
GPU side and this is only 'valid' in the pretend mode where we treat the
GPU like a CPU program. Doing this keeps us from crashing and burning
if people continue using the program while this is running as `exit`
would tear down the offloading library in memory and lead to segfaults.
This just drops everything where it is and lets the process manager
clean it up for us.

  Commit: 750a36186525f18f769833a359ebc72a4f26f937
      https://github.com/llvm/llvm-project/commit/750a36186525f18f769833a359ebc72a4f26f937
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll

  Log Message:
  -----------
  [RISCV] Add RV32 Zabha RUN lines to atomic-rmw.ll. NFC

We already had RV64 RUN lines.

  Commit: aed73d2afeecace1e38f9a85ec94d0aa05e86bda
      https://github.com/llvm/llvm-project/commit/aed73d2afeecace1e38f9a85ec94d0aa05e86bda
  Author: Maksim Levental <maksim.levental at gmail.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M mlir/python/mlir/ir.py

  Log Message:
  -----------
  [MLIR][Python] hide globals in ir.py (#162339)

We're shadowing the Python builtin function `globals` in `ir.py` and
therefore anywhere someone does `from mlir.ir import *`. So hide it.

  Commit: 981dadcd60481939bdc8917c6f15cb6232313bc1
      https://github.com/llvm/llvm-project/commit/981dadcd60481939bdc8917c6f15cb6232313bc1
  Author: Martin Storsjö <martin at martin.st>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M libcxx/src/system_error.cpp

  Log Message:
  -----------
  [libcxx] Map Windows ERROR_NETNAME_DELETED to no_such_file_or_directory (#162257)

This fixes spurious failures in
std/input.output/filesystems/fs.op.funcs/fs.op.proximate/proximate.pass.cpp
on Windows.

As part of that test, libcxx tries to open a fake network path such as
"//foo/a". Normally, this sets the error ERROR_BAD_NETPATH, which is
mapped to no_such_file_or_directory. However occasionally, it can end up
setting the error ERROR_NETNAME_DELETED instead.

Map ERROR_NETNAME_DELETED to no_such_file_or_directory just like
ERROR_BAD_NETPATH is mapped. This makes these cases be treated equally
within the create_file_status function in
src/filesystem/file_descriptor.h, causing the __weakly_canonical
function in operations.cpp to keep iterating, rather than erroring out.

  Commit: 7546bd38041612e8b768f4b315e491cd549d608c
      https://github.com/llvm/llvm-project/commit/7546bd38041612e8b768f4b315e491cd549d608c
  Author: Janet Yang <qxy11 at meta.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/include/lldb/API/SBDebugger.h
    M lldb/include/lldb/API/SBTarget.h
    M lldb/include/lldb/Target/Target.h
    M lldb/include/lldb/Target/TargetList.h
    M lldb/include/lldb/lldb-defines.h
    M lldb/source/API/SBDebugger.cpp
    M lldb/source/API/SBTarget.cpp
    M lldb/source/Target/Target.cpp
    M lldb/source/Target/TargetList.cpp
    M lldb/test/API/python_api/debugger/TestDebuggerAPI.py

  Log Message:
  -----------
  [lldb] Add support for unique target ids (#160736)

### Summary
Add support for unique target ids per Target instance. This is needed
for upcoming changes to allow debugger instances to be shared across
separate DAP instances for child process debugging. We want the IDE to
be able to attach to existing targets in an already runny lldb-dap
session, and having a unique ID per target would make that easier.

Each Target instance will have its own unique id, and uses a
function-local counter in `TargetList::CreateTargetInternal` to assign
incremental unique ids.

### Tests
Added several unit tests to test basic functionality, uniqueness of
targets, and target deletion doesn't affect the uniqueness.
```
bin/lldb-dotest -p TestDebuggerAPI
```

  Commit: 605e2d1fdd26bc78b824a8b97c1f2eafbcbe5a54
      https://github.com/llvm/llvm-project/commit/605e2d1fdd26bc78b824a8b97c1f2eafbcbe5a54
  Author: Jonas Devlieghere <jonas at devlieghere.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/unittests/Host/MainLoopTest.cpp

  Log Message:
  -----------
  [lldb] Make MainLoopTest::CallbackWithTimeout slightly more resilient (#162197)

Compute the start time *before* registering the callback, rather than
after, to avoid the possibility of a small race.

The following scenario illustrates the problem.

1. The callback is registered with a 2 second timeout at t=0ms.
2. We compute the start time after registering the callback. For the
sake of argument, let's say it took 5ms to return from registering the
callback and computing the current time. Start=5ms.
3. The callback fires after exactly 2 seconds, or t=2000ms.
4. We compute the difference between start and now. If it took less than
5ms to compute, then we end up with a difference that's less than 2000ms
and the test fails. Let's say it took 3ms this time, then
2003ms-5ms=1998ms < 2000ms.

The actual values in the example above are arbitrary. All that matters
is that it took longer to compute the start time than the end time. My
theory is that this explains why this test is flaky when running under
ASan in CI (which has unpredictable timing).

rdar://160956999

  Commit: c7d776b06897567e2d698e447d80279664b67d47
      https://github.com/llvm/llvm-project/commit/c7d776b06897567e2d698e447d80279664b67d47
  Author: Gergely Bálint <gergely.balint at arm.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    R bolt/docs/PacRetDesign.md
    M bolt/include/bolt/Core/BinaryFunction.h
    M bolt/include/bolt/Core/MCPlus.h
    M bolt/include/bolt/Core/MCPlusBuilder.h
    R bolt/include/bolt/Passes/InsertNegateRAStatePass.h
    R bolt/include/bolt/Passes/MarkRAStates.h
    M bolt/include/bolt/Utils/CommandLineOpts.h
    M bolt/lib/Core/BinaryBasicBlock.cpp
    M bolt/lib/Core/BinaryContext.cpp
    M bolt/lib/Core/BinaryFunction.cpp
    M bolt/lib/Core/Exceptions.cpp
    M bolt/lib/Core/MCPlusBuilder.cpp
    M bolt/lib/Passes/CMakeLists.txt
    R bolt/lib/Passes/InsertNegateRAStatePass.cpp
    R bolt/lib/Passes/MarkRAStates.cpp
    M bolt/lib/Rewrite/BinaryPassManager.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
    R bolt/test/AArch64/negate-ra-state-disallow.s
    R bolt/test/AArch64/negate-ra-state-incorrect.s
    R bolt/test/AArch64/negate-ra-state-reorder.s
    R bolt/test/AArch64/negate-ra-state.s
    R bolt/test/AArch64/pacret-split-funcs.s
    R bolt/test/runtime/AArch64/negate-ra-state.cpp
    R bolt/test/runtime/AArch64/pacret-function-split.cpp

  Log Message:
  -----------
  Revert "[BOLT][AArch64] Handle OpNegateRAState to enable optimizing binaries with pac-ret hardening" (#162353)

Reverts llvm/llvm-project#120064.

@gulfemsavrun reported that the patch broke toolchain builders.

  Commit: 0df5fc7d825d2b279ecd283ca002834c223853ff
      https://github.com/llvm/llvm-project/commit/0df5fc7d825d2b279ecd283ca002834c223853ff
  Author: Rolf Morel <rolf.morel at intel.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M mlir/docs/Dialects/Transform.md

  Log Message:
  -----------
  [MLIR][Transform] Docs: add SMT extension section and fix Tune header (#161560)

  Commit: 70c1c8f8007746040e256186d1e23b65d7590e00
      https://github.com/llvm/llvm-project/commit/70c1c8f8007746040e256186d1e23b65d7590e00
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
    A llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll

  Log Message:
  -----------
  [VPlan] Create SCEV expansion for epilogue check first.

VPExpandSCEVRecipes must be at the beginning of the entry block.
addMinimumEpilogueIterationCheck currently creates VPInstructions to
compute the remaining iterations before potentially creating
VPExpandSCEVRecipes.

Fix this by first creating any SCEV expansions if needed.

Fixes https://github.com/llvm/llvm-project/issues/162128.

  Commit: 0d758de6fbbe52d5001aa25b46bbe1c8b9206971
      https://github.com/llvm/llvm-project/commit/0d758de6fbbe52d5001aa25b46bbe1c8b9206971
  Author: Sang Ik Lee <sang.ik.lee at intel.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
    M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
    M mlir/test/Dialect/LLVMIR/invalid.mlir

  Log Message:
  -----------
  [MLIR][XeVM] blockload and blockstore ops should use scalar types (#161708)

instead of single element vectors.
XeVM type system does not support single element vectors.

  Commit: 47820b1260b4f3282792e89a42272758c777c51c
      https://github.com/llvm/llvm-project/commit/47820b1260b4f3282792e89a42272758c777c51c
  Author: Cyndy Ishida <cyndy_ishida at apple.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    A clang/test/Driver/darwin-maccatalyst-error.c
    M clang/test/Driver/darwin-maccatalyst.c

  Log Message:
  -----------
  [tests] Split up darwin-macatalyst test (#162358)

The way this test was constructed made it difficult to test downstream
divergence correctly; instead split the error case.

  Commit: 879f8616ef93b5f3732568aeabdade6af26094f7
      https://github.com/llvm/llvm-project/commit/879f8616ef93b5f3732568aeabdade6af26094f7
  Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/include/llvm/Analysis/IR2Vec.h
    A llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/InitializePasses.h
    A llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json
    M llvm/lib/CodeGen/CMakeLists.txt
    M llvm/lib/CodeGen/CodeGen.cpp
    A llvm/lib/CodeGen/MIR2Vec.cpp
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
    A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
    A llvm/test/CodeGen/MIR2Vec/vocab-basic.ll
    A llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll
    M llvm/tools/llc/llc.cpp
    M llvm/unittests/CodeGen/CMakeLists.txt
    A llvm/unittests/CodeGen/MIR2VecTest.cpp

  Log Message:
  -----------
  [IR2Vec] Initial infrastructure for MIR2Vec (#161463)

This PR introduces the initial infrastructure and vocabulary necessary for generating embeddings for MIR (discussed briefly in the earlier IR2Vec RFC - https://discourse.llvm.org/t/rfc-enhancing-mlgo-inlining-with-ir2vec-embeddings).  The MIR2Vec embeddings are useful in driving target specific optimizations that work on MIR like register allocation.

(Tracking issue - #141817)

  Commit: edb43192516a55165cc4c158eb4fd4b2d81a8fce
      https://github.com/llvm/llvm-project/commit/edb43192516a55165cc4c158eb4fd4b2d81a8fce
  Author: Brad Smith <brad at comstyle.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M compiler-rt/lib/builtins/cpu_model/aarch64.c
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc

  Log Message:
  -----------
  [FMV][AArch64] Add initial AT_HWCAP3 / AT_HWCAP4 support (#161595)

Add support for AT_HWCAP3 / AT_HWCAP4 which is supported by glibc, musl,
Android and FreeBSD 15/-current.

Stop using sys/ifunc.h as libgcc has done. This is more portable as
older glibc will not have the hwcap3/4 fields.

  Commit: c95f5bbe6f6b1d20aadcb717c56d97c81fc40ee0
      https://github.com/llvm/llvm-project/commit/c95f5bbe6f6b1d20aadcb717c56d97c81fc40ee0
  Author: Joshua Rodriguez <josh.rodriguez at arm.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    A llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
    M llvm/test/CodeGen/AArch64/arm64-vadd.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Prevented llvm.aarch64.neon.saddlp/uaddlp fallback (#160883)

Prevented fallback on G_SADDLP/G_UADDLP instructions that return
one-element i64 vectors, caused due to incorrect Register Bank
Selection.

  Commit: 5f7dc8ad11c096a556d49ee676bb627eb8b5cd11
      https://github.com/llvm/llvm-project/commit/5f7dc8ad11c096a556d49ee676bb627eb8b5cd11
  Author: Fei Peng <pengfei.02 at bytedance.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp

  Log Message:
  -----------
  [compiler-rt][TSan] Fix TSan compile error on Android (#162369)

  Commit: 125f0ac75796bc6807c98796bc1c5fff858acc7e
      https://github.com/llvm/llvm-project/commit/125f0ac75796bc6807c98796bc1c5fff858acc7e
  Author: David Green <david.green at arm.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/ARM/llrint-conv.ll
    M llvm/test/CodeGen/ARM/lrint-conv.ll
    M llvm/test/CodeGen/ARM/vector-lrint.ll

  Log Message:
  -----------
  [ARM][SDAG] Half promote llvm.lrint nodes. (#161088)

As shown in #137101, fp16 lrint are not handled correctly on Arm. This
adds soft-half promotion for them, reusing the function that promotes a
value with operands (and can handle strict fp once that is added).

  Commit: 57f69232da622569d3a06ecb717fbf713aa8d457
      https://github.com/llvm/llvm-project/commit/57f69232da622569d3a06ecb717fbf713aa8d457
  Author: Kelvin Li <kli at ca.ibm.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/test/Driver/env.c

  Log Message:
  -----------
  Disable Driver/env.c on AIX (NFC) (#161874)

AIX does not use LD_LIBRARY_PATH.

  Commit: 5c613f287df7fc94e159621f870f1bb1fe3baaee
      https://github.com/llvm/llvm-project/commit/5c613f287df7fc94e159621f870f1bb1fe3baaee
  Author: Erik Enikeev <47039011+Varnike at users.noreply.github.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/lib/Target/ARM/ARMRegisterInfo.td
    M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
    M llvm/test/CodeGen/ARM/bf16_fast_math.ll
    M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
    M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
    M llvm/test/CodeGen/ARM/fp16_fast_math.ll
    M llvm/test/CodeGen/ARM/ipra-reg-usage.ll
    M llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
    M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
    M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
    M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
    M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
    M llvm/test/CodeGen/Thumb2/swp-regpressure.mir

  Log Message:
  -----------
  [ARM] Add mayRaiseFPException to appropriate instructions and mark all instructions that read/write fpscr rounding bits as doing so (#160698)

Added new register FPSCR_RM to correctly model interactions with
rounding mode control bits of fpscr and to avoid performance regressions
in normal non-strictfp case

This PR is part of the work on adding strict FP support in ARM, which
was previously discussed in #137101.

  Commit: 30b9ef8088c35d86fbdffebe0ba8cdcea1afe6eb
      https://github.com/llvm/llvm-project/commit/30b9ef8088c35d86fbdffebe0ba8cdcea1afe6eb
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Factor out the core part of LMULWriteResMXVariant. NFC (#162347)

LMULWriteResMXVariant is a helper class that makes creating LMUL-aware
`SchedVar` easier. In preparation for later patches that require
  - LMUL- _and_ SEW-aware `SchedVar`
- Assign different processor resources for predicated and non-predicated
variants

I factor out the core logics of LMULWriteResMXVariant into another impl
class, such that it'll be easier to add _"LMULSEWWriteResMXSEWVariant"_
easier later. I also extend this class so that users can customize
processor resources for the non-predicated variant.

Despite these, this patch is still a NFC. I thought it'll be cleaner not
to mix the changes here into later patches.

  Commit: b54f01e91163abb7cfcca76da34efebbee4622b4
      https://github.com/llvm/llvm-project/commit/b54f01e91163abb7cfcca76da34efebbee4622b4
  Author: Ahmed Bougacha <ahmed at bougacha.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
    M clang/test/Driver/aarch64-cpu-defaults-appleos26.c

  Log Message:
  -----------
  [AArch64] Bump default CPUs for iOS 18/watchOS 26 to A10/S9. (#162325)

We previously bumped the defaults for 26.0 Apple OS targets to
conservative CPU targets in 69d141712a10.

We can further bump it for watchOS arm64 (which lets us be a little bit
more aggressive than arm64e/arm64_32), as well as for the iOS
predecessor, iOS 18.

  Commit: 7ab7554ef6e1eb45791d047eb332837e6d7d603f
      https://github.com/llvm/llvm-project/commit/7ab7554ef6e1eb45791d047eb332837e6d7d603f
  Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/tools/debugserver/source/RNBRemote.cpp

  Log Message:
  -----------
  [debugserver][NFC] Add helper function for escaping special characters (#162297)

This code was duplicated in multiple places and a subsequent patch will
need to do it again.

  Commit: 25933f62dc261c394361ff8b42f40196ee36f44e
      https://github.com/llvm/llvm-project/commit/25933f62dc261c394361ff8b42f40196ee36f44e
  Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/tools/debugserver/source/RNBRemote.cpp

  Log Message:
  -----------
  [debugserver][NFC] Make helper functions have internal linkage (#162307)

This also allowed deleting unreachable code.

  Commit: 2a2324a6eae7447be07ed95a24d5b335c9513450
      https://github.com/llvm/llvm-project/commit/2a2324a6eae7447be07ed95a24d5b335c9513450
  Author: Helena Kotas <hekotas at microsoft.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/include/clang/AST/HLSLResource.h
    M clang/lib/Sema/SemaHLSL.cpp
    M clang/test/AST/HLSL/resource_binding_attr.hlsl
    M clang/test/AST/HLSL/vk_binding_attr.hlsl

  Log Message:
  -----------
  [HLSL] Do not remove `HLSLVkBindingAttr` if the target is not SPIR-V (#161752)

The attribute needs to be preserved for rewriter scenarios. Two places were updated to use the `ResourceBindingAttrs` helper struct to make sure the `HLSLVkBindingAttr` is ignored when the target is DirectX.

  Commit: 84cb38684b03f83f5e7412c1ac447d8037e32fc3
      https://github.com/llvm/llvm-project/commit/84cb38684b03f83f5e7412c1ac447d8037e32fc3
  Author: CatherineMoore <catmoore at amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/docs/OpenMPSupport.rst

  Log Message:
  -----------
  [OpenMP] Update OpenMP 6.0 implementation status. (#162379)

Please review

  Commit: 57b5ba00cb421b9be17bac10036763f42fbe9298
      https://github.com/llvm/llvm-project/commit/57b5ba00cb421b9be17bac10036763f42fbe9298
  Author: Brad Smith <brad at comstyle.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc

  Log Message:
  -----------
  [FMV][AArch64] Fix build after edb43192516a55165cc4c158eb4fd4b2d81a8fce (#162383)

Revert removal of local variables.

  Commit: 198f29469a159e8418734e18edb60e33cb476462
      https://github.com/llvm/llvm-project/commit/198f29469a159e8418734e18edb60e33cb476462
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s

  Log Message:
  -----------
  [RISCV] Add missing vector floating point scheduling model tests for SiFive7 (#162386)

This is helpful on validating the non-throttled vector FP64 performance,
compared to the throttled model of sifive-x390.

  Commit: 7f82996cd2b5e062e835b7aa3b99ecfdf54eeeb5
      https://github.com/llvm/llvm-project/commit/7f82996cd2b5e062e835b7aa3b99ecfdf54eeeb5
  Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/unittests/CodeGen/MIR2VecTest.cpp

  Log Message:
  -----------
  [MIR2Vec] Fixing non x86 unittest failures (#162381)

Fixing failures due to #161463

  Commit: 699f085791872f9006e25d1369327e1ddc44002e
      https://github.com/llvm/llvm-project/commit/699f085791872f9006e25d1369327e1ddc44002e
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/include/clang/Basic/SanitizerSpecialCaseList.h
    M clang/lib/Basic/SanitizerSpecialCaseList.cpp

  Log Message:
  -----------
  [NFC][SanitizerSection] Store Section& instead of Entries and FileIdx (#162382)

  Commit: 33e82e663d3ae15c4f73afa79bf8d27d66156311
      https://github.com/llvm/llvm-project/commit/33e82e663d3ae15c4f73afa79bf8d27d66156311
  Author: Anthony Latsis <alatsis at apple.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/test/tools/llvm-ar/extract.test
    M llvm/test/tools/llvm-ar/print.test

  Log Message:
  -----------
  [test] llvm-ar: Adjust 2 tests to pass again after inadvertent unXFAIL for some target triples (#159796)

The problem with the current `target={{.*}}-darwin{{.*}}` XFAIL
condition (changed in https://github.com/llvm/llvm-project/pull/130144)
is that the Swift build script uses Apple platform names like 'macosx',
not 'darwin', for the LLVM target triple, e.g. `arm64-apple-macosx13.0`.

These tests appear to have been originally XFAILed because the default
format on macOS (darwin) adds newlines as padding to align members. See:
https://github.com/llvm/llvm-project/blob/ee8394d9469a2946ffe2e7d192c593ecf3f93098/llvm/lib/Object/ArchiveWriter.cpp#L897-L904

Use `--format=gnu` to cope with the differences in the output and
reenable the tests.

rdar://157213658

  Commit: ca1a1f47da0a073de838748b9b7067d7f10e8c92
      https://github.com/llvm/llvm-project/commit/ca1a1f47da0a073de838748b9b7067d7f10e8c92
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Support/SpecialCaseList.cpp

  Log Message:
  -----------
  [NFC][SpecialCaseList] Generalize "#!special-case-list-v" parsing (#162350)

  Commit: 768f438c6a31aecfecb848f560a8f698d80d908f
      https://github.com/llvm/llvm-project/commit/768f438c6a31aecfecb848f560a8f698d80d908f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll

  Log Message:
  -----------
  [RISCV][GISel] Add Zalasr RUN lines to atomic-load-store-fp.ll. NFC (#162204)

After #161774 and #162042, this works correctly.

  Commit: 1a9efac9a255e28ab673fe78b22a23c380f7bebc
      https://github.com/llvm/llvm-project/commit/1a9efac9a255e28ab673fe78b22a23c380f7bebc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s

  Log Message:
  -----------
  [RISCV] Rename atomic instructions to remove underscore between AQ and RL. NFC (#162321)

Instruction names should match the mnemomic with '.' replaced by '_'.
The instruction mnemonics use ".aqrl" not ".aq.rl".

  Commit: 681bd80ca5986b85695fdd5e6b4fc205f514ba0c
      https://github.com/llvm/llvm-project/commit/681bd80ca5986b85695fdd5e6b4fc205f514ba0c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Bump Zalasr version to 0.9. (#162329)

Update doc repository link.

  Commit: fee4c16cf7483741f0a9fa033e6c76ec8f68bd4f
      https://github.com/llvm/llvm-project/commit/fee4c16cf7483741f0a9fa033e6c76ec8f68bd4f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td

  Log Message:
  -----------
  [RISCV] Add IsSignExtendingOpW to Zabha and Zalasr instructions. (#162341)

  Commit: 235308892ac73d457f4c7763e2f184f3c19fdd43
      https://github.com/llvm/llvm-project/commit/235308892ac73d457f4c7763e2f184f3c19fdd43
  Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/unittests/Analysis/IR2VecTest.cpp

  Log Message:
  -----------
  [IR2Vec] Adding tests to check multiple invocations of `getFunctionVector()` and `getInstVecMap()` return same results (#162365)

Tests for #162165. Missed it earlier.

  Commit: 9715ccae1f98162f03ac0884a3dce5045b6b9a6e
      https://github.com/llvm/llvm-project/commit/9715ccae1f98162f03ac0884a3dce5045b6b9a6e
  Author: Brad Smith <brad at comstyle.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc

  Log Message:
  -----------
  [FMV][AArch64] Fix build after edb43192516a55165cc4c158eb4fd4b2d81a8fce, try 2 (#162393)

Correct the variable names

  Commit: 94f290fffd80bd7c7d65db1df78cdacab633aab4
      https://github.com/llvm/llvm-project/commit/94f290fffd80bd7c7d65db1df78cdacab633aab4
  Author: yonghong-song <yhs at fb.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
    A llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll
    A llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll

  Log Message:
  -----------
  [BPF] Handle certain mem intrinsic functions with addr-space arguments (#160025)

In linux kernel commit [1], we have a bpf selftest failure caused by
llvm. In this particular case, the BPFCheckAndAdjustIR pass has a
function insertASpaceCasts() which inserts proper addrspacecast insn
at proper IR places. It does not handle __builtin_memset() and hance
caused selftest failure.

Add support in insertASpaceCasts() to handle
  __builtin_(memset,memcpy,memmove,memset_inline,memcpy_inline}()
properly and this can fix the issue in [1] as well.

[1]
https://lore.kernel.org/all/20250920045805.3288551-1-yonghong.song@linux.dev/

  Commit: 289e85b18101e058b3f4b81ce3c2b7c47489e7ca
      https://github.com/llvm/llvm-project/commit/289e85b18101e058b3f4b81ce3c2b7c47489e7ca
  Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .github/new-prs-labeler.yml

  Log Message:
  -----------
  Add MIR2Vec and missing IR2Vec files to MLGO label (#162395)

  Commit: 566040e1352740ee35927b68fafe5d778a1f2111
      https://github.com/llvm/llvm-project/commit/566040e1352740ee35927b68fafe5d778a1f2111
  Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/lib/CodeGen/MIR2Vec.cpp
    M llvm/unittests/CodeGen/MIR2VecTest.cpp

  Log Message:
  -----------
  [MIR2Vec] Refactor MIR vocabulary to use opcode-based indexing (#161713)

Refactor MIRVocabulary to improve opcode lookup and add Section enum for better organization. This is useful for embedder lookups (next patches)

(Tracking issue - #141817)

  Commit: abc8aac6d242df9f26c8dbaf8b2a65aaa5abe791
      https://github.com/llvm/llvm-project/commit/abc8aac6d242df9f26c8dbaf8b2a65aaa5abe791
  Author: Derek Schuff <dschuff at chromium.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll

  Log Message:
  -----------
  [WebAssembly] Check intrinsic argument count before Any/All combine (#162163)

This code is activated on all INTRINSIC_WO_CHAIN but only handles
a selection. However it was trying to read the arguments before
checking which intrinsic it was handling. This fails for intrinsics
that have no arguments.

  Commit: b7df53380960efca085e3d849d3a163e8e919880
      https://github.com/llvm/llvm-project/commit/b7df53380960efca085e3d849d3a163e8e919880
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M clang/lib/Basic/SanitizerSpecialCaseList.cpp
    M llvm/include/llvm/Support/SpecialCaseList.h
    M llvm/lib/Support/SpecialCaseList.cpp

  Log Message:
  -----------
  [NFC][SpecialCaseList] Rename SpecialCaseList::inSectionBlame and move into Section (#162390)

Co-authored-by: Craig Topper <craig.topper at sifive.com>

  Commit: 01a8f9b81870ac9bfe26d80fa3313d56cb8cbe13
      https://github.com/llvm/llvm-project/commit/01a8f9b81870ac9bfe26d80fa3313d56cb8cbe13
  Author: Jason Molenda <jmolenda at apple.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py
    M lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml
    M lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json

  Log Message:
  -----------
  [lldb] Cortex-M exception unwind API test cleanup

This test, with a corefile created via yaml2macho-core plus an
ObjectFileJSON binary with symbol addresses and ranges, was failing
on some machines/CI because the wrong ABI was being picked.

The bytes of the functions were not included in the yaml or .json
binary.  The unwind falls back to using the ABI plugin default
unwind plans.  We have two armv7 ABIs - the Darwin ABI that always
uses r7 as the frame pointer, and the AAPCS ABI which uses r11 code.
In reality, armv7 code uses r11 in arm mode, r7 in thumb code.  But
the ABI ArchDefaultUnwindPlan doesn't have any access to the Target's
ArchSpec or Process register state, to determine the correct processor
state (arm or thumb).  And in fact, on Cortex-M targets, the
instructions are always thumb, so the arch default unwind plan
(hardcoded r11) is always wrong.

The corefile doesn't specify a vendor/os, only a cpu.
The object file json specifies the armv7m-apple-* triple, which will
select the correct ABI plugin, and the test runs.

In some cases, it looks like the Process ABI was fetched after
opening the corefile, but before the binary.json was loaded and
corrected the Target's ArchSpec.  And we never re-evaluate the ABI
once it is set, in a Process.  When we picked the AAPCS armv7 ABI,
we would try to use r11 as frame pointer, and the unwind would stop
after one stack frame.

I'm stepping around this problem by (1) adding the register bytes of
the prologues of every test function in the backtrace, and (2)
shortening the function ranges (in binary.json) to specify that the
functions are all just long enough for the prologue where execution
is stopped.  The instruction emulation plugin will fail if it can't
get all of the bytes from the function instructions, so I hacked
the function sizes in the .json to cover the prologue plus one and
changed the addresses in the backtrace to fit within those ranges.

  Commit: e5d15c12001dc8e066ecad65297fe87e953bcc39
      https://github.com/llvm/llvm-project/commit/e5d15c12001dc8e066ecad65297fe87e953bcc39
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-08 (Wed, 08 Oct 2025)

  Changed paths:
    M llvm/lib/Support/SpecialCaseList.cpp

  Log Message:
  -----------
  [NFC][SpecialCaseList] Make default version 2 instead of max() (#162398)

This way we can roll out new breaking features as opt-int.
E.g. "#!special-case-list-v3" will enabled something new.

Nothing to enabled yet, but with pinpointed default it's an option.

Follow up #162350.

  Commit: 5deb787c02ed4bd26b6554199c539bf5478671a7
      https://github.com/llvm/llvm-project/commit/5deb787c02ed4bd26b6554199c539bf5478671a7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVGISel.td

  Log Message:
  -----------
  [RISCV][GISel] Add manual instruction selection for i8/i16/i32->i32/i64 G_SEXT/G_ZEXT. (#161971)

Because GISel doesn't distinquish integer and FP types, we need to allow
s16/s32 as legal inputs/outputs of G_SEXT and G_ZEXT.

This requires a extra isel patterns to support the cross product of
these types that we don't need for SelectionDAG. We also needed to add
i16/i32 to the GPR register class which prevents some type inferencing
in tablegen and increases the size of the RISCVGenDAGISel.inc by 2K.

This patch proposes to do manual selection so we can remove these
patterns and eventually remove the types from the register class.

  Commit: 5d5fe11c38caabe97337afa5a426c7c8de10a29e
      https://github.com/llvm/llvm-project/commit/5d5fe11c38caabe97337afa5a426c7c8de10a29e
  Author: Fei Peng <pengfei.02 at bytedance.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp

  Log Message:
  -----------
  [compiler-rt][TSan] Fix compilation error on Android x86 (#162385)

  Commit: bdef80f7a9a1f563f7d2f528e12bb3321d836857
      https://github.com/llvm/llvm-project/commit/bdef80f7a9a1f563f7d2f528e12bb3321d836857
  Author: jimingham <jingham at apple.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M lldb/include/lldb/Utility/Stream.h

  Log Message:
  -----------
  Fix an API that was changed w/o changing the header doc (#162401)

This was causing bot failures if you build with -Werror -Wdocumentation.
Fix the docs to reflect the new headers.

  Commit: aed53d19f9f4a6db4210e50712b96d4881d83774
      https://github.com/llvm/llvm-project/commit/aed53d19f9f4a6db4210e50712b96d4881d83774
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-08 (Wed, 08 Oct 2025)

  Changed paths:
    M clang/lib/Basic/SanitizerSpecialCaseList.cpp
    M llvm/include/llvm/Support/SpecialCaseList.h
    M llvm/lib/Support/SpecialCaseList.cpp

  Log Message:
  -----------
  [NFC][SpecialCaseList] Extract findMatcher and ::match with callback (#162397)

There are some users who rely on more than line
number. It would be easy to move some logic from
users side here with extracted methods.

  Commit: 70b7a3502ee975ad08e2bc3ade32a04db19e31de
      https://github.com/llvm/llvm-project/commit/70b7a3502ee975ad08e2bc3ade32a04db19e31de
  Author: Lang Hames <lhames at gmail.com>
  Date:   2025-10-08 (Wed, 08 Oct 2025)

  Changed paths:
    A orc-rt/unittests/DirectCaller.h
    M orc-rt/unittests/SPSWrapperFunctionTest.cpp

  Log Message:
  -----------
  [orc-rt] Hoist DirectCaller test utility into header to enable re-use. (#162405)

The DirectCaller utility allows "direct" calls (with arguments
serialized into, and then immediately back out of a
WrapperFunctionBuffer) to wrapper functions. It was introduced for the
SPSWrapperFunction tests, but will be useful for testing WrapperFunction
interfaces for various orc-rt APIs too, so this commit hoists it
somewhere where it can be reused.

  Commit: 7212d27a44d35a4bd6a9738dc9d883efdb33501e
      https://github.com/llvm/llvm-project/commit/7212d27a44d35a4bd6a9738dc9d883efdb33501e
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-08 (Wed, 08 Oct 2025)

  Changed paths:
    M llvm/include/llvm/Support/SpecialCaseList.h
    M llvm/lib/Support/SpecialCaseList.cpp

  Log Message:
  -----------
  [NFC][SpecialCaseList] Add Name into Regex version (#162408)

To pass something into Cb in `match()`.

No need to bother with test coverage, as it's
legacy transitional code, maybe we can remove it
soon.

  Commit: 3af95f016e1d690670c13b1d33d14999d863f3fe
      https://github.com/llvm/llvm-project/commit/3af95f016e1d690670c13b1d33d14999d863f3fe
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-10-08 (Wed, 08 Oct 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
    M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll

  Log Message:
  -----------
  AMDGPU: Figure out required AGPR count for inline asm (#150910)

For now just try to compute the minimum number of AGPRs required
to allocate the asm. Leave the attributor changes to turn this
into an integer value for later.

  Commit: 82e0a59df12a24208b8e0247ff08d14407be2a2e
      https://github.com/llvm/llvm-project/commit/82e0a59df12a24208b8e0247ff08d14407be2a2e
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .ci/all_requirements.txt
    M .ci/cache_lit_timing_files.py
    M .github/new-prs-labeler.yml
    R bolt/docs/PacRetDesign.md
    M bolt/include/bolt/Core/BinaryFunction.h
    M bolt/include/bolt/Core/MCPlus.h
    M bolt/include/bolt/Core/MCPlusBuilder.h
    R bolt/include/bolt/Passes/InsertNegateRAStatePass.h
    R bolt/include/bolt/Passes/MarkRAStates.h
    M bolt/include/bolt/Utils/CommandLineOpts.h
    M bolt/lib/Core/BinaryBasicBlock.cpp
    M bolt/lib/Core/BinaryContext.cpp
    M bolt/lib/Core/BinaryFunction.cpp
    M bolt/lib/Core/Exceptions.cpp
    M bolt/lib/Core/MCPlusBuilder.cpp
    M bolt/lib/Passes/CMakeLists.txt
    R bolt/lib/Passes/InsertNegateRAStatePass.cpp
    R bolt/lib/Passes/MarkRAStates.cpp
    M bolt/lib/Rewrite/BinaryPassManager.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
    R bolt/test/AArch64/negate-ra-state-disallow.s
    R bolt/test/AArch64/negate-ra-state-incorrect.s
    R bolt/test/AArch64/negate-ra-state-reorder.s
    R bolt/test/AArch64/negate-ra-state.s
    R bolt/test/AArch64/pacret-split-funcs.s
    R bolt/test/runtime/AArch64/negate-ra-state.cpp
    R bolt/test/runtime/AArch64/pacret-function-split.cpp
    M clang/docs/ClangLinkerWrapper.rst
    M clang/docs/OpenMPSupport.rst
    M clang/docs/ReleaseNotes.rst
    M clang/docs/WarningSuppressionMappings.rst
    M clang/docs/index.rst
    M clang/include/clang/AST/HLSLResource.h
    M clang/include/clang/Analysis/Analyses/LifetimeSafety.h
    M clang/include/clang/Basic/Diagnostic.h
    M clang/include/clang/Basic/SanitizerSpecialCaseList.h
    M clang/include/clang/Basic/Sanitizers.def
    M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
    M clang/lib/AST/DeclPrinter.cpp
    M clang/lib/Analysis/LifetimeSafety.cpp
    A clang/lib/Analysis/LifetimeSafety.md
    M clang/lib/Basic/Diagnostic.cpp
    M clang/lib/Basic/ProfileList.cpp
    M clang/lib/Basic/SanitizerSpecialCaseList.cpp
    M clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp
    M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
    M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
    M clang/lib/CIR/CodeGen/CIRGenFunction.h
    M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M clang/lib/CodeGen/CGExpr.cpp
    M clang/lib/CodeGen/CGExprCXX.cpp
    M clang/lib/CodeGen/CodeGenFunction.cpp
    M clang/lib/CodeGen/CodeGenFunction.h
    M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
    M clang/lib/Sema/SemaHLSL.cpp
    M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
    M clang/test/AST/HLSL/resource_binding_attr.hlsl
    M clang/test/AST/HLSL/vk_binding_attr.hlsl
    M clang/test/AST/ast-print-record-decl.c
    M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
    M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
    M clang/test/Analysis/LifetimeSafety/benchmark.py
    M clang/test/CIR/CodeGen/new.cpp
    A clang/test/CIR/IR/dynamic-cast.cir
    A clang/test/CIR/IR/invalid-dyn-cast.cir
    M clang/test/Driver/aarch64-cpu-defaults-appleos26.c
    A clang/test/Driver/darwin-maccatalyst-error.c
    M clang/test/Driver/darwin-maccatalyst.c
    M clang/test/Driver/env.c
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M clang/test/Sema/warn-lifetime-safety.cpp
    M clang/unittests/AST/DeclPrinterTest.cpp
    M clang/unittests/Analysis/LifetimeSafetyTest.cpp
    M clang/unittests/Basic/DiagnosticTest.cpp
    M compiler-rt/lib/builtins/cpu_model/aarch64.c
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
    M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
    M compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp
    M flang/test/Lower/OpenMP/atomic-control-options.f90
    M libc/src/__support/RPC/rpc_server.h
    M libcxx/src/system_error.cpp
    M lldb/include/lldb/API/SBDebugger.h
    M lldb/include/lldb/API/SBTarget.h
    M lldb/include/lldb/Target/Target.h
    M lldb/include/lldb/Target/TargetList.h
    M lldb/include/lldb/Utility/Stream.h
    M lldb/include/lldb/lldb-defines.h
    M lldb/source/API/SBDebugger.cpp
    M lldb/source/API/SBTarget.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
    M lldb/source/Target/Target.cpp
    M lldb/source/Target/TargetList.cpp
    M lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py
    M lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml
    M lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json
    M lldb/test/API/python_api/debugger/TestDebuggerAPI.py
    M lldb/test/Shell/SymbolFile/NativePDB/break-by-function.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/break-by-line.cpp
    A lldb/test/Shell/SymbolFile/NativePDB/c-calling-conventions.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/stack_unwinding01.cpp
    M lldb/test/Shell/SymbolFile/PDB/function-nested-block.test
    M lldb/test/Shell/SymbolFile/PDB/variables.test
    M lldb/tools/debugserver/source/RNBRemote.cpp
    M lldb/unittests/Host/MainLoopTest.cpp
    M llvm/docs/RISCVUsage.rst
    M llvm/include/llvm/ADT/EquivalenceClasses.h
    M llvm/include/llvm/Analysis/HeatUtils.h
    M llvm/include/llvm/Analysis/IR2Vec.h
    A llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Support/SpecialCaseList.h
    M llvm/lib/Analysis/HeatUtils.cpp
    A llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json
    M llvm/lib/CodeGen/CMakeLists.txt
    M llvm/lib/CodeGen/CodeGen.cpp
    A llvm/lib/CodeGen/MIR2Vec.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/Support/SpecialCaseList.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/lib/Target/ARM/ARMRegisterInfo.td
    M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
    M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
    A llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
    M llvm/test/CodeGen/AArch64/arm64-vadd.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll
    M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
    M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
    M llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/minmax.ll
    M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
    M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
    M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
    M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
    M llvm/test/CodeGen/ARM/bf16_fast_math.ll
    M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
    M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
    M llvm/test/CodeGen/ARM/fp16_fast_math.ll
    M llvm/test/CodeGen/ARM/ipra-reg-usage.ll
    M llvm/test/CodeGen/ARM/llrint-conv.ll
    M llvm/test/CodeGen/ARM/lrint-conv.ll
    M llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
    M llvm/test/CodeGen/ARM/vector-lrint.ll
    M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
    A llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll
    A llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
    A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
    A llvm/test/CodeGen/MIR2Vec/vocab-basic.ll
    A llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
    M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
    M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
    M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
    M llvm/test/CodeGen/Thumb2/swp-regpressure.mir
    M llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll
    M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
    A llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll
    M llvm/test/tools/llvm-ar/extract.test
    M llvm/test/tools/llvm-ar/print.test
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
    M llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll
    M llvm/tools/llc/llc.cpp
    M llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp
    M llvm/unittests/Analysis/IR2VecTest.cpp
    M llvm/unittests/CodeGen/CMakeLists.txt
    A llvm/unittests/CodeGen/MIR2VecTest.cpp
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
    M llvm/utils/gn/secondary/clang/test/BUILD.gn
    M llvm/utils/gn/secondary/llvm/test/BUILD.gn
    A llvm/utils/gn/secondary/llvm/tools/llvm-offload-binary/BUILD.gn
    M llvm/utils/profcheck-xfail.txt
    M mlir/cmake/modules/AddMLIRPython.cmake
    M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
    M mlir/docs/Dialects/Linalg/OpDSL.md
    M mlir/docs/Dialects/Transform.md
    M mlir/examples/standalone/pyproject.toml
    M mlir/examples/standalone/python/CMakeLists.txt
    A mlir/examples/standalone/python/StandaloneExtensionPybind11.cpp
    A mlir/examples/standalone/python/mlir_standalone/dialects/standalone_pybind11.py
    M mlir/examples/standalone/test/python/smoketest.py
    A mlir/include/mlir/Bindings/Python/PybindAdaptors.h
    M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
    M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
    M mlir/python/CMakeLists.txt
    M mlir/python/mlir/dialects/python_test.py
    M mlir/python/mlir/ir.py
    M mlir/python/requirements.txt
    M mlir/test/Dialect/LLVMIR/invalid.mlir
    M mlir/test/python/dialects/python_test.py
    M mlir/test/python/lib/CMakeLists.txt
    A mlir/test/python/lib/PythonTestModulePybind11.cpp
    M mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in
    A orc-rt/unittests/DirectCaller.h
    M orc-rt/unittests/SPSWrapperFunctionTest.cpp
    M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
    M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
    M utils/bazel/llvm-project-overlay/llvm/driver.bzl
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6

[skip ci]

  Commit: 2468505671e8598f0fba888c39be975b02369c6b
      https://github.com/llvm/llvm-project/commit/2468505671e8598f0fba888c39be975b02369c6b
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .ci/all_requirements.txt
    M .ci/cache_lit_timing_files.py
    M .github/new-prs-labeler.yml
    R bolt/docs/PacRetDesign.md
    M bolt/include/bolt/Core/BinaryFunction.h
    M bolt/include/bolt/Core/MCPlus.h
    M bolt/include/bolt/Core/MCPlusBuilder.h
    R bolt/include/bolt/Passes/InsertNegateRAStatePass.h
    R bolt/include/bolt/Passes/MarkRAStates.h
    M bolt/include/bolt/Utils/CommandLineOpts.h
    M bolt/lib/Core/BinaryBasicBlock.cpp
    M bolt/lib/Core/BinaryContext.cpp
    M bolt/lib/Core/BinaryFunction.cpp
    M bolt/lib/Core/Exceptions.cpp
    M bolt/lib/Core/MCPlusBuilder.cpp
    M bolt/lib/Passes/CMakeLists.txt
    R bolt/lib/Passes/InsertNegateRAStatePass.cpp
    R bolt/lib/Passes/MarkRAStates.cpp
    M bolt/lib/Rewrite/BinaryPassManager.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
    R bolt/test/AArch64/negate-ra-state-disallow.s
    R bolt/test/AArch64/negate-ra-state-incorrect.s
    R bolt/test/AArch64/negate-ra-state-reorder.s
    R bolt/test/AArch64/negate-ra-state.s
    R bolt/test/AArch64/pacret-split-funcs.s
    R bolt/test/runtime/AArch64/negate-ra-state.cpp
    R bolt/test/runtime/AArch64/pacret-function-split.cpp
    M clang/docs/ClangLinkerWrapper.rst
    M clang/docs/OpenMPSupport.rst
    M clang/docs/ReleaseNotes.rst
    M clang/docs/WarningSuppressionMappings.rst
    M clang/docs/index.rst
    M clang/include/clang/AST/HLSLResource.h
    M clang/include/clang/Analysis/Analyses/LifetimeSafety.h
    M clang/include/clang/Basic/Diagnostic.h
    M clang/include/clang/Basic/SanitizerSpecialCaseList.h
    M clang/include/clang/Basic/Sanitizers.def
    M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
    M clang/lib/AST/DeclPrinter.cpp
    M clang/lib/Analysis/LifetimeSafety.cpp
    A clang/lib/Analysis/LifetimeSafety.md
    M clang/lib/Basic/Diagnostic.cpp
    M clang/lib/Basic/ProfileList.cpp
    M clang/lib/Basic/SanitizerSpecialCaseList.cpp
    M clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp
    M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
    M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
    M clang/lib/CIR/CodeGen/CIRGenFunction.h
    M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M clang/lib/CodeGen/CGExpr.cpp
    M clang/lib/CodeGen/CGExprCXX.cpp
    M clang/lib/CodeGen/CodeGenFunction.cpp
    M clang/lib/CodeGen/CodeGenFunction.h
    M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
    M clang/lib/Sema/SemaHLSL.cpp
    M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
    M clang/test/AST/HLSL/resource_binding_attr.hlsl
    M clang/test/AST/HLSL/vk_binding_attr.hlsl
    M clang/test/AST/ast-print-record-decl.c
    M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
    M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
    M clang/test/Analysis/LifetimeSafety/benchmark.py
    M clang/test/CIR/CodeGen/new.cpp
    A clang/test/CIR/IR/dynamic-cast.cir
    A clang/test/CIR/IR/invalid-dyn-cast.cir
    M clang/test/Driver/aarch64-cpu-defaults-appleos26.c
    A clang/test/Driver/darwin-maccatalyst-error.c
    M clang/test/Driver/darwin-maccatalyst.c
    M clang/test/Driver/env.c
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Driver/riscv-arch.c
    M clang/test/Preprocessor/riscv-target-features.c
    M clang/test/Sema/warn-lifetime-safety.cpp
    M clang/unittests/AST/DeclPrinterTest.cpp
    M clang/unittests/Analysis/LifetimeSafetyTest.cpp
    M clang/unittests/Basic/DiagnosticTest.cpp
    M compiler-rt/lib/builtins/cpu_model/aarch64.c
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
    M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
    M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
    M compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp
    M flang/test/Lower/OpenMP/atomic-control-options.f90
    M libc/src/__support/RPC/rpc_server.h
    M libcxx/src/system_error.cpp
    M lldb/include/lldb/API/SBDebugger.h
    M lldb/include/lldb/API/SBTarget.h
    M lldb/include/lldb/Target/Target.h
    M lldb/include/lldb/Target/TargetList.h
    M lldb/include/lldb/Utility/Stream.h
    M lldb/include/lldb/lldb-defines.h
    M lldb/source/API/SBDebugger.cpp
    M lldb/source/API/SBTarget.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
    M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h
    M lldb/source/Target/Target.cpp
    M lldb/source/Target/TargetList.cpp
    M lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py
    M lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml
    M lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json
    M lldb/test/API/python_api/debugger/TestDebuggerAPI.py
    M lldb/test/Shell/SymbolFile/NativePDB/break-by-function.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/break-by-line.cpp
    A lldb/test/Shell/SymbolFile/NativePDB/c-calling-conventions.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp
    M lldb/test/Shell/SymbolFile/NativePDB/stack_unwinding01.cpp
    M lldb/test/Shell/SymbolFile/PDB/function-nested-block.test
    M lldb/test/Shell/SymbolFile/PDB/variables.test
    M lldb/tools/debugserver/source/RNBRemote.cpp
    M lldb/unittests/Host/MainLoopTest.cpp
    M llvm/docs/RISCVUsage.rst
    M llvm/include/llvm/ADT/EquivalenceClasses.h
    M llvm/include/llvm/Analysis/HeatUtils.h
    M llvm/include/llvm/Analysis/IR2Vec.h
    A llvm/include/llvm/CodeGen/MIR2Vec.h
    M llvm/include/llvm/CodeGen/Passes.h
    M llvm/include/llvm/InitializePasses.h
    M llvm/include/llvm/Support/SpecialCaseList.h
    M llvm/lib/Analysis/HeatUtils.cpp
    A llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json
    M llvm/lib/CodeGen/CMakeLists.txt
    M llvm/lib/CodeGen/CodeGen.cpp
    A llvm/lib/CodeGen/MIR2Vec.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/lib/Support/SpecialCaseList.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/FLATInstructions.td
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/lib/Target/ARM/ARMRegisterInfo.td
    M llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
    M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
    A llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
    M llvm/test/CodeGen/AArch64/arm64-vadd.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
    M llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll
    M llvm/test/CodeGen/AMDGPU/atomic_load_local.ll
    M llvm/test/CodeGen/AMDGPU/atomic_store_local.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
    M llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
    M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
    M llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
    M llvm/test/CodeGen/AMDGPU/min.ll
    M llvm/test/CodeGen/AMDGPU/minmax.ll
    M llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll
    M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
    M llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll
    M llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll
    M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
    M llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
    M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
    M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
    M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
    M llvm/test/CodeGen/ARM/bf16_fast_math.ll
    M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
    M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
    M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
    M llvm/test/CodeGen/ARM/fp16_fast_math.ll
    M llvm/test/CodeGen/ARM/ipra-reg-usage.ll
    M llvm/test/CodeGen/ARM/llrint-conv.ll
    M llvm/test/CodeGen/ARM/lrint-conv.ll
    M llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
    M llvm/test/CodeGen/ARM/vector-lrint.ll
    M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
    A llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll
    A llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json
    A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
    A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
    A llvm/test/CodeGen/MIR2Vec/vocab-basic.ll
    A llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
    M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
    M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
    M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
    M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
    M llvm/test/CodeGen/Thumb2/swp-regpressure.mir
    M llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll
    M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
    A llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll
    M llvm/test/tools/llvm-ar/extract.test
    M llvm/test/tools/llvm-ar/print.test
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s
    M llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
    M llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll
    M llvm/tools/llc/llc.cpp
    M llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp
    M llvm/unittests/Analysis/IR2VecTest.cpp
    M llvm/unittests/CodeGen/CMakeLists.txt
    A llvm/unittests/CodeGen/MIR2VecTest.cpp
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
    M llvm/utils/gn/secondary/clang/test/BUILD.gn
    M llvm/utils/gn/secondary/llvm/test/BUILD.gn
    A llvm/utils/gn/secondary/llvm/tools/llvm-offload-binary/BUILD.gn
    M llvm/utils/profcheck-xfail.txt
    M mlir/cmake/modules/AddMLIRPython.cmake
    M mlir/cmake/modules/MLIRDetectPythonEnv.cmake
    M mlir/docs/Dialects/Linalg/OpDSL.md
    M mlir/docs/Dialects/Transform.md
    M mlir/examples/standalone/pyproject.toml
    M mlir/examples/standalone/python/CMakeLists.txt
    A mlir/examples/standalone/python/StandaloneExtensionPybind11.cpp
    A mlir/examples/standalone/python/mlir_standalone/dialects/standalone_pybind11.py
    M mlir/examples/standalone/test/python/smoketest.py
    A mlir/include/mlir/Bindings/Python/PybindAdaptors.h
    M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
    M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
    M mlir/python/CMakeLists.txt
    M mlir/python/mlir/dialects/python_test.py
    M mlir/python/mlir/ir.py
    M mlir/python/requirements.txt
    M mlir/test/Dialect/LLVMIR/invalid.mlir
    M mlir/test/python/dialects/python_test.py
    M mlir/test/python/lib/CMakeLists.txt
    A mlir/test/python/lib/PythonTestModulePybind11.cpp
    M mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in
    A orc-rt/unittests/DirectCaller.h
    M orc-rt/unittests/SPSWrapperFunctionTest.cpp
    M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
    M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
    M utils/bazel/llvm-project-overlay/llvm/driver.bzl
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

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