[all-commits] [llvm/llvm-project] 93f2e0: [CI] Make cache_lit_timing_files.py Script Gracefu...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Tue Oct 7 16:14:52 PDT 2025
Branch: refs/heads/users/vitalybuka/spr/nfcspecialcaselist-rename-specialcaselistinsectionblame-and-move-into-section
Home: https://github.com/llvm/llvm-project
Commit: 93f2e0a4433f5f7ede3aeccda0a44c8482c3022d
https://github.com/llvm/llvm-project/commit/93f2e0a4433f5f7ede3aeccda0a44c8482c3022d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M .ci/cache_lit_timing_files.py
Log Message:
-----------
[CI] Make cache_lit_timing_files.py Script Gracefully Fail (#162316)
This is a performance optimization and does not impact test fidelity.
There have been some flakes where this script will fail to download
files, exit with code 1, causing the job to fail before it even starts
running tests. This is undesirable as the tests will only run 10-15%
slower without this, so catch the exceptions and emit a warning we can
track later in the rare case we cannot download the timing files.
This fixes #162294.
Commit: 0cee4db636ae802e6d2ecf2e53c4538f3354736e
https://github.com/llvm/llvm-project/commit/0cee4db636ae802e6d2ecf2e53c4538f3354736e
Author: Marco Elver <elver at google.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/CodeGen/CodeGenFunction.cpp
Log Message:
-----------
[Clang][CodeGen] Introduce the AllocToken SanitizerKind (#162098)
Introduce the "alloc-token" sanitizer kind, in preparation of wiring it
up. Currently this is a no-op, and any attempt to enable it will result
in failure:
clang: error: unsupported option '-fsanitize=alloc-token' for target
'x86_64-unknown-linux-gnu'
In this step we can already wire up the `sanitize_alloc_token` IR
attribute where the instrumentation is enabled. Subsequent changes will
complete wiring up the AllocToken pass.
---
This change is part of the following series:
1. https://github.com/llvm/llvm-project/pull/160131
2. https://github.com/llvm/llvm-project/pull/156838
3. https://github.com/llvm/llvm-project/pull/162098
4. https://github.com/llvm/llvm-project/pull/162099
5. https://github.com/llvm/llvm-project/pull/156839
6. https://github.com/llvm/llvm-project/pull/156840
7. https://github.com/llvm/llvm-project/pull/156841
8. https://github.com/llvm/llvm-project/pull/156842
Commit: d0d18a80e52749a95e18acc39772fc3a21108e66
https://github.com/llvm/llvm-project/commit/d0d18a80e52749a95e18acc39772fc3a21108e66
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
Log Message:
-----------
[RISCV] Remove -rc1 from Zacas/Zabha version comment. NFC (#162331)
Commit: 631719d0d9ce7616f82aef22bab59ab82eb7cec2
https://github.com/llvm/llvm-project/commit/631719d0d9ce7616f82aef22bab59ab82eb7cec2
Author: Marco Elver <elver at google.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CodeGenFunction.h
Log Message:
-----------
[Clang][CodeGen] Emit !alloc_token for new expressions (#162099)
For new expressions, the allocated type is syntactically known and we
can trivially emit the !alloc_token metadata. A subsequent change will
wire up the AllocToken pass and introduce appropriate tests.
---
This change is part of the following series:
1. https://github.com/llvm/llvm-project/pull/160131
2. https://github.com/llvm/llvm-project/pull/156838
3. https://github.com/llvm/llvm-project/pull/162098
4. https://github.com/llvm/llvm-project/pull/162099
5. https://github.com/llvm/llvm-project/pull/156839
6. https://github.com/llvm/llvm-project/pull/156840
7. https://github.com/llvm/llvm-project/pull/156841
8. https://github.com/llvm/llvm-project/pull/156842
Commit: e166816af0fc53723866608e1ff79f0a75ebcfdb
https://github.com/llvm/llvm-project/commit/e166816af0fc53723866608e1ff79f0a75ebcfdb
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
Log Message:
-----------
[WebKit Checkers] Treat a boxed value as a safe pointer origin (#161133)
Commit: 872c4319dfc52886bbac03955ba1b7fe3ce83efc
https://github.com/llvm/llvm-project/commit/872c4319dfc52886bbac03955ba1b7fe3ce83efc
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
Log Message:
-----------
[WebKit Checkers] Recognize NSApp as a safe global variable (#160990)
Treat accessing NSApp without retaining it as safe
Commit: c5e343022cedd107559411378e6e008ef87b3caf
https://github.com/llvm/llvm-project/commit/c5e343022cedd107559411378e6e008ef87b3caf
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/docs/ClangLinkerWrapper.rst
M clang/docs/index.rst
Log Message:
-----------
[Clang][Docs] Fix leftoever references to moved documenation
Commit: 11fb8358fab2796e6cdc5f85d24cc33696317b11
https://github.com/llvm/llvm-project/commit/11fb8358fab2796e6cdc5f85d24cc33696317b11
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M libc/src/__support/RPC/rpc_server.h
Log Message:
-----------
[libc] Make LIBC_EXIT RPC code use quick exit
Summary:
This RPC call does the final exiting. The callbacks were handled on the
GPU side and this is only 'valid' in the pretend mode where we treat the
GPU like a CPU program. Doing this keeps us from crashing and burning
if people continue using the program while this is running as `exit`
would tear down the offloading library in memory and lead to segfaults.
This just drops everything where it is and lets the process manager
clean it up for us.
Commit: 750a36186525f18f769833a359ebc72a4f26f937
https://github.com/llvm/llvm-project/commit/750a36186525f18f769833a359ebc72a4f26f937
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
Log Message:
-----------
[RISCV] Add RV32 Zabha RUN lines to atomic-rmw.ll. NFC
We already had RV64 RUN lines.
Commit: aed73d2afeecace1e38f9a85ec94d0aa05e86bda
https://github.com/llvm/llvm-project/commit/aed73d2afeecace1e38f9a85ec94d0aa05e86bda
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M mlir/python/mlir/ir.py
Log Message:
-----------
[MLIR][Python] hide globals in ir.py (#162339)
We're shadowing the Python builtin function `globals` in `ir.py` and
therefore anywhere someone does `from mlir.ir import *`. So hide it.
Commit: 981dadcd60481939bdc8917c6f15cb6232313bc1
https://github.com/llvm/llvm-project/commit/981dadcd60481939bdc8917c6f15cb6232313bc1
Author: Martin Storsjö <martin at martin.st>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M libcxx/src/system_error.cpp
Log Message:
-----------
[libcxx] Map Windows ERROR_NETNAME_DELETED to no_such_file_or_directory (#162257)
This fixes spurious failures in
std/input.output/filesystems/fs.op.funcs/fs.op.proximate/proximate.pass.cpp
on Windows.
As part of that test, libcxx tries to open a fake network path such as
"//foo/a". Normally, this sets the error ERROR_BAD_NETPATH, which is
mapped to no_such_file_or_directory. However occasionally, it can end up
setting the error ERROR_NETNAME_DELETED instead.
Map ERROR_NETNAME_DELETED to no_such_file_or_directory just like
ERROR_BAD_NETPATH is mapped. This makes these cases be treated equally
within the create_file_status function in
src/filesystem/file_descriptor.h, causing the __weakly_canonical
function in operations.cpp to keep iterating, rather than erroring out.
Commit: 7546bd38041612e8b768f4b315e491cd549d608c
https://github.com/llvm/llvm-project/commit/7546bd38041612e8b768f4b315e491cd549d608c
Author: Janet Yang <qxy11 at meta.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Target/TargetList.h
M lldb/include/lldb/lldb-defines.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetList.cpp
M lldb/test/API/python_api/debugger/TestDebuggerAPI.py
Log Message:
-----------
[lldb] Add support for unique target ids (#160736)
### Summary
Add support for unique target ids per Target instance. This is needed
for upcoming changes to allow debugger instances to be shared across
separate DAP instances for child process debugging. We want the IDE to
be able to attach to existing targets in an already runny lldb-dap
session, and having a unique ID per target would make that easier.
Each Target instance will have its own unique id, and uses a
function-local counter in `TargetList::CreateTargetInternal` to assign
incremental unique ids.
### Tests
Added several unit tests to test basic functionality, uniqueness of
targets, and target deletion doesn't affect the uniqueness.
```
bin/lldb-dotest -p TestDebuggerAPI
```
Commit: 605e2d1fdd26bc78b824a8b97c1f2eafbcbe5a54
https://github.com/llvm/llvm-project/commit/605e2d1fdd26bc78b824a8b97c1f2eafbcbe5a54
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M lldb/unittests/Host/MainLoopTest.cpp
Log Message:
-----------
[lldb] Make MainLoopTest::CallbackWithTimeout slightly more resilient (#162197)
Compute the start time *before* registering the callback, rather than
after, to avoid the possibility of a small race.
The following scenario illustrates the problem.
1. The callback is registered with a 2 second timeout at t=0ms.
2. We compute the start time after registering the callback. For the
sake of argument, let's say it took 5ms to return from registering the
callback and computing the current time. Start=5ms.
3. The callback fires after exactly 2 seconds, or t=2000ms.
4. We compute the difference between start and now. If it took less than
5ms to compute, then we end up with a difference that's less than 2000ms
and the test fails. Let's say it took 3ms this time, then
2003ms-5ms=1998ms < 2000ms.
The actual values in the example above are arbitrary. All that matters
is that it took longer to compute the start time than the end time. My
theory is that this explains why this test is flaky when running under
ASan in CI (which has unpredictable timing).
rdar://160956999
Commit: c7d776b06897567e2d698e447d80279664b67d47
https://github.com/llvm/llvm-project/commit/c7d776b06897567e2d698e447d80279664b67d47
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
R bolt/docs/PacRetDesign.md
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlus.h
M bolt/include/bolt/Core/MCPlusBuilder.h
R bolt/include/bolt/Passes/InsertNegateRAStatePass.h
R bolt/include/bolt/Passes/MarkRAStates.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryBasicBlock.cpp
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/Exceptions.cpp
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/lib/Passes/CMakeLists.txt
R bolt/lib/Passes/InsertNegateRAStatePass.cpp
R bolt/lib/Passes/MarkRAStates.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
R bolt/test/AArch64/negate-ra-state-disallow.s
R bolt/test/AArch64/negate-ra-state-incorrect.s
R bolt/test/AArch64/negate-ra-state-reorder.s
R bolt/test/AArch64/negate-ra-state.s
R bolt/test/AArch64/pacret-split-funcs.s
R bolt/test/runtime/AArch64/negate-ra-state.cpp
R bolt/test/runtime/AArch64/pacret-function-split.cpp
Log Message:
-----------
Revert "[BOLT][AArch64] Handle OpNegateRAState to enable optimizing binaries with pac-ret hardening" (#162353)
Reverts llvm/llvm-project#120064.
@gulfemsavrun reported that the patch broke toolchain builders.
Commit: 0df5fc7d825d2b279ecd283ca002834c223853ff
https://github.com/llvm/llvm-project/commit/0df5fc7d825d2b279ecd283ca002834c223853ff
Author: Rolf Morel <rolf.morel at intel.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M mlir/docs/Dialects/Transform.md
Log Message:
-----------
[MLIR][Transform] Docs: add SMT extension section and fix Tune header (#161560)
Commit: 70c1c8f8007746040e256186d1e23b65d7590e00
https://github.com/llvm/llvm-project/commit/70c1c8f8007746040e256186d1e23b65d7590e00
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
A llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll
Log Message:
-----------
[VPlan] Create SCEV expansion for epilogue check first.
VPExpandSCEVRecipes must be at the beginning of the entry block.
addMinimumEpilogueIterationCheck currently creates VPInstructions to
compute the remaining iterations before potentially creating
VPExpandSCEVRecipes.
Fix this by first creating any SCEV expansions if needed.
Fixes https://github.com/llvm/llvm-project/issues/162128.
Commit: 0d758de6fbbe52d5001aa25b46bbe1c8b9206971
https://github.com/llvm/llvm-project/commit/0d758de6fbbe52d5001aa25b46bbe1c8b9206971
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/test/Dialect/LLVMIR/invalid.mlir
Log Message:
-----------
[MLIR][XeVM] blockload and blockstore ops should use scalar types (#161708)
instead of single element vectors.
XeVM type system does not support single element vectors.
Commit: 47820b1260b4f3282792e89a42272758c777c51c
https://github.com/llvm/llvm-project/commit/47820b1260b4f3282792e89a42272758c777c51c
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
A clang/test/Driver/darwin-maccatalyst-error.c
M clang/test/Driver/darwin-maccatalyst.c
Log Message:
-----------
[tests] Split up darwin-macatalyst test (#162358)
The way this test was constructed made it difficult to test downstream
divergence correctly; instead split the error case.
Commit: 879f8616ef93b5f3732568aeabdade6af26094f7
https://github.com/llvm/llvm-project/commit/879f8616ef93b5f3732568aeabdade6af26094f7
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/include/llvm/Analysis/IR2Vec.h
A llvm/include/llvm/CodeGen/MIR2Vec.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
A llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
A llvm/lib/CodeGen/MIR2Vec.cpp
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
A llvm/test/CodeGen/MIR2Vec/vocab-basic.ll
A llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll
M llvm/tools/llc/llc.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/MIR2VecTest.cpp
Log Message:
-----------
[IR2Vec] Initial infrastructure for MIR2Vec (#161463)
This PR introduces the initial infrastructure and vocabulary necessary for generating embeddings for MIR (discussed briefly in the earlier IR2Vec RFC - https://discourse.llvm.org/t/rfc-enhancing-mlgo-inlining-with-ir2vec-embeddings). The MIR2Vec embeddings are useful in driving target specific optimizations that work on MIR like register allocation.
(Tracking issue - #141817)
Commit: edb43192516a55165cc4c158eb4fd4b2d81a8fce
https://github.com/llvm/llvm-project/commit/edb43192516a55165cc4c158eb4fd4b2d81a8fce
Author: Brad Smith <brad at comstyle.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64.c
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
Log Message:
-----------
[FMV][AArch64] Add initial AT_HWCAP3 / AT_HWCAP4 support (#161595)
Add support for AT_HWCAP3 / AT_HWCAP4 which is supported by glibc, musl,
Android and FreeBSD 15/-current.
Stop using sys/ifunc.h as libgcc has done. This is more portable as
older glibc will not have the hwcap3/4 fields.
Commit: c95f5bbe6f6b1d20aadcb717c56d97c81fc40ee0
https://github.com/llvm/llvm-project/commit/c95f5bbe6f6b1d20aadcb717c56d97c81fc40ee0
Author: Joshua Rodriguez <josh.rodriguez at arm.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
A llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
Log Message:
-----------
[AArch64][GlobalISel] Prevented llvm.aarch64.neon.saddlp/uaddlp fallback (#160883)
Prevented fallback on G_SADDLP/G_UADDLP instructions that return
one-element i64 vectors, caused due to incorrect Register Bank
Selection.
Commit: 5f7dc8ad11c096a556d49ee676bb627eb8b5cd11
https://github.com/llvm/llvm-project/commit/5f7dc8ad11c096a556d49ee676bb627eb8b5cd11
Author: Fei Peng <pengfei.02 at bytedance.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
Log Message:
-----------
[compiler-rt][TSan] Fix TSan compile error on Android (#162369)
Commit: 125f0ac75796bc6807c98796bc1c5fff858acc7e
https://github.com/llvm/llvm-project/commit/125f0ac75796bc6807c98796bc1c5fff858acc7e
Author: David Green <david.green at arm.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/ARM/llrint-conv.ll
M llvm/test/CodeGen/ARM/lrint-conv.ll
M llvm/test/CodeGen/ARM/vector-lrint.ll
Log Message:
-----------
[ARM][SDAG] Half promote llvm.lrint nodes. (#161088)
As shown in #137101, fp16 lrint are not handled correctly on Arm. This
adds soft-half promotion for them, reusing the function that promotes a
value with operands (and can handle strict fp once that is added).
Commit: 57f69232da622569d3a06ecb717fbf713aa8d457
https://github.com/llvm/llvm-project/commit/57f69232da622569d3a06ecb717fbf713aa8d457
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/test/Driver/env.c
Log Message:
-----------
Disable Driver/env.c on AIX (NFC) (#161874)
AIX does not use LD_LIBRARY_PATH.
Commit: 5c613f287df7fc94e159621f870f1bb1fe3baaee
https://github.com/llvm/llvm-project/commit/5c613f287df7fc94e159621f870f1bb1fe3baaee
Author: Erik Enikeev <47039011+Varnike at users.noreply.github.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
M llvm/test/CodeGen/ARM/bf16_fast_math.ll
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
M llvm/test/CodeGen/ARM/fp16_fast_math.ll
M llvm/test/CodeGen/ARM/ipra-reg-usage.ll
M llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
M llvm/test/CodeGen/Thumb2/swp-regpressure.mir
Log Message:
-----------
[ARM] Add mayRaiseFPException to appropriate instructions and mark all instructions that read/write fpscr rounding bits as doing so (#160698)
Added new register FPSCR_RM to correctly model interactions with
rounding mode control bits of fpscr and to avoid performance regressions
in normal non-strictfp case
This PR is part of the work on adding strict FP support in ARM, which
was previously discussed in #137101.
Commit: 30b9ef8088c35d86fbdffebe0ba8cdcea1afe6eb
https://github.com/llvm/llvm-project/commit/30b9ef8088c35d86fbdffebe0ba8cdcea1afe6eb
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
Log Message:
-----------
[RISCV] Factor out the core part of LMULWriteResMXVariant. NFC (#162347)
LMULWriteResMXVariant is a helper class that makes creating LMUL-aware
`SchedVar` easier. In preparation for later patches that require
- LMUL- _and_ SEW-aware `SchedVar`
- Assign different processor resources for predicated and non-predicated
variants
I factor out the core logics of LMULWriteResMXVariant into another impl
class, such that it'll be easier to add _"LMULSEWWriteResMXSEWVariant"_
easier later. I also extend this class so that users can customize
processor resources for the non-predicated variant.
Despite these, this patch is still a NFC. I thought it'll be cleaner not
to mix the changes here into later patches.
Commit: b54f01e91163abb7cfcca76da34efebbee4622b4
https://github.com/llvm/llvm-project/commit/b54f01e91163abb7cfcca76da34efebbee4622b4
Author: Ahmed Bougacha <ahmed at bougacha.org>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/test/Driver/aarch64-cpu-defaults-appleos26.c
Log Message:
-----------
[AArch64] Bump default CPUs for iOS 18/watchOS 26 to A10/S9. (#162325)
We previously bumped the defaults for 26.0 Apple OS targets to
conservative CPU targets in 69d141712a10.
We can further bump it for watchOS arm64 (which lets us be a little bit
more aggressive than arm64e/arm64_32), as well as for the iOS
predecessor, iOS 18.
Commit: 7ab7554ef6e1eb45791d047eb332837e6d7d603f
https://github.com/llvm/llvm-project/commit/7ab7554ef6e1eb45791d047eb332837e6d7d603f
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M lldb/tools/debugserver/source/RNBRemote.cpp
Log Message:
-----------
[debugserver][NFC] Add helper function for escaping special characters (#162297)
This code was duplicated in multiple places and a subsequent patch will
need to do it again.
Commit: 25933f62dc261c394361ff8b42f40196ee36f44e
https://github.com/llvm/llvm-project/commit/25933f62dc261c394361ff8b42f40196ee36f44e
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M lldb/tools/debugserver/source/RNBRemote.cpp
Log Message:
-----------
[debugserver][NFC] Make helper functions have internal linkage (#162307)
This also allowed deleting unreachable code.
Commit: 2a2324a6eae7447be07ed95a24d5b335c9513450
https://github.com/llvm/llvm-project/commit/2a2324a6eae7447be07ed95a24d5b335c9513450
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/include/clang/AST/HLSLResource.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/resource_binding_attr.hlsl
M clang/test/AST/HLSL/vk_binding_attr.hlsl
Log Message:
-----------
[HLSL] Do not remove `HLSLVkBindingAttr` if the target is not SPIR-V (#161752)
The attribute needs to be preserved for rewriter scenarios. Two places were updated to use the `ResourceBindingAttrs` helper struct to make sure the `HLSLVkBindingAttr` is ignored when the target is DirectX.
Commit: 84cb38684b03f83f5e7412c1ac447d8037e32fc3
https://github.com/llvm/llvm-project/commit/84cb38684b03f83f5e7412c1ac447d8037e32fc3
Author: CatherineMoore <catmoore at amd.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[OpenMP] Update OpenMP 6.0 implementation status. (#162379)
Please review
Commit: 57b5ba00cb421b9be17bac10036763f42fbe9298
https://github.com/llvm/llvm-project/commit/57b5ba00cb421b9be17bac10036763f42fbe9298
Author: Brad Smith <brad at comstyle.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
Log Message:
-----------
[FMV][AArch64] Fix build after edb43192516a55165cc4c158eb4fd4b2d81a8fce (#162383)
Revert removal of local variables.
Commit: 198f29469a159e8418734e18edb60e33cb476462
https://github.com/llvm/llvm-project/commit/198f29469a159e8418734e18edb60e33cb476462
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
A llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s
Log Message:
-----------
[RISCV] Add missing vector floating point scheduling model tests for SiFive7 (#162386)
This is helpful on validating the non-throttled vector FP64 performance,
compared to the throttled model of sifive-x390.
Commit: 7f82996cd2b5e062e835b7aa3b99ecfdf54eeeb5
https://github.com/llvm/llvm-project/commit/7f82996cd2b5e062e835b7aa3b99ecfdf54eeeb5
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/unittests/CodeGen/MIR2VecTest.cpp
Log Message:
-----------
[MIR2Vec] Fixing non x86 unittest failures (#162381)
Fixing failures due to #161463
Commit: 699f085791872f9006e25d1369327e1ddc44002e
https://github.com/llvm/llvm-project/commit/699f085791872f9006e25d1369327e1ddc44002e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M clang/include/clang/Basic/SanitizerSpecialCaseList.h
M clang/lib/Basic/SanitizerSpecialCaseList.cpp
Log Message:
-----------
[NFC][SanitizerSection] Store Section& instead of Entries and FileIdx (#162382)
Commit: 33e82e663d3ae15c4f73afa79bf8d27d66156311
https://github.com/llvm/llvm-project/commit/33e82e663d3ae15c4f73afa79bf8d27d66156311
Author: Anthony Latsis <alatsis at apple.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/test/tools/llvm-ar/extract.test
M llvm/test/tools/llvm-ar/print.test
Log Message:
-----------
[test] llvm-ar: Adjust 2 tests to pass again after inadvertent unXFAIL for some target triples (#159796)
The problem with the current `target={{.*}}-darwin{{.*}}` XFAIL
condition (changed in https://github.com/llvm/llvm-project/pull/130144)
is that the Swift build script uses Apple platform names like 'macosx',
not 'darwin', for the LLVM target triple, e.g. `arm64-apple-macosx13.0`.
These tests appear to have been originally XFAILed because the default
format on macOS (darwin) adds newlines as padding to align members. See:
https://github.com/llvm/llvm-project/blob/ee8394d9469a2946ffe2e7d192c593ecf3f93098/llvm/lib/Object/ArchiveWriter.cpp#L897-L904
Use `--format=gnu` to cope with the differences in the output and
reenable the tests.
rdar://157213658
Commit: ca1a1f47da0a073de838748b9b7067d7f10e8c92
https://github.com/llvm/llvm-project/commit/ca1a1f47da0a073de838748b9b7067d7f10e8c92
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Support/SpecialCaseList.cpp
Log Message:
-----------
[NFC][SpecialCaseList] Generalize "#!special-case-list-v" parsing (#162350)
Commit: 768f438c6a31aecfecb848f560a8f698d80d908f
https://github.com/llvm/llvm-project/commit/768f438c6a31aecfecb848f560a8f698d80d908f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
Log Message:
-----------
[RISCV][GISel] Add Zalasr RUN lines to atomic-load-store-fp.ll. NFC (#162204)
After #161774 and #162042, this works correctly.
Commit: 5290515d897b9860855640b07a44cfc727e09c1c
https://github.com/llvm/llvm-project/commit/5290515d897b9860855640b07a44cfc727e09c1c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M .ci/cache_lit_timing_files.py
R bolt/docs/PacRetDesign.md
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlus.h
M bolt/include/bolt/Core/MCPlusBuilder.h
R bolt/include/bolt/Passes/InsertNegateRAStatePass.h
R bolt/include/bolt/Passes/MarkRAStates.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryBasicBlock.cpp
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/Exceptions.cpp
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/lib/Passes/CMakeLists.txt
R bolt/lib/Passes/InsertNegateRAStatePass.cpp
R bolt/lib/Passes/MarkRAStates.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
R bolt/test/AArch64/negate-ra-state-disallow.s
R bolt/test/AArch64/negate-ra-state-incorrect.s
R bolt/test/AArch64/negate-ra-state-reorder.s
R bolt/test/AArch64/negate-ra-state.s
R bolt/test/AArch64/pacret-split-funcs.s
R bolt/test/runtime/AArch64/negate-ra-state.cpp
R bolt/test/runtime/AArch64/pacret-function-split.cpp
M clang/docs/ClangLinkerWrapper.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/index.rst
M clang/include/clang/AST/HLSLResource.h
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/AST/HLSL/resource_binding_attr.hlsl
M clang/test/AST/HLSL/vk_binding_attr.hlsl
M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/Driver/aarch64-cpu-defaults-appleos26.c
A clang/test/Driver/darwin-maccatalyst-error.c
M clang/test/Driver/darwin-maccatalyst.c
M clang/test/Driver/env.c
M compiler-rt/lib/builtins/cpu_model/aarch64.c
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
M libc/src/__support/RPC/rpc_server.h
M libcxx/src/system_error.cpp
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Target/TargetList.h
M lldb/include/lldb/lldb-defines.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetList.cpp
M lldb/test/API/python_api/debugger/TestDebuggerAPI.py
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M llvm/include/llvm/Analysis/IR2Vec.h
A llvm/include/llvm/CodeGen/MIR2Vec.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
A llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
A llvm/lib/CodeGen/MIR2Vec.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/Support/SpecialCaseList.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
A llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
M llvm/test/CodeGen/ARM/bf16_fast_math.ll
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
M llvm/test/CodeGen/ARM/fp16_fast_math.ll
M llvm/test/CodeGen/ARM/ipra-reg-usage.ll
M llvm/test/CodeGen/ARM/llrint-conv.ll
M llvm/test/CodeGen/ARM/lrint-conv.ll
M llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
M llvm/test/CodeGen/ARM/vector-lrint.ll
M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
A llvm/test/CodeGen/MIR2Vec/vocab-basic.ll
A llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
M llvm/test/CodeGen/Thumb2/swp-regpressure.mir
A llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll
M llvm/test/tools/llvm-ar/extract.test
M llvm/test/tools/llvm-ar/print.test
A llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s
M llvm/tools/llc/llc.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/MIR2VecTest.cpp
M mlir/docs/Dialects/Transform.md
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/python/mlir/ir.py
M mlir/test/Dialect/LLVMIR/invalid.mlir
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.6
[skip ci]
Commit: e16103cf9f19196f33a7ed668d4719fcfdc8154c
https://github.com/llvm/llvm-project/commit/e16103cf9f19196f33a7ed668d4719fcfdc8154c
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M .ci/cache_lit_timing_files.py
R bolt/docs/PacRetDesign.md
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/include/bolt/Core/MCPlus.h
M bolt/include/bolt/Core/MCPlusBuilder.h
R bolt/include/bolt/Passes/InsertNegateRAStatePass.h
R bolt/include/bolt/Passes/MarkRAStates.h
M bolt/include/bolt/Utils/CommandLineOpts.h
M bolt/lib/Core/BinaryBasicBlock.cpp
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/Exceptions.cpp
M bolt/lib/Core/MCPlusBuilder.cpp
M bolt/lib/Passes/CMakeLists.txt
R bolt/lib/Passes/InsertNegateRAStatePass.cpp
R bolt/lib/Passes/MarkRAStates.cpp
M bolt/lib/Rewrite/BinaryPassManager.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
R bolt/test/AArch64/negate-ra-state-disallow.s
R bolt/test/AArch64/negate-ra-state-incorrect.s
R bolt/test/AArch64/negate-ra-state-reorder.s
R bolt/test/AArch64/negate-ra-state.s
R bolt/test/AArch64/pacret-split-funcs.s
R bolt/test/runtime/AArch64/negate-ra-state.cpp
R bolt/test/runtime/AArch64/pacret-function-split.cpp
M clang/docs/ClangLinkerWrapper.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/index.rst
M clang/include/clang/AST/HLSLResource.h
M clang/include/clang/Basic/Sanitizers.def
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/test/AST/HLSL/resource_binding_attr.hlsl
M clang/test/AST/HLSL/vk_binding_attr.hlsl
M clang/test/Analysis/Checkers/WebKit/objc-mock-types.h
M clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm
M clang/test/Driver/aarch64-cpu-defaults-appleos26.c
A clang/test/Driver/darwin-maccatalyst-error.c
M clang/test/Driver/darwin-maccatalyst.c
M clang/test/Driver/env.c
M compiler-rt/lib/builtins/cpu_model/aarch64.c
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc
M compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc
M compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
M libc/src/__support/RPC/rpc_server.h
M libcxx/src/system_error.cpp
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Target/TargetList.h
M lldb/include/lldb/lldb-defines.h
M lldb/source/API/SBDebugger.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetList.cpp
M lldb/test/API/python_api/debugger/TestDebuggerAPI.py
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/unittests/Host/MainLoopTest.cpp
M llvm/include/llvm/Analysis/IR2Vec.h
A llvm/include/llvm/CodeGen/MIR2Vec.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/InitializePasses.h
A llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGen.cpp
A llvm/lib/CodeGen/MIR2Vec.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/Support/SpecialCaseList.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMInstrVFP.td
M llvm/lib/Target/ARM/ARMRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
A llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
M llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir
M llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
M llvm/test/CodeGen/ARM/bf16_fast_math.ll
M llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
M llvm/test/CodeGen/ARM/fp16-litpool-arm.mir
M llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir
M llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir
M llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir
M llvm/test/CodeGen/ARM/fp16_fast_math.ll
M llvm/test/CodeGen/ARM/ipra-reg-usage.ll
M llvm/test/CodeGen/ARM/llrint-conv.ll
M llvm/test/CodeGen/ARM/lrint-conv.ll
M llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir
M llvm/test/CodeGen/ARM/vector-lrint.ll
M llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json
A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt
A llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt
A llvm/test/CodeGen/MIR2Vec/vocab-basic.ll
A llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll
M llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
M llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir
M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
M llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir
M llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir
M llvm/test/CodeGen/Thumb2/swp-fixedii.mir
M llvm/test/CodeGen/Thumb2/swp-regpressure.mir
A llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll
M llvm/test/tools/llvm-ar/extract.test
M llvm/test/tools/llvm-ar/print.test
A llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s
M llvm/tools/llc/llc.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
A llvm/unittests/CodeGen/MIR2VecTest.cpp
M mlir/docs/Dialects/Transform.md
M mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp
M mlir/python/mlir/ir.py
M mlir/test/Dialect/LLVMIR/invalid.mlir
Log Message:
-----------
rebase
Created using spr 1.3.6
Compare: https://github.com/llvm/llvm-project/compare/1f4d103d0c36...e16103cf9f19
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