[all-commits] [llvm/llvm-project] 616e52: Fixing memory leaks in tests (#161878)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Mon Oct 6 10:44:41 PDT 2025
Branch: refs/heads/users/alexey-bataev/spr/slpenable-sdivudiv-support-as-main-op-in-copyables
Home: https://github.com/llvm/llvm-project
Commit: 616e5230c7e31caae2c58b46c9655a3617a437a3
https://github.com/llvm/llvm-project/commit/616e5230c7e31caae2c58b46c9655a3617a437a3
Author: S. VenkataKeerthy <31350914+svkeerthy at users.noreply.github.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/unittests/Analysis/FunctionPropertiesAnalysisTest.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
Log Message:
-----------
Fixing memory leaks in tests (#161878)
Fixing the memory leaks introduced (#158376) in the unit tests of
FunctionPropertiesAnalysis and IR2Vec.
Commit: eabfed8690a1e87056140c1b311f82457e27feb9
https://github.com/llvm/llvm-project/commit/eabfed8690a1e87056140c1b311f82457e27feb9
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for modernize-use-bool-literals in VectorEmulateNarrowType.cpp (NFC)
Commit: aea5399919ade83f587a57395ed606528f1985f2
https://github.com/llvm/llvm-project/commit/aea5399919ade83f587a57395ed606528f1985f2
Author: Fateme Hosseini <136356764+fhossein-quic at users.noreply.github.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
A llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
Log Message:
-----------
[Hexagon] Support lowering of setuo & seto for vector types in Hexagon (#158740)
Resolves instruction selection failure for v64f16 and v32f32 vector
types.
Patch by: Fateme Hosseini
---------
Co-authored-by: Kaushik Kulkarni <quic_kauskulk at quicinc.com>
Commit: 478048df443a25d75f7cb2dd7b50ba94e73303c2
https://github.com/llvm/llvm-project/commit/478048df443a25d75f7cb2dd7b50ba94e73303c2
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[mlir][acc] Add firstprivate operands to `acc.loop` (#161881)
Add support for firstprivate operands to the OpenACC loop construct,
enabling representation of privatization scenarios that require
initialization from original values.
Commit: 16f5a85fb648027b9644b21c8c0fa9188d6c39b9
https://github.com/llvm/llvm-project/commit/16f5a85fb648027b9644b21c8c0fa9188d6c39b9
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
A clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
A clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CIR/IR/func.cir
Log Message:
-----------
[CIR] Initial support for emitting coroutine body (#161616)
This PR adds new `FuncOp` attributes (`coroutine` and `builtin`) and
begins the implementation of the `emitCoroutineBody` function. Feature
markers were also added for guidance in future PRs.
Commit: 0cc2ad3c00e255a044ca65af2c09bdfbafc6143d
https://github.com/llvm/llvm-project/commit/0cc2ad3c00e255a044ca65af2c09bdfbafc6143d
Author: Nico Weber <thakis at chromium.org>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
Log Message:
-----------
[gn] port 1af8ed198828
Commit: 8284e4d7cd5cce7f14f820ea2a3f043311eb1d4c
https://github.com/llvm/llvm-project/commit/8284e4d7cd5cce7f14f820ea2a3f043311eb1d4c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
Log Message:
-----------
[RISCV] Remove unused uimm5i32 from RISCVGISel.td. NFC
Commit: 8ae30a3facd25c9c7c2cfb96b69466a6c4d22baa
https://github.com/llvm/llvm-project/commit/8ae30a3facd25c9c7c2cfb96b69466a6c4d22baa
Author: John Harrison <harjohn at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M lldb/include/lldb/Host/JSONTransport.h
M lldb/include/lldb/Protocol/MCP/MCPError.h
M lldb/include/lldb/Protocol/MCP/Protocol.h
M lldb/include/lldb/Protocol/MCP/Server.h
M lldb/include/lldb/Protocol/MCP/Transport.h
M lldb/source/Host/common/JSONTransport.cpp
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h
M lldb/source/Protocol/MCP/MCPError.cpp
M lldb/source/Protocol/MCP/Server.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Transport.h
M lldb/unittests/DAP/DAPTest.cpp
M lldb/unittests/DAP/Handler/DisconnectTest.cpp
M lldb/unittests/DAP/TestBase.cpp
M lldb/unittests/DAP/TestBase.h
M lldb/unittests/Host/JSONTransportTest.cpp
M lldb/unittests/Protocol/ProtocolMCPServerTest.cpp
M lldb/unittests/TestingSupport/Host/JSONTransportTestUtilities.h
Log Message:
-----------
[lldb] Adding A new Binding helper for JSONTransport. (#159160)
This adds a new Binding helper class to allow mapping of incoming and
outgoing requests / events to specific handlers.
This should make it easier to create new protocol implementations and
allow us to create a relay in the lldb-mcp binary.
Commit: 119216ead189f9a695ab6361ab86d0121e765797
https://github.com/llvm/llvm-project/commit/119216ead189f9a695ab6361ab86d0121e765797
Author: David Green <david.green at arm.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
M llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
Log Message:
-----------
[AArch64][GlobalISel] Use TargetConstant for shift immediates (#161527)
This changes the intrinsic definitions for shifts to use IntArg, which
in turn changes how the shifts are represented in SDAG to use
TargetConstant (and fixes up a number of ISel lowering places too). The
vecshift immediates are changed from ImmLeaf to TImmLeaf to keep them
matching the TargetConstant. On the GISel side the constant shift
amounts are then represented as immediate operands, not separate constants.
The end result is that this allows a few more patterns to match in GISel.
Commit: 272025e5afa858ebc6e49df88958b34a9b186f54
https://github.com/llvm/llvm-project/commit/272025e5afa858ebc6e49df88958b34a9b186f54
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
Log Message:
-----------
[RISCV] Remove unneeded anyext/trunc patterns from RISCVGISel.td. NFC
We have code to manually select these as copies already. There are
multiple combinations of types that need to be supported due to
s32 and s16 being legal for the GPR register bank. It's simpler
to handle generically than to write out all the patterns.
Commit: f5dc553e93293743f4c1e36dc119e4823f5970d3
https://github.com/llvm/llvm-project/commit/f5dc553e93293743f4c1e36dc119e4823f5970d3
Author: Martin Storsjö <martin at martin.st>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
[libcxx] [ci] Make the CI find the right version of Clang-cl (#161736)
We install a (or in practice, update a preexisting) copy of Clang, in
order to get a specific version that we want. At that point in the
procedure, this is the only version of Clang in the PATH.
However, the step of adding the MSVC build tools to the environment also
ends up adding another copy of Clang, bundled with MSVC, into the PATH.
Due to this, CMake ends up finding and preferring the older version of
Clang bundled with MSVC, rather than the one we intend to be used.
Manually add the directory of the version of Clang we want to use at the
head of the search path, after initializing the MSVC build tool
environment.
The directory name we add is a hardcoded guess of where it is installed
- this is not ideal, but seems like the most straightforward solution
for now.
Commit: 3b38314a2b69847305b692677dbe64f1eb43235a
https://github.com/llvm/llvm-project/commit/3b38314a2b69847305b692677dbe64f1eb43235a
Author: Alan Zhao <ayzhao at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-and-cmp.ll
M llvm/test/Transforms/InstCombine/select-or-cmp.ll
Log Message:
-----------
Reapply "[InstCombine] Preserve profile after folding select instructions with conditionals" (#161885) (#161890)
This reverts commit 572b579632fb79ea6eb562a537c9ff1280b3d4f5.
This is a reland of #159666 but with a fix moving the `extern`
declaration of the flag under the LLVM namespace, which is needed to fix
a linker error caused by #161240.
Commit: 99b0aafa4ae792104948e40d64d9fef6e8c7c93b
https://github.com/llvm/llvm-project/commit/99b0aafa4ae792104948e40d64d9fef6e8c7c93b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Log Message:
-----------
[AArch64] Use isStrongerThanMonotonic. NFC (#161866)
Commit: b86fef88c54b20812ed3f1a67869dcaa54a07882
https://github.com/llvm/llvm-project/commit/b86fef88c54b20812ed3f1a67869dcaa54a07882
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
A mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
Log Message:
-----------
[mlir][xegpu] Create a test pass for subgroup distribution. (#161592)
Current subgroup distribution test employ the entire
`xegpu-subgroup-distribute` pass which include multiple steps like
layout propagation, move func body into warp op, and distribute to work
items.
This makes it harder to isolate the testing for xegpu subgroup
distribution logic, because certain corner cases may be not supported
yet by other steps mentioned above.
This PR introduces a test pass for subgroup distribution logic and
isolate the testing for distribution logic. We plan to add more corner
case (that were not possible before) covering non-xegpu ops (like
vector) in next PRs.
This PR also include,
1. minor bug fixes in gather/scatter distribution.
2. bug fix in vector multi reduction lowering where it fails to retain
some layouts.
Commit: 178e2a704b1dc5209e4cc24866a2738c5bc468f3
https://github.com/llvm/llvm-project/commit/178e2a704b1dc5209e4cc24866a2738c5bc468f3
Author: Yatao Wang <ningxinr at live.cn>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/fpclamptosat.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/ARM/fpclamptosat.ll
M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/fpclamptosat.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
Log Message:
-----------
[LLVM][CodeGen] Check Non Saturate Case in isSaturatingMinMax (#160637)
Fix Issue #160611
Commit: be29612ffceac888f931dc45664f7c42cea9b598
https://github.com/llvm/llvm-project/commit/be29612ffceac888f931dc45664f7c42cea9b598
Author: ManuelJBrito <59119670+ManuelJBrito at users.noreply.github.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/NewGVN.cpp
A llvm/test/Transforms/NewGVN/pr159918.ll
Log Message:
-----------
[NewGVN] Remove returned arg simplification (#161865)
Replacing uses of the return value with the argument is already handled
in other passes, additionally it causes issues with memory value
numbering when the call is a memory defining intrinsic.
fixes #159918
Commit: b0ad9c293a493c5912ffee6c18191bf35095f9f7
https://github.com/llvm/llvm-project/commit/b0ad9c293a493c5912ffee6c18191bf35095f9f7
Author: Lucie Choi <ychoi0407 at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
A llvm/test/CodeGen/SPIRV/pointers/ptrcast-bitcast.ll
Log Message:
-----------
[SPIR-V] Fix `asdouble` issue in SPIRV codegen to correctly generate `OpBitCast` instruction. (#161891)
Generate `OpBitCast` instruction for pointer cast operation if the
element type is different.
The HLSL for the unit test is
```hlsl
StructuredBuffer<uint2> In : register(t0);
RWStructuredBuffer<double2> Out : register(u2);
[numthreads(1,1,1)]
void main() {
Out[0] = asdouble(In[0], In[1]);
}
```
Resolves https://github.com/llvm/llvm-project/issues/153513
Commit: 36dc2a941f531d6b5662f2ad2c11e7264e5d9622
https://github.com/llvm/llvm-project/commit/36dc2a941f531d6b5662f2ad2c11e7264e5d9622
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
Log Message:
-----------
[RISCV] Reverse the operands in ins for Zalasr store instructions. NFC (#161882)
Match the assembly printing order rather than sorting by operand name.
Tnis is consistent with normal store instructions.
Commit: 2a059042882ed5108478c635322e4e94439386f5
https://github.com/llvm/llvm-project/commit/2a059042882ed5108478c635322e4e94439386f5
Author: sstwcw <su3e8a96kzlver at posteo.net>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTestObjC.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Keep the ObjC selector name and `@selector` together (#160739)
Fixes #36459.
after
```Objective-C
- (void)test {
if ([object
respondsToSelector:@selector(
selectorNameThatIsReallyLong:param1:param2:)])
return;
}
```
before
```Objective-C
- (void)test {
if ([object respondsToSelector:@selector
(selectorNameThatIsReallyLong:param1:param2:)])
return;
}
```
Before this patch, the `ObjCMethodExpr` type was assigned to many kinds
of tokens. The rule for allowing breaking the line before the colon on
line TokenAnnotator.cpp:6289 was intended for method declarations and
calls. It matched the parenthesis following `@selector` by mistake. To
fix the problem, this patch adds a new type for `@selector`. Most of the
special things in the code related to the old type is intended for other
constructs. So most of the code related to the old type is not changed
in this patch.
Commit: 1d65d9ce06fef890389e61990d9c748162334e55
https://github.com/llvm/llvm-project/commit/1d65d9ce06fef890389e61990d9c748162334e55
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
[VPlan] Match legacy CM in ::computeCost if load is used by load/store.
If a load is scalarized because it is used by a load/store address, the
legacy cost model does not pass ScalarEvolution to getAddressComputationCost.
Match the behavior in VPReplicateRecipe::computeCost.
Commit: 50285eaa594618bc430114da17fcce3c24f36810
https://github.com/llvm/llvm-project/commit/50285eaa594618bc430114da17fcce3c24f36810
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
Log Message:
-----------
[OpenMP][Clang][NFC] Initializer all of ScanInfo member variables and add deleted copy ctor and assignment operator (#158130)
Static analysis flagged that we were not initializing all of the members
of ScanInfo, fix this so that they are all initialized. Also it pointed
out that we were not following the rule of three. We had a custom
destructor but not copy constructor or assignment. We should never copy
or assignment so defaulting them as deleted.
Commit: b8127cc8d0f5cb48c106199a059442e2719e8656
https://github.com/llvm/llvm-project/commit/b8127cc8d0f5cb48c106199a059442e2719e8656
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/true16-fold.mir
Log Message:
-----------
[AMDGPU][True16][CodeGen] fix v_mov_b16_t16 index in folding pass (#161764)
With true16 mode v_mov_b16_t16 is added as new foldable copy inst, but
the src operand is in different index.
Use the correct src index for v_mov_b16_t16.
Commit: 9c118aa6a6fedb1006a3a81ebca40f226e5abf93
https://github.com/llvm/llvm-project/commit/9c118aa6a6fedb1006a3a81ebca40f226e5abf93
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVGISel.td
Log Message:
-----------
[RISCV] Remove unusable pattern from RISCVGISel.td. NFC
This pattern doesn't have a GISelPredicateCode so it's only usable
in SDAG.
Commit: fb458aa91f8fa614086e855ab29749e81e834194
https://github.com/llvm/llvm-project/commit/fb458aa91f8fa614086e855ab29749e81e834194
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/hip-options.hip
M clang/test/Driver/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
A llvm/include/llvm/Support/Jobserver.h
M llvm/include/llvm/Support/ThreadPool.h
M llvm/include/llvm/Support/Threading.h
M llvm/lib/Support/CMakeLists.txt
A llvm/lib/Support/Jobserver.cpp
M llvm/lib/Support/Parallel.cpp
M llvm/lib/Support/ThreadPool.cpp
M llvm/lib/Support/Threading.cpp
A llvm/lib/Support/Unix/Jobserver.inc
A llvm/lib/Support/Windows/Jobserver.inc
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/JobserverTest.cpp
Log Message:
-----------
Reland "[LLVM] Add GNU make jobserver support (#145131)"
With fix for JobServerTest where default parallel scheduling
strategy is saved/restored.
Commit: 7f51a2a47d2e706d04855b0e41690ebafa2b3238
https://github.com/llvm/llvm-project/commit/7f51a2a47d2e706d04855b0e41690ebafa2b3238
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M lldb/source/Target/Language.cpp
M lldb/unittests/Target/CMakeLists.txt
A lldb/unittests/Target/Language.cpp
Log Message:
-----------
[lldb][Language] Simplify SourceLanguage::GetDescription (#161804)
Currently we don't benefit from the user-friendly names that
`LanguageDescription` returns because we would always use
`Language::GetNameForLanguageType`. I'm not aware of a situation where
`GetDescription` should prefer the non-human readable form of the name
with. This patch removes the call to `GetNameForLanguageType`.
`LanguageDescription` already handles languages that it doesn't know
about. For those it would return `Unknown`. The LLDB language types
should all be available via DWARF. If there are languages that don't map
cleanly between `lldb::LanguageType` and `DW_LANG`, then we should add
explicit support for that in the `SourceLanguage::SourceLanguage`
constructor.
Commit: 2c3724419c04c3b6d918eb4c2eec00a4372d2937
https://github.com/llvm/llvm-project/commit/2c3724419c04c3b6d918eb4c2eec00a4372d2937
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M lldb/include/lldb/Target/Language.h
M lldb/source/Target/Language.cpp
Log Message:
-----------
[lldb][Language] Add Language::GetDisplayNameForLanguageType API (#161803)
The intention for this API is to be used when presenting language names
to the user, e.g., in expression evaluation diagnostics or LLDB errors.
Most uses of `GetNameForLanguageType` can be probably replaced with
`GetDisplayNameForLanguageType`, but that's out of scope of this PR.
This uses `llvm::dwarf::LanguageDescription` under the hood, so we would
lose the version numbers in the names. If we deem those to be important,
we could switch to an implementation that hardcodes a list of
user-friendly names with version numbers included.
The intention is to use it from
https://github.com/llvm/llvm-project/pull/161688
Depends on https://github.com/llvm/llvm-project/pull/161804
Commit: df61e349bc4441640a825acefef753637a55633f
https://github.com/llvm/llvm-project/commit/df61e349bc4441640a825acefef753637a55633f
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
A openmp/runtime/test/transform/tile/intfor.F90
R openmp/runtime/test/transform/tile/intfor.f90
Log Message:
-----------
[OpenMP][test] .f90 -> .F90
The test makes use of the preprocessor, which requires a .F90 suffix
Commit: fc1df44dec6396a468edab8136b1969eede54509
https://github.com/llvm/llvm-project/commit/fc1df44dec6396a468edab8136b1969eede54509
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
Log Message:
-----------
[gn build] Port fb458aa91f8f
Commit: 162b87b0ac86f7604db245b67874fc6715b2f06b
https://github.com/llvm/llvm-project/commit/162b87b0ac86f7604db245b67874fc6715b2f06b
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/dotest.py
Log Message:
-----------
[lldb][yaml2macho-core] Set binary path for tests differently
The way I was setting the path to the yaml2macho-core tool for
API tests assumed that the llvm tool bin directory was the same
as the lldb tool bin directory. There are build configuration
styles where they are not. Set it the same way lldb-dap etc
are set to the lldb bin dir.
Commit: c488dca6564d11ae84fb482599996a9d310f370d
https://github.com/llvm/llvm-project/commit/c488dca6564d11ae84fb482599996a9d310f370d
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M lldb/unittests/Host/posix/HostTest.cpp
Log Message:
-----------
[lldb][test] check if CoreDumping is supported at runtime (#161385)
#160333 reimplementation but at runtime instead because of broken CI.
---------
Co-authored-by: Michael Buch <michaelbuch12 at gmail.com>
Co-authored-by: Daniel Thornburgh <mysterymath at gmail.com>
Commit: c2c2e4ec90d0c1d65fff34fc4835dc6ba1ab25fc
https://github.com/llvm/llvm-project/commit/c2c2e4ec90d0c1d65fff34fc4835dc6ba1ab25fc
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Log Message:
-----------
[SelectionDAG] Add support to dump DAGs with sorted nodes (#161097)
An alternative approach to #149732 , which sorts the DAG before dumping
it. That approach runs a risk of altering the codegen result as we don't
know if any of the downstream DAG users relies on the node ID, which was
updated as part of the sorting.
The new method proposed by this PR does not update the node ID or any of
the DAG's internal states: the newly added
`SelectionDAG::getTopologicallyOrderedNodes` is a const member function
that returns a list of all nodes in their topological order.
Commit: 4368616452476472e3d776c9ae72be34fa674146
https://github.com/llvm/llvm-project/commit/4368616452476472e3d776c9ae72be34fa674146
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M clang/lib/Tooling/DependencyScanning/CMakeLists.txt
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
Log Message:
-----------
[clang][Dependency Scanning] Refactor Scanning Compiler Instance Initialization (#161300)
This PR follows https://github.com/llvm/llvm-project/pull/160795, and it
is the second of a series of planned PRs to land
https://github.com/llvm/llvm-project/pull/160207 in smaller pieces.
The initialization steps before and within
`DependencyScanningAction::runInvocation` are broken up in to several
helper functions. The intention is to reuse the helper functions in a
followup PR to initialize the `CompilerInstanceWithContext`.
Part of work for rdar://136303612.
Commit: d322ebdeabf6acac6d1b1580c10abdbc7aef2802
https://github.com/llvm/llvm-project/commit/d322ebdeabf6acac6d1b1580c10abdbc7aef2802
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
A llvm/test/ThinLTO/X86/memprof-dups.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal.ll
Log Message:
-----------
[MemProf] Suppress duplicate clones in the LTO backend (#161551)
In some cases due to phase ordering issues with re-cloning during
function assignment, we may end up with duplicate clones in the
summaries (calling the same set of callee clones and/or allocation
hints).
Ideally we would fix this in the thin link, but for now, detect and
suppress these in the LTO backend. In order to satisfy possibly
cross-module references, make each duplicate an alias to the first
identical copy, which gets materialized.
This reduces ThinLTO backend compile times.
Commit: 1eaf081d5eee11ad5797d8825b0510d61a034099
https://github.com/llvm/llvm-project/commit/1eaf081d5eee11ad5797d8825b0510d61a034099
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
R clang/test/CodeGenHLSL/resources/AppendStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/resources/ConsumeStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/resources/RWStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/resources/StructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/resources/StructuredBuffers-elementtype.hlsl
Log Message:
-----------
[HLSL][NFC] Merge element type tests for structured buffers (#161895)
The change merges 4 similar test files into one file with multiple RUN: lines and uses macros to parametrize the test.
Commit: 0b543e39351a72f65521522fbe9f3622abc00b47
https://github.com/llvm/llvm-project/commit/0b543e39351a72f65521522fbe9f3622abc00b47
Author: Alex White <milkeeycat at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/Target/GenericOpcodes.td
Log Message:
-----------
[TableGen] Set `G_GLOBAL_VALUE` out operand type to `ptype0` (#161894)
I'm not familiar with how every target handles this generic opcode but I
think it shouldn't break anything and it makes sense to use `ptype0`
because `G_GLOBAL_VALUE` returns a pointer.
Commit: 716fe1cbd9496564ac3588069846a52b8539df65
https://github.com/llvm/llvm-project/commit/716fe1cbd9496564ac3588069846a52b8539df65
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
A flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90
Log Message:
-----------
[Flang][OpenMP] Fix negative array indexing with allocatable derived type array maps (#154193)
The main problem is that the previous intermediate map generation for
allocatable members wasn't quite handling negative bounds acccesses
correctly, it seems to require slightly more complicated access using
shape_shift/dimension information. So this more closely mimics what
Flang generates in other cases now.
There is still a path for non-Box types to go down the old route for the
moment, so it is possible we may still have issues with negative bounds
in these cases. But, that's better in another PR if we come across it,
instead of too much change in this one.
Commit: a4b297532d3b3555b70c8b047e7d0ef3457f6ac8
https://github.com/llvm/llvm-project/commit/a4b297532d3b3555b70c8b047e7d0ef3457f6ac8
Author: Jie Fu <jiefu at tencent.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
Log Message:
-----------
[SPIRV] Fix unused-variable warnings (NFC)
/llvm-project/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp:198:12:
error: unused variable 'dstBitWidth' [-Werror,-Wunused-variable]
auto dstBitWidth =
^
/llvm-project/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp:200:12:
error: unused variable 'srcBitWidth' [-Werror,-Wunused-variable]
auto srcBitWidth =
^
2 errors generated.
Commit: f3673c5e5bfef176b3f630d82ec2299390b8a69a
https://github.com/llvm/llvm-project/commit/f3673c5e5bfef176b3f630d82ec2299390b8a69a
Author: John Harrison <harjohn at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M lldb/unittests/Protocol/ProtocolMCPServerTest.cpp
M lldb/unittests/Protocol/ProtocolMCPTest.cpp
Log Message:
-----------
[lldb] Disabling tests in win32 to investigate the root cause. (#161931)
These tests are failing on win32 platforms, disabling while I
investigate the root cause.
Commit: cb8b48e583f8f31ef162bcbaabbe95815f08230d
https://github.com/llvm/llvm-project/commit/cb8b48e583f8f31ef162bcbaabbe95815f08230d
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
A llvm/test/TableGen/ResolveSchedClass.td
M llvm/utils/TableGen/SubtargetEmitter.cpp
Log Message:
-----------
[TableGen][MC] Pass a MCSubtargetInfo instance into resolveVariantSchedClassImpl (#161886)
`Target_MC::resolveVariantSchedClassImpl` is the implementation function
for `TargetGenMCSubtargetInfo::resolveVariantSchedClass`. Despite being
only called by `resolveVariantSchedClass`,
`resolveVariantSchedClassImpl` is still a standalone function that
cannot access a MCSubtargetInfo through `this` (i.e.
`TargetGenMCSubtargetInfo`). And having access to a `MCSubtargetInfo`
could be useful for some (future) SchedPredicate.
This patch modifies TableGen to generate `resolveVariantSchedClassImpl`
with an additional `MCSubtargetInfo` argument passing in. Note that this
does not change any public interface in either `TargetGenMCSubtargetInfo
` or `MCSubtargetInfo`, as `resolveVariantSchedClassImpl` is basically
an internal function.
Commit: 1a3f84864f9d69e0c98500349a638f6ee360322e
https://github.com/llvm/llvm-project/commit/1a3f84864f9d69e0c98500349a638f6ee360322e
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/signed-char-misuse.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/signed-char-misuse-with-option.cpp
Log Message:
-----------
[clang-tidy] Fix typoed option name in `bugprone-signed-char-misuse` (#161064)
Following the example of #158282.
Commit: 3896212ceab8fe963335e8a31b898b6099292c88
https://github.com/llvm/llvm-project/commit/3896212ceab8fe963335e8a31b898b6099292c88
Author: David Rivera <davidriverg at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.h
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/TargetInfo.h
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/address-space.c
A clang/test/CIR/IR/invalid-addrspace.cir
Log Message:
-----------
[CIR] Implement Target-specific address space handling support for `PointerType` (#161028)
This PR adds support for address spaces in CIR pointer types by:
1. Introducing a `TargetAddressSpaceAttr` to represent target-specific
numeric address spaces (A Lang-specific attribute is to be implemented
in a different PR)
2. Extending the `PointerType` to include an optional address space
parameter
3. Adding helper methods in `CIRBaseBuilder` to create pointers with
address spaces
4. Implementing custom parsers and printers for address space attributes
5. Updating the LLVM lowering to properly handle address spaces when
converting CIR to LLVM IR
The implementation allows for creating pointers with specific address
spaces, which is necessary for supporting language features like Clang's
`__attribute__((address_space(N)))`. Address spaces are preserved
through the CIR representation and correctly lowered to LLVM IR.
Commit: 1b30e49b9b37673a1e8437b54c077611789f60a3
https://github.com/llvm/llvm-project/commit/1b30e49b9b37673a1e8437b54c077611789f60a3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
A llvm/test/CodeGen/AMDGPU/.#llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
AMDGPU: Remove m0 classes (#161758)
These are singleton register classes, which are not a good idea
and also are unused.
Commit: 910e536fb09f39493906005b9a8d7d1fbcc20e28
https://github.com/llvm/llvm-project/commit/910e536fb09f39493906005b9a8d7d1fbcc20e28
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/switch_create.ll
Log Message:
-----------
[SimplifyCFG][profcheck] Synthesize profile for `br (X == 0 | X == 1), T, F1 -> switch` (#161549)
We cannot calculate the weights of the switch precisely, but we do know the probability of the default branch. We then split equally the remaining probability over the rest of the cases. If we did nothing, the static estimation could be considerably poorer.
Issue #147390
Commit: 977b546c32d8978bc5682125e64e84aeee41ee76
https://github.com/llvm/llvm-project/commit/977b546c32d8978bc5682125e64e84aeee41ee76
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/include/llvm/Target/TargetSchedule.td
M llvm/test/TableGen/ResolveSchedClass.td
M llvm/utils/TableGen/SubtargetEmitter.cpp
Log Message:
-----------
[TableGen][SchedModel] Introduce a new SchedPredicate that checks against SubtargetFeature (#161888)
Introduce a new SchedPredicate, `FeatureSchedPredicate`, that holds true
when a certain SubtargetFeature is enabled. This could be useful when we
want to configure a scheduling model with subtarget features.
I add this as a separate SchedPredicate rather than piggy-back on the
existing `SchedPredicate<[{....}]>` because first and foremost,
`SchedPredicate` is expected to only operate on MachineInstr, so it does
_not_ appear in `MCGenSubtargetInfo::resolveVariantSchedClass` but only
show up in `TargetGenSubtargetInfo::resolveSchedClass`. Yet I think
`FeatureSchedPredicate` will be useful for both MCInst and MachineInstr.
There is another subtle difference between `resolveVariantSchedClass`
and `resolveSchedClass` regarding how we access the MCSubtargetInfo
instance, if we really want to express `FeatureSchedPredicate` using
`SchedPredicate<[{.....}]>`.
So I thought it'll be easier to add another new SchedPredicate for
SubtargetFeature.
Commit: 4af3e8f1d4ae0a3eb45068bd12c3b67cb92a7a90
https://github.com/llvm/llvm-project/commit/4af3e8f1d4ae0a3eb45068bd12c3b67cb92a7a90
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
AMDGPU: Remove LDS_DIRECT_CLASS register class (#161762)
This is a singleton register class which is a bad idea,
and not actually used.
Commit: 5ec11900e5df2cb8abcd8626609d38c2a26f0940
https://github.com/llvm/llvm-project/commit/5ec11900e5df2cb8abcd8626609d38c2a26f0940
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[profcheck] Exclude new test cases for SPIRV and GVN transformations (#161941)
Commit: 5fe6479bf2dbd008d9e300c0ea2d1c1ff30ebe58
https://github.com/llvm/llvm-project/commit/5fe6479bf2dbd008d9e300c0ea2d1c1ff30ebe58
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/rangereduce.ll
Log Message:
-----------
[SimplifyCFG][profcheck] Handle branch weights in `simplifySwitchLookup` (#161739)
The switch becomes a conditional branch, one edge going to what was the default target of the switch, the other to a BB that performs a lookup in a table. The branch weights are accurately determinable from the ones of the switch.
Issue #147390
Commit: e61b6f63ed98041911853101c7e5821f0861765b
https://github.com/llvm/llvm-project/commit/e61b6f63ed98041911853101c7e5821f0861765b
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[nfc][profcheck] Re-sort exclude list (#161942)
Commit: b1e29ec3b73b9dd06656c7e30ace597ff72cde70
https://github.com/llvm/llvm-project/commit/b1e29ec3b73b9dd06656c7e30ace597ff72cde70
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M flang/include/flang/Parser/message.h
M flang/lib/Parser/message.cpp
M flang/test/Semantics/associated.f90
Log Message:
-----------
[flang] remove sequences of duplicate messages (#161916)
Fixes bug exposed by https://github.com/llvm/llvm-project/pull/161915 by keeping a cache of messages printed at a given location.
Commit: e95a571f402074ac438235b13a4099f43c4e822c
https://github.com/llvm/llvm-project/commit/e95a571f402074ac438235b13a4099f43c4e822c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Log Message:
-----------
[RISCV] Add i32 to some QC_SHLADD patterns to reduce RISCVGenDAGISel.inc size. NFC
The shift amount type is independent of the output type. We need to
force it to i32 to prevent tablegen from creating an unnecessary
i64 pattern.
Commit: 7fbfbab3324b88d75d68b2bdb3aed696be80d8d5
https://github.com/llvm/llvm-project/commit/7fbfbab3324b88d75d68b2bdb3aed696be80d8d5
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
Log Message:
-----------
[Clang][NFC] Avoid duplication in BuildDeductionGuideForTypeAlias (#161948)
This addresses the post-commit review https://github.com/llvm/llvm-project/pull/161035#discussion_r2403312649 from Shafik
Commit: 0ce7cbddd29bc857c6d500a6d754352d24254b71
https://github.com/llvm/llvm-project/commit/0ce7cbddd29bc857c6d500a6d754352d24254b71
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
Log Message:
-----------
[AMDGPU] Add another test for missing S_WAIT_XCNT (#161838)
Commit: cd32b9b6c3b2fda3a781d9ce0a0cf8e21c9d0137
https://github.com/llvm/llvm-project/commit/cd32b9b6c3b2fda3a781d9ce0a0cf8e21c9d0137
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/Object/MachO.h
M llvm/lib/BinaryFormat/MachO.cpp
M llvm/lib/Object/MachOObjectFile.cpp
Log Message:
-----------
[MachO] Move getArchTriple implementation into BinaryFormat. (#161468)
There's nothing ObjectFile specific about getArchTriple, so move it into
the BinaryFormat library so that clients can use it without taking a
dependence on libObject.
MachOObjectFile::getArchTriple is updated to call through to the moved
implementation.
Commit: 30f7c5d04c395e766bd778acfa46ee88e2ad300d
https://github.com/llvm/llvm-project/commit/30f7c5d04c395e766bd778acfa46ee88e2ad300d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/BitmaskEnum.h
M llvm/include/llvm/ADT/PointerUnion.h
M llvm/include/llvm/ADT/bit.h
M llvm/unittests/ADT/BitTest.cpp
Log Message:
-----------
[ADT] Add bit_width_constexpr (#161775)
This patch adds llvm::bit_width_constexpr, a constexpr version of
llvm::bit_width.
The new function is intended to serve as a marker. When we switch to
C++20, we will most likely go through functions in llvm/ADT/bit.h and
replace them with their counterparts from <bit>. With
llvm::bit_width_constexpr, we can easily replace its use with
std::bit_width.
This patch refactors a couple of places. Specifically:
- bitWidth in BitmaskEnum.h is replaced with the new function.
- bitsRequired in PointerUnion.h is redefined in terms of the new
function.
I've used Compiler Explorer to check the equivalence:
https://godbolt.org/z/1oKMK9Ez7
Commit: 2689abab42c98abb3bdeb8aad38744d3153c0c6b
https://github.com/llvm/llvm-project/commit/2689abab42c98abb3bdeb8aad38744d3153c0c6b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/include/llvm/IR/ValueMap.h
Log Message:
-----------
[IR] Consolidate ValueMap iterator classes (NFC) (#161777)
This patch consolidates ValueMapIterator and ValueMapConstIterator
into ValueMapIteratorImpl. ValueMapIteratorImpl takes a boolean
template parameter to determine whether it should act as a const
iterator or a non-const one. ValueMapIterator and
ValueMapConstIterator are now type aliases of ValueMapIteratorImpl.
Commit: 8af44b07db315baf9819d3395ab9efc64b26af08
https://github.com/llvm/llvm-project/commit/8af44b07db315baf9819d3395ab9efc64b26af08
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/include/llvm/Support/ScopedPrinter.h
Log Message:
-----------
[Support] Use a C++17 fold expression in ScopedPrinter.h (NFC) (#161778)
Commit: 93b01739563202436573b3fd4b5a3ad9142b55c3
https://github.com/llvm/llvm-project/commit/93b01739563202436573b3fd4b5a3ad9142b55c3
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M llvm/docs/ProgrammersManual.rst
Log Message:
-----------
[llvm] Proofread ProgrammersManual.rst (#161779)
Commit: 25e02a43fe6bf95c118d7c3862d7d7c4abe4dcde
https://github.com/llvm/llvm-project/commit/25e02a43fe6bf95c118d7c3862d7d7c4abe4dcde
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/Object/MachO.h
M llvm/lib/BinaryFormat/MachO.cpp
M llvm/lib/Object/MachOObjectFile.cpp
Log Message:
-----------
Revert "[MachO] Move getArchTriple implementation into BinaryFormat. (#161468)"
Reverts commit cd32b9b6c3b while I investigate some bot failures, e.g.
https://lab.llvm.org/buildbot/#/builders/10/builds/14784.
Commit: ad7334b067ced512d65cd7576b0472cf8fc0487c
https://github.com/llvm/llvm-project/commit/ad7334b067ced512d65cd7576b0472cf8fc0487c
Author: Amir Ayupov <aaupov at fb.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M bolt/utils/dot2html/d3-graphviz-template.html
Log Message:
-----------
[BOLT] Bump d3js version in dot2html
Commit: 823094e407d74ce1b2a805bbfa4a9cfaf743d23c
https://github.com/llvm/llvm-project/commit/823094e407d74ce1b2a805bbfa4a9cfaf743d23c
Author: Andre Kuhlenschmidt <andre.kuhlenschmidt at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M flang/lib/Evaluate/check-expression.cpp
M flang/test/Semantics/intrinsics03.f90
M flang/test/Semantics/intrinsics04.f90
A flang/test/Semantics/type-parameter-constant.f90
Log Message:
-----------
[flang][semantics] fix IsConstantExpr for intrinsic with optional argument (#161915)
fixes https://github.com/llvm/llvm-project/issues/161694
Exposes that some sequences of duplicate messages are being printed,
which is fixed in https://github.com/llvm/llvm-project/pull/161916 .
Commit: 54012102c4a8e8bba9b3b27291dab126e3521544
https://github.com/llvm/llvm-project/commit/54012102c4a8e8bba9b3b27291dab126e3521544
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/Object/MachO.h
M llvm/lib/BinaryFormat/MachO.cpp
M llvm/lib/Object/CMakeLists.txt
M llvm/lib/Object/MachOObjectFile.cpp
Log Message:
-----------
Reapply [MachO] Move getArchTriple implementation..." with fixes. (#161949)
This reapplies cd32b9b6c3b, which was reverted in 25e02a43fe6 due to bot
failures.
The failures all appear to be link errors due to the Object library not
depending on BinaryFormat. This commit adds the missing dependence.
Commit: 47361e7e0d3acb5b14f4a0dbd0b451bf7881eca2
https://github.com/llvm/llvm-project/commit/47361e7e0d3acb5b14f4a0dbd0b451bf7881eca2
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/test/CIR/CodeGen/struct.cpp
Log Message:
-----------
[CIR] Implement BinComma Expr for AggregateExpr (#161823)
Implement the BinComma Expr support for AggregateExpr
Commit: c06aa2e8137a7e27e0bd0296d2f489c44d47f6f2
https://github.com/llvm/llvm-project/commit/c06aa2e8137a7e27e0bd0296d2f489c44d47f6f2
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/BinaryFormat/MachO.h
M llvm/include/llvm/Object/MachO.h
M llvm/lib/BinaryFormat/MachO.cpp
M llvm/lib/Object/CMakeLists.txt
M llvm/lib/Object/MachOObjectFile.cpp
Log Message:
-----------
Revert "Reapply [MachO] Move getArchTriple impl... with fixes. (#161949)"
This reverts commit 54012102c4a8e8bba9b3b27291dab126e3521544 while I further
investigate bot failures. Apparently adding a dependence on BinaryFormat to
Object was insufficient to fix the original linker issues.
Commit: 8243c368b750cfe127aed3cd96c675b4499be7f9
https://github.com/llvm/llvm-project/commit/8243c368b750cfe127aed3cd96c675b4499be7f9
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
A clang/test/CIR/CodeGen/paren-init-list.cpp
Log Message:
-----------
[CIR] Upstream CXXParenListInitExpr for AggregateExpr (#161876)
Upstream the CXXParenListInitExpr support for AggregateExpr
Commit: 7c666e24807b4b2a07370a11706a4bff8f34aef2
https://github.com/llvm/llvm-project/commit/7c666e24807b4b2a07370a11706a4bff8f34aef2
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/test/CIR/CodeGen/struct.cpp
Log Message:
-----------
[CIR] Implement UnaryExtension for AggregateExpr (#161820)
Implement the UnaryExtension support for AggregateExpr
Commit: a6a78eb2f67257adf2aa0b86f40a58c61eb0f3e2
https://github.com/llvm/llvm-project/commit/a6a78eb2f67257adf2aa0b86f40a58c61eb0f3e2
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.h
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Support ComplexType in CallExpr args (#156236)
This change adds support for ComplexType in the CallExpr args
Issue: https://github.com/llvm/llvm-project/issues/141365
Commit: 9a2a4f65bc70712c667feaf0f6559f7ab94d7e11
https://github.com/llvm/llvm-project/commit/9a2a4f65bc70712c667feaf0f6559f7ab94d7e11
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/struct.cpp
Log Message:
-----------
[CIR] Implement emitAtomicInit for AggregateExpr (#161826)
Implement emitAtomicInit support for AggregateExpr
Commit: a368fb5205a305197b650cbbc7264085d133e3e3
https://github.com/llvm/llvm-project/commit/a368fb5205a305197b650cbbc7264085d133e3e3
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Update ComplexImagOp to work on scalar type (#161571)
Update cir::ComplexImagOp to make it visible on scalars
Issue https://github.com/llvm/llvm-project/issues/160568
Commit: 9ebf1e91759d74e703d02ff385dabf0a53ac58b9
https://github.com/llvm/llvm-project/commit/9ebf1e91759d74e703d02ff385dabf0a53ac58b9
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Log Message:
-----------
[NFC][InstCombine] Fix namespace usage in InstCombine (#161902)
Commit: e9330fd244f93c53b13a876769fe9555913e6028
https://github.com/llvm/llvm-project/commit/e9330fd244f93c53b13a876769fe9555913e6028
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
A llvm/include/llvm/TableGen/CodeGenHelpers.h
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M llvm/utils/TableGen/Basic/TargetFeaturesEmitter.cpp
M mlir/include/mlir/TableGen/CodeGenHelpers.h
M mlir/include/mlir/TableGen/Dialect.h
M mlir/lib/TableGen/CodeGenHelpers.cpp
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/DialectGen.cpp
M mlir/tools/mlir-tblgen/OmpOpGen.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
Log Message:
-----------
[NFC][TableGen] Migrate IfDef/Namespace emitter from MLIR to LLVM (#161744)
Commit: f3703f36ee5cf09b0fe86a25270d5923deb43788
https://github.com/llvm/llvm-project/commit/f3703f36ee5cf09b0fe86a25270d5923deb43788
Author: Owen Anderson <resistor at mac.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/utils/TableGen/CompressInstEmitter.cpp
Log Message:
-----------
[TableGen] Look up registers directly in the CodeGenRegBank in CompressInstEmitter, rather than indirecting via the name. (#161853)
The previous code was subtly incorrect, as it indexed the RegistersByName map using the tblgen Def name of the register, rather than the AsmName with which the table was initialized. But all of this indirection via the name was unnecessary.
Commit: 679d2b2ab618a1933c5feb216d665b703d80a650
https://github.com/llvm/llvm-project/commit/679d2b2ab618a1933c5feb216d665b703d80a650
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
Log Message:
-----------
AMDGPU: Fix using IRAttribute with nounwind for AMDGPUNoAGPR (#161954)
Don't think this did anything harmful, but it doesn't make sense
to report this as implementing nounwind handling.
Commit: 1f5fa79d26c8a92e35ccca39f6ae5323ad896d9e
https://github.com/llvm/llvm-project/commit/1f5fa79d26c8a92e35ccca39f6ae5323ad896d9e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[Github] Add pr-subscribers-infrastructure notifications (#142697)
This patch sets up the new PRs labeller for a
pr-subscribers-infrastructure team that can be used for recieving
notifications about infrastructure changes in the monorepo. This is
primarily centered around the .ci directory currently where most of the
action is taking place.
Commit: 648e65e2c51b58deb05b70d190f6a55063c93322
https://github.com/llvm/llvm-project/commit/648e65e2c51b58deb05b70d190f6a55063c93322
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
A .github/workflows/llvm-abi-tests.yml
R .github/workflows/llvm-tests.yml
Log Message:
-----------
[Github] Rename llvm-tests.yml workflow (#153866)
This check used to also run tests for everything, but has since been
modified to only run the ABI tests with actual testing being run through
the premerge configuration. This patch renames the workflow to better
reflect this.
Commit: 9e4af2ffa6e7ff4119b3975df76184bacb1fc209
https://github.com/llvm/llvm-project/commit/9e4af2ffa6e7ff4119b3975df76184bacb1fc209
Author: David Green <david.green at arm.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/test/CodeGen/ARM/llround-conv.ll
M llvm/test/CodeGen/ARM/lround-conv.ll
Log Message:
-----------
[ARM] Update and cleanup lround/llround tests. NFC
Similar to f4370fb801aa, the fp16 tests do not work yet.
Commit: 9dcfebfaee2defe51862699e8fa0c48f32916812
https://github.com/llvm/llvm-project/commit/9dcfebfaee2defe51862699e8fa0c48f32916812
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrCDE.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Log Message:
-----------
[ARM] Auto-decode vpred_n/vpred_r operands (#160282)
Make the operands auto-decodable by adding `bits<0>` fields to
instructions.
Now we try to decode a vpred_n/vpred_r operand only if the instruction
being decoded has one.
We still need post-decoding pass to check/advance VPT state.
Part of #156540.
Commit: cc127f086df8db320f2e07f5fe6a669433e0c5b0
https://github.com/llvm/llvm-project/commit/cc127f086df8db320f2e07f5fe6a669433e0c5b0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/MC/TargetRegistry.h
Log Message:
-----------
[TargetRegistry] Remove deprecated createTargetMachine (#161053)
This was included in the v21 release, so we can reasonably remove it
now. Add a TODO for the other functions that have not yet made it into a
release. It does not cost much to keep them around until the next
release given the small amount of code and should give a little bit of
extra time for some downstreams to migrate.
Commit: 6ee362e1b5eb52421e0e700074c40ff9e7e0205e
https://github.com/llvm/llvm-project/commit/6ee362e1b5eb52421e0e700074c40ff9e7e0205e
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M mlir/lib/Conversion/VectorToAMX/VectorToAMX.cpp
M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
Log Message:
-----------
[mlir][vector] Simplify rewrite pattern inheriting constructors. NFC. (#161966)
Use the `Base` type alias from
https://github.com/llvm/llvm-project/pull/158433.
Commit: 8a8a589f24e9520db28180b6651b632799513cb5
https://github.com/llvm/llvm-project/commit/8a8a589f24e9520db28180b6651b632799513cb5
Author: David Blaikie <dblaikie at gmail.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/docs/GitHub.rst
Log Message:
-----------
Update wording for GitHub CI/CD admin requests to direct to the LLVM Infrastructure Area Team (#150462)
(we should probably add some doc pages about governance/area teams/etc
that this
could link to... )
Commit: 85c7cea8aca5bc58a9bc52f79433569d3cf87ca9
https://github.com/llvm/llvm-project/commit/85c7cea8aca5bc58a9bc52f79433569d3cf87ca9
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/TypeSwitch.h
M llvm/unittests/ADT/TypeSwitchTest.cpp
Log Message:
-----------
[ADT] Add `DefaultUnreachable("msg")` to TypeSwitch (#161970)
This is to allow making it explicit that all the cases must be handled.
The error message is customizable.
Something similar was already supported using the conversion operator
for the typed case but less explicit. In the `void` case when
`TypeSwitch` doesn't return anything, this was not possible without a
custom lambda.
Commit: 9bfbff2c22f14d0494d324302bb5df0f7d2a7c45
https://github.com/llvm/llvm-project/commit/9bfbff2c22f14d0494d324302bb5df0f7d2a7c45
Author: Joseph Bak <36170953+josephbak at users.noreply.github.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M mlir/docs/Tutorials/CreatingADialect.md
Log Message:
-----------
[mlir][docs] Fix typo: 'DDR' → 'DRR' in Creating a Dialect tutorial (#161967)
Fixes a small typo in the Creating a Dialect tutorial.
The rewrite rules format should be DRR (Declarative Rewrite Rules), not
DDR.
Commit: e301a7bbe1fb7006b969c54675ec3813b45d82c7
https://github.com/llvm/llvm-project/commit/e301a7bbe1fb7006b969c54675ec3813b45d82c7
Author: Luke Lau <luke at igalia.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
Log Message:
-----------
[TTI] Remove getVPMemoryOpCost. NFC (#160838)
No target implements this and nothing calls it. The cost of
vp.load/store/gather/scatter etc. are handled by
BasicTTIImpl::getIntrinsicInstrCost which forwards it onto the
appropriate TTI::getMemoryOpCost/getGatherScatterOpCost etc.
Commit: 24c1bb60e321c16cb8247b45b080b2d5e02a2b31
https://github.com/llvm/llvm-project/commit/24c1bb60e321c16cb8247b45b080b2d5e02a2b31
Author: ssijaric-nv <ssijaric at nvidia.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCAsmInfoELF.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/MC/MCAsmInfoELF.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
M llvm/test/CodeGen/AArch64/trampoline.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/tools/llvm-mc/llvm-mc.cpp
Log Message:
-----------
[MC] Make .note.GNU-stack explicit for the trampoline case (#151754)
In the presence of trampolines, the .note.GNU-stack section is not emitted. The
absence of .note.GNU-stack results in the stack marked executable by some
linkers. But others require an explict .note.GNU-stack section.
The GNU ld 2.43 on x86 machines, for example, issues the following:
missing .note.GNU-stack section implies executable stack
NOTE: This behaviour is deprecated and will be removed in a future version of the linker
On one of the ARM machines, the absence of .note.GNU-stack results in the stack
marked as non-executable:
STACK off 0x0000000000000000 vaddr 0x0000000000000000 paddr 0x0000000000000000 align 2**4
filesz 0x0000000000000000 memsz 0x0000000000000000 flags rw-
This change just emits the explicit .note.GNU-stack and marks it executable if required.
Commit: 795a115d1919966df72079eb3bd82699bfb2fa58
https://github.com/llvm/llvm-project/commit/795a115d1919966df72079eb3bd82699bfb2fa58
Author: Luke Lau <luke at igalia.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
M llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll
M llvm/test/CodeGen/AArch64/peephole-and-tst.ll
M llvm/test/CodeGen/AArch64/reserveXreg-for-regalloc.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/ARM/combine-movc-sub.ll
M llvm/test/CodeGen/ARM/extract-bits.ll
M llvm/test/CodeGen/ARM/extract-lowbits.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/SystemZ/llvm.sincos.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination.ll
M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-phireg.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
M llvm/test/CodeGen/Thumb2/mve-qrintrsplat.ll
M llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
M llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
M llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
M llvm/test/CodeGen/X86/delete-dead-instrs-with-live-uses.mir
M llvm/test/CodeGen/X86/inalloca-invoke.ll
M llvm/test/CodeGen/X86/licm-regpressure.ll
Log Message:
-----------
[RegAlloc] Remove default restriction on non-trivial rematerialization (#159211)
In the register allocator we define non-trivial rematerialization as the
rematerlization of an instruction with virtual register uses.
We have been able to perform non-trivial rematerialization for a while,
but it has been prevented by default unless specifically overriden by
the target in `TargetTransformInfo::isReMaterializableImpl`. The
original reasoning for this given by the comment in the default
implementation is because we might increase a live range of the virtual
register, but we don't actually do this.
LiveRangeEdit::allUsesAvailableAt makes sure that we only rematerialize
instructions whose virtual registers are already live at the use sites.
https://reviews.llvm.org/D106408 had originally tried to remove this
restriction but it was reverted after some performance regressions were
reported. We think it is likely that the regressions were caused by the
fact that the old isTriviallyReMaterializable API sometimes returned
true for non-trivial rematerializations.
However https://github.com/llvm/llvm-project/pull/160377 recently split
the API out into a separate non-trivial and trivial version and updated
the call-sites accordingly, and
https://github.com/llvm/llvm-project/pull/160709 and #159180 fixed
heuristics which weren't accounting for the difference between
non-trivial and trivial.
With these fixes in place, this patch proposes to again allow
non-trivial rematerialization by default which reduces a significant
amount of spills and reloads across various targets.
For llvm-test-suite built with -O3 -flto, we get the following geomean
reduction in reloads:
- arm64-apple-darwin: 11.6%
- riscv64-linux-gnu: 8.1%
- x86_64-linux-gnu: 6.5%
Commit: 074308c64ba10a3346c65deda67501e7bfc58eaa
https://github.com/llvm/llvm-project/commit/074308c64ba10a3346c65deda67501e7bfc58eaa
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M orc-rt/unittests/CMakeLists.txt
R orc-rt/unittests/CommonTestUtils.cpp
M orc-rt/unittests/CommonTestUtils.h
M orc-rt/unittests/bind-test.cpp
Log Message:
-----------
[orc-rt] Support multiple copies of OpCounter unittest utility. (#161985)
This commit templatizes OpCounter with a size_t argument, allowing
multiple copies of OpCounter to be easily created. This functionality
will be used in upcoming unit tests that need to count operations on
several types at once.
Commit: 8181c3deae482769937bdcee68f381df4141eb24
https://github.com/llvm/llvm-project/commit/8181c3deae482769937bdcee68f381df4141eb24
Author: Twice <twice at apache.org>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M mlir/include/mlir-c/Rewrite.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/Rewrite.cpp
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/test/python/integration/dialects/pdl.py
Log Message:
-----------
[MLIR][Python] Expose the insertion point of pattern rewriter (#161001)
In [#160520](https://github.com/llvm/llvm-project/pull/160520), we
discussed the current limitations of PDL rewriting in Python (see [this
comment](https://github.com/llvm/llvm-project/pull/160520#issuecomment-3332326184)).
At the moment, we cannot create new operations in PDL native (python)
rewrite functions because the `PatternRewriter` APIs are not exposed.
This PR introduces bindings to retrieve the insertion point of the
`PatternRewriter`, enabling users to create new operations within Python
rewrite functions. With this capability, more complex rewrites e.g. with
branching and loops that involve op creations become possible.
---------
Co-authored-by: Maksim Levental <maksim.levental at gmail.com>
Commit: 3e78c313bcfa54f8d1f1bdf221611d461e56111c
https://github.com/llvm/llvm-project/commit/3e78c313bcfa54f8d1f1bdf221611d461e56111c
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M libc/shared/math.h
A libc/shared/math/exp2.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/common_constants.h
A libc/src/__support/math/exp2.h
M libc/src/math/generic/CMakeLists.txt
R libc/src/math/generic/common_constants.cpp
R libc/src/math/generic/common_constants.h
M libc/src/math/generic/exp2.cpp
M libc/src/math/generic/expm1.cpp
M libc/src/math/generic/expm1f.cpp
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log10f.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log1pf.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/log2f.cpp
M libc/src/math/generic/log_range_reduction.h
M libc/src/math/generic/logf.cpp
M libc/src/math/generic/pow.cpp
M libc/src/math/generic/powf.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor exp2 implementation to header-only in src/__support/math folder. (#161297)
Part of #147386
in preparation for: https://discourse.llvm.org/t/rfc-make-clang-builtin-math-functions-constexpr-with-llvm-libc-to-support-c-23-constexpr-math-functions/86450
Commit: 92d83134b44161cad50198e663b543b46d25b45a
https://github.com/llvm/llvm-project/commit/92d83134b44161cad50198e663b543b46d25b45a
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/test/SemaTemplate/concepts.cpp
Log Message:
-----------
[Clang] Fix concept paramater mapping and caching (#161994)
This expression is not handled by default in RAV, so our parameter
mapping and cache mechanism don't work when it appears in a template
argument list.
There are a few other expressions, such as PackIndexingExpr and
FunctionParmPackExpr, which are also no-ops by default. I don't have a
test case for them now, so let's leave those until users complain :/
There was also a bug in updating the parameter mapping, where the
AssociatedDecl was not updated accordingly.
Also also, this fixes another regression reported in
https://github.com/llvm/llvm-project/pull/161671#issuecomment-3367225480,
where we failed to account for the variable initializer in cache
profiling.
Relies on #161671
Fixes https://github.com/llvm/llvm-project/issues/161983
Fixes https://github.com/llvm/llvm-project/issues/161987
Commit: c41611bacb0ca72a283accd7680061421454e152
https://github.com/llvm/llvm-project/commit/c41611bacb0ca72a283accd7680061421454e152
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-gep.ll
Log Message:
-----------
[InstCombine] Fix pointer replacement in `foldSelectValueEquivalence` (#161701)
Closes https://github.com/llvm/llvm-project/issues/161636.
Compile-time impact (+0.06%):
https://llvm-compile-time-tracker.com/compare.php?from=c2ef022aa7413ddc9aba48fa6fbe6fbd0cb14e19&to=9a0f0302efc30580136d191e66bac929f08ee25f&stat=instructions%3Au
I used to disable this fold for pointers, because I cannot construct a
positive test that is covered by `foldSelectValueEquivalence ` but not
covered by `simplifySelectWithICmpCond`. But the IR diff shows we still
benefit from the fold in InstCombine:
+ Bail out on pointers:
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2880
+ This patch: https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2882
Commit: a7414796c0854a9e6f649d922a58aa63147ae2e4
https://github.com/llvm/llvm-project/commit/a7414796c0854a9e6f649d922a58aa63147ae2e4
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-10-04 (Sat, 04 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[MachineScheduler] Convert some of the debug prints into using LDBG. NFC (#161997)
These lines are heavily skewed and hard to read. Using the new LDBG
there instead.
NFC.
Commit: 505956eeb0943461f9f0c10f0cca0da185fa142d
https://github.com/llvm/llvm-project/commit/505956eeb0943461f9f0c10f0cca0da185fa142d
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaInit.cpp
M clang/test/Parser/cxx0x-lambda-expressions.cpp
M clang/test/SemaCXX/diagnose_if.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
Log Message:
-----------
[Clang] Use the templated declaration for DiagnoseUseOfDecl (#161900)
We missed the check of diagnose_if attributes for the constructor
templates, because we used the template declaration, rather than its
templated one.
Also, we can avoid the duplicate constraint checking because it's
already performed in overload resolution.
There are some diagnostic regressions, all of which are warnings for
uses of lambdas in C++03 mode, which I believe we should still diagnose.
Fixes https://github.com/llvm/llvm-project/issues/160776
Commit: 8dac6e28c951b33659f1f1f80e0dd553788abaab
https://github.com/llvm/llvm-project/commit/8dac6e28c951b33659f1f1f80e0dd553788abaab
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaCXX/builtin-assume-aligned.cpp
Log Message:
-----------
Reapply "[clang] Convert second arg of __builtin_assume_aligned to Co… (#161945)
…nstantExpr (#161314)" (#161719)
This reverts commit f1650cf91b01470ce44f47797663d59f00828493.
Commit: 5284c83a8ff143b2d93853d1209f06d7d571f865
https://github.com/llvm/llvm-project/commit/5284c83a8ff143b2d93853d1209f06d7d571f865
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
Revert "[MachineScheduler] Convert some of the debug prints into using LDBG. NFC (#161997)"
This reverts commit a7414796c0854a9e6f649d922a58aa63147ae2e4.
This breaks builds:
3355 | << SchedModel->getResourceName(CurrZone.getZoneCritResIdx()) << "\n";
| ~~~~~~~~~~ ^
/home/buildbot/workspace/bolt-aarch64-ubuntu-clang/llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp:3358:51: error: no member named 'getResourceName' in 'llvm::TargetSchedModel'
3358 | LDBG() << " RemainingLimit: " << SchedModel->getResourceName(OtherCritIdx)
| ~~~~~~~~~~ ^
2 errors generated.
E.g. https://lab.llvm.org/buildbot/#/builders/128/builds/7522
Commit: e8489c162b32d9bc458a0ec779b69a23c9de478d
https://github.com/llvm/llvm-project/commit/e8489c162b32d9bc458a0ec779b69a23c9de478d
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M orc-rt/include/orc-rt/SPSWrapperFunction.h
M orc-rt/include/orc-rt/WrapperFunction.h
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
Log Message:
-----------
[orc-rt] WrapperFunction::handle: add by-ref args, minimize temporaries. (#161999)
This adds support for WrapperFunction::handle handlers that take their
arguments by reference, rather than by value.
This commit also reduces the number of temporary objects created to
support SPS-transparent conversion in SPSWrapperFunction.
Commit: 0338350ccb506020529259427ec1c66ca6569749
https://github.com/llvm/llvm-project/commit/0338350ccb506020529259427ec1c66ca6569749
Author: Maxime Arthaud <maxime at arthaud.me>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/lib/IR/Core.cpp
M llvm/tools/llvm-c-test/debuginfo.c
Log Message:
-----------
[llvm-c] Add missing nullptr check in LLVMGetFirstDbgRecord (#151101)
I'm using the LLVM C bindings through the llvm-sys rust crate, and
noticed that LLVMGetFirstDbgRecord and LLVMGetLastDbgRecord are
segfault-ing when called on instructions without debug markers. I found
out it's missing a null pointer check. This PR fixes the issue.
Commit: ca5ece89394f64ab814032d9562b2e4770160523
https://github.com/llvm/llvm-project/commit/ca5ece89394f64ab814032d9562b2e4770160523
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstSimplify/domcondition.ll
Log Message:
-----------
[InstSimplify] Simplify fcmp implied by dominating fcmp (#161090)
This patch simplifies an fcmp into true/false if it is implied by a
dominating fcmp.
As an initial support, it only handles two cases:
+ `fcmp pred1, X, Y -> fcmp pred2, X, Y`: use set operations.
+ `fcmp pred1, X, C1 -> fcmp pred2, X, C2`: use `ConstantFPRange` and
set operations.
Note: It doesn't fix https://github.com/llvm/llvm-project/issues/70985,
as the second fcmp in the motivating case is not dominated by the edge.
We may need to adjust JumpThreading to handle this case.
Comptime impact (~+0.1%):
https://llvm-compile-time-tracker.com/compare.php?from=a728f213c863e4dd19f8969a417148d2951323c0&to=8ca70404fb0d66a824f39d83050ac38e2f1b25b9&stat=instructions:u
IR diff: https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2848
Commit: 90d5795a3da3c336bda3c9f9c2f85210395cf676
https://github.com/llvm/llvm-project/commit/90d5795a3da3c336bda3c9f9c2f85210395cf676
Author: Pranav Kant <prka at google.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
R llvm/test/CodeGen/AMDGPU/.#llvm.amdgcn.smfmac.gfx950.ll
Log Message:
-----------
[NFC] Remove accidently added file in #161758 (#161991)
Commit: f61789f5f6788322d8864f2c32021fd552f3f7b4
https://github.com/llvm/llvm-project/commit/f61789f5f6788322d8864f2c32021fd552f3f7b4
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/StringSwitch.h
M llvm/unittests/ADT/StringSwitchTest.cpp
Log Message:
-----------
[ADT] Add `DefaultUnreachable("msg")` to StringSwitch (#161976)
Similar to TypeSwitch (#161970), allow for explicit unreachable default
case with a custom error message on unhandled cases.
StringSwitch already allowed for checking if any of the cases matched
with the conversion operator, but `DefaultUnreachable` is more explicit
and allows for a custom message.
Commit: 1d01a8473908cf3422fee4905fcf82f160ae0be0
https://github.com/llvm/llvm-project/commit/1d01a8473908cf3422fee4905fcf82f160ae0be0
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Indent literal block properly (NFC)
Commit: 2ef3771175ff36e8a14a949e35fbba24f5ff3e73
https://github.com/llvm/llvm-project/commit/2ef3771175ff36e8a14a949e35fbba24f5ff3e73
Author: Ivan Dzuhan <nadare2357 at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/docs/GettingStarted.rst
Log Message:
-----------
[docs] Fix enumeration in GettingStarted.rst (#96684)
Commit: 76cff3bcdbe945c053f4c3a7d9c99c7c2ae2bb10
https://github.com/llvm/llvm-project/commit/76cff3bcdbe945c053f4c3a7d9c99c7c2ae2bb10
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M clang/include/clang/Sema/SemaConcept.h
Log Message:
-----------
[clang][Sema] NormalizedConstraint - fix MSVC "not all control paths return a value" warnings. NFC. (#162004)
Commit: 1af06cb636c780b2f24f247f0efc0576e411d9c4
https://github.com/llvm/llvm-project/commit/1af06cb636c780b2f24f247f0efc0576e411d9c4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][bytecode] interp__builtin_ia32_pshuf - modulo lane index to allow reuse of PSHUFD/LW/HW mask decode. NFC (#162006)
Removes need to offset PSHUFHW land index to extract the shuffle mask element.
Commit: 3149a7720f714c14f7e6320745d9e35f49dba62b
https://github.com/llvm/llvm-project/commit/3149a7720f714c14f7e6320745d9e35f49dba62b
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/test/CIR/CodeGen/struct.cpp
Log Message:
-----------
[CIR] Implement DesignatedInitUpdateExpr for AggregateExpr (#161897)
Implement the DesignatedInitUpdateExpr support for AggregateExpr
Commit: 94eade61a02ae5fc6e7e19f1aff8c0eeb0b0d0a0
https://github.com/llvm/llvm-project/commit/94eade61a02ae5fc6e7e19f1aff8c0eeb0b0d0a0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
Log Message:
-----------
Revert "[VPlan] Match legacy CM in ::computeCost if load is used by load/store."
This reverts commit 1d65d9ce06fef890389e61990d9c748162334e55 to fix
crashes, reported in the commits
Commit: f80c0baf058dbdc54d413cdc56a6c551dfa66387
https://github.com/llvm/llvm-project/commit/f80c0baf058dbdc54d413cdc56a6c551dfa66387
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
Revert "Reapply "[VPlan] Compute cost of more replicating loads/stores in ::computeCost. (#160053)" (#161724)"
This reverts commit 8f2466bc72a5ab163621cb1bf4bf53a27f1cefe7 to fix
crashes reported in commits
Commit: 718ef3427a2ddd09122e2185962e4b241848d8b9
https://github.com/llvm/llvm-project/commit/718ef3427a2ddd09122e2185962e4b241848d8b9
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/tools/llvm-c-test/debuginfo.c
Log Message:
-----------
[llvm-c-test] Fix warnings
This patch fixes:
llvm/tools/llvm-c-test/debuginfo.c:330:20: error: unused variable
'Phi1FirstDbgRecord' [-Werror,-Wunused-variable]
llvm/tools/llvm-c-test/debuginfo.c:332:20: error: unused variable
'Phi1LastDbgRecord' [-Werror,-Wunused-variable]
Commit: e543ca685791b7424fb99187507fd555ff7832d4
https://github.com/llvm/llvm-project/commit/e543ca685791b7424fb99187507fd555ff7832d4
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector][nfc] Add comments in tests (#160106)
Small follow-up for https://github.com/llvm/llvm-project/pull/158528,
otherwise it's not clear what makes the updated tests "negative".
Commit: 2121bda3424d7d8a18b4cd6718514be9bef5932e
https://github.com/llvm/llvm-project/commit/2121bda3424d7d8a18b4cd6718514be9bef5932e
Author: Andrey Ali Khan Bolshakov <bolsh.andrey at yandex.ru>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/DeclPrinter.cpp
M clang/test/AST/ast-print-record-decl.c
Log Message:
-----------
[clang][AST] Don't print inherited default template args (#161953)
Prior to this change, for the code like this:
```cpp
template <int, int = 0>
class Tpl;
template <int = 0, int>
class Tpl;
```
pretty-printing produced an uncompilable code:
```cpp
template <int, int = 0> class Tpl;
template <int = 0, int = 0> class Tpl;
```
Commit: 3ae7af70ce633f1dd552dc7ba3f1b000c66fc821
https://github.com/llvm/llvm-project/commit/3ae7af70ce633f1dd552dc7ba3f1b000c66fc821
Author: Yixuan Cao <caoyixuan2019 at email.szu.edu.cn>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/wcscat.cpp
M compiler-rt/test/asan/TestCases/wcscpy.cpp
M compiler-rt/test/asan/TestCases/wcsncat.cpp
M compiler-rt/test/asan/TestCases/wcsncpy.cpp
Log Message:
-----------
Revert "[compiler-rt][asan][tests] Stabilize wchar tests on Darwin/Android" (#162001)
Reverts llvm/llvm-project#161624
Commit: c793782b03aba045f3b8ae6aa90b7bb7b9579a09
https://github.com/llvm/llvm-project/commit/c793782b03aba045f3b8ae6aa90b7bb7b9579a09
Author: Thurston Dang <thurston at google.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/asan/asan_interceptors.h
M compiler-rt/lib/asan/asan_win_static_runtime_thunk.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
R compiler-rt/test/asan/TestCases/wcscat.cpp
R compiler-rt/test/asan/TestCases/wcscpy.cpp
R compiler-rt/test/asan/TestCases/wcsncat.cpp
R compiler-rt/test/asan/TestCases/wcsncpy.cpp
Log Message:
-----------
Revert "[compiler-rt][asan] Add wcscpy/wcsncpy; enable wcscat/wcsncat on Windows" (#162021)
Reverts llvm/llvm-project#160493 due to buildbot failures e.g.,
https://github.com/llvm/llvm-project/pull/160493#issuecomment-3357314356
The fix-forward (https://github.com/llvm/llvm-project/pull/161624) still
had failures on Darwin, and was reverted in
https://github.com/llvm/llvm-project/pull/162001 i.e., this pull request
completes the revert to green for this patch stack.
Commit: 4a2f29dd0ccbb378a7c0698a51f3dc42ee615ff4
https://github.com/llvm/llvm-project/commit/4a2f29dd0ccbb378a7c0698a51f3dc42ee615ff4
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/SemaTemplate/alias-template-deprecated.cpp
M clang/test/SemaTemplate/alias-templates.cpp
Log Message:
-----------
[clang] don't print redundant context notes when instantiating alias templates (#161986)
The redundant notes were introduced with the workaround for finding the
template instantiationa args for lambdas inside template type aliases.
This removes the notes for the cases where we are simply instantiating
an outer template, and when diagnosing uses of the alias template.
Also adds comments calling the workaround explicitly.
Commit: c40ee0f32218be0e7f0abd43f96f2f65d2bb1a2a
https://github.com/llvm/llvm-project/commit/c40ee0f32218be0e7f0abd43f96f2f65d2bb1a2a
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M llvm/include/llvm/Analysis/MemoryProfileInfo.h
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/test/ThinLTO/X86/memprof-basic.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
M llvm/unittests/Analysis/MemoryProfileInfoTest.cpp
Log Message:
-----------
Reapply "[MemProf] Add ambigous memprof attribute" (#161717) (#161918)
Reapply llvm/llvm-project#157204 with fix and a new test for the issue
it caused (the test change provoked the assert that was converted to an
if condition).
Also, make the application of this new attribute under an (on by
default) flag, so that it can be more easily disabled if needed. Add
test for the new flag.
Commit: 99d802a3332b25deae1c8c2be5b8875ba9926a4a
https://github.com/llvm/llvm-project/commit/99d802a3332b25deae1c8c2be5b8875ba9926a4a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/lib/Optimizer/Transforms/CUFComputeSharedMemoryOffsetsAndSize.cpp
M flang/test/Fir/CUDA/cuda-shared-offset.mlir
Log Message:
-----------
[flang][cuda] Fix linkage for dynamic shared memory (#161940)
Commit: 2e6da800484d9cf5a75a9a57919f855d7de70d42
https://github.com/llvm/llvm-project/commit/2e6da800484d9cf5a75a9a57919f855d7de70d42
Author: Yixuan Cao <caoyixuan2019 at email.szu.edu.cn>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M compiler-rt/lib/asan/asan_interceptors.cpp
M compiler-rt/lib/asan/asan_interceptors.h
M compiler-rt/lib/asan/asan_win_static_runtime_thunk.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
A compiler-rt/test/asan/TestCases/wcscat.cpp
A compiler-rt/test/asan/TestCases/wcscpy.cpp
A compiler-rt/test/asan/TestCases/wcsncat.cpp
A compiler-rt/test/asan/TestCases/wcsncpy.cpp
Log Message:
-----------
[compiler-rt][asan] Reland: wcscpy/wcsncpy interceptors and stabilize wchar tests on Darwin/Android (#162028)
### Summary
Reland: wcscpy/wcsncpy interceptors and stabilize wchar tests on
Darwin/Android. Functional reland (runtime + tests).
### Context
Reland of #160493 and #161624; previously reverted by #162021 and
#162001 to restore green.
### Motivation
- Restore wchar interceptors (wcscpy/wcsncpy), broaden ASan coverage,
and improve Windows parity with narrow-string checks.
- Make tests robust across Darwin/Android to keep bots green.
### Runtime (wcscpy/wcsncpy)
- Add overlap checks; mark read/write ranges in bytes.
- Use MaybeRealWcsnlen when available to bound reads.
- Register Windows static runtime thunk where applicable.
### Tests (wcscpy/wcsncpy/wcscat/wcsncat)
- Android: keep `%env_asan_opts=log_to_stderr=1` so the ASan header is
on stderr.
- Darwin: tolerate reordering by putting all four key lines in one DAG
group:
```cpp
// CHECK-DAG: Good so far.
// CHECK-DAG: ERROR: AddressSanitizer: stack-buffer-overflow on address [[ADDR:...]] at pc {{...}} bp {{...}} sp {{...}}
// CHECK-DAG: WRITE of size {{[0-9]+}} at [[ADDR]] thread T0
// CHECK-DAG: #0 {{0x[0-9a-f]+}} in <func>
```
### Risk
- Functional reland (runtime + tests), intended to restore functionality
and maintain stability across platforms.
---------
Signed-off-by: Yixuan Cao <caoyixuan2019 at email.szu.edu.cn>
Commit: 6f3d765d04041412e9801187eb261253c3ceb2a1
https://github.com/llvm/llvm-project/commit/6f3d765d04041412e9801187eb261253c3ceb2a1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
libclc: Add gfx1250 and gfx1251 to amdgpu target list (#162034)
Commit: 1f82e818faac8a2ff868ec364ce1f3de5ceebf2d
https://github.com/llvm/llvm-project/commit/1f82e818faac8a2ff868ec364ce1f3de5ceebf2d
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsNVPTX.td
M clang/test/CodeGen/builtins-nvptx.c
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/convert-sm103a.ll
Log Message:
-----------
[clang][NVPTX] Add intrinsics and builtins for CVT RS rounding mode (#160494)
This change adds LLVM intrinsics and clang builtins for the `cvt`
RS rounding mode instruction variants.
Tests are added in `convert-sm103a.ll` and verified through ptxas-13.0.
Commit: 6b1604ac30082cd7316f06c2b904cb23af95468e
https://github.com/llvm/llvm-project/commit/6b1604ac30082cd7316f06c2b904cb23af95468e
Author: Connector Switch <c8ef at outlook.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/netinet-in-macros.h
A libc/include/netinet/in.h.def
A libc/include/netinet/in.yaml
M libc/test/include/CMakeLists.txt
A libc/test/include/netinet_in_test.cpp
Log Message:
-----------
[libc] add IPPROTO related macros (#161855)
Commit: 36cfdebe927c34508c1e245b459da43b745ae620
https://github.com/llvm/llvm-project/commit/36cfdebe927c34508c1e245b459da43b745ae620
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M orc-rt/include/orc-rt/WrapperFunction.h
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
Log Message:
-----------
[orc-rt] Add method-wrapper utils for use with WrapperFunction::handle. (#162035)
WrapperFunction::handleWithAsyncMethod can be used to wrap asynchronous
methods (void methods whose first arguments are Return callbacks) for
use with WrapperFunction::handle.
WrapperFunction::handleWithSyncMethod can be used to wrap regular
(non-asynchronous) methods for use with WrapperFunction::handle.
Both variants return function objects that take a Return callback as
their first argument, and an ExecutorAddr representing the address of
the instance to call the object on. For asynchronous methods the
resulting function object (AsyncMethod<method-ptr>) forwards the Return
callback through to the method. For synchronous methods the method is
called and the result passed to the Return callback.
Commit: bbdcba9b851abe37cf2b10ec6d9b50c12cdd3604
https://github.com/llvm/llvm-project/commit/bbdcba9b851abe37cf2b10ec6d9b50c12cdd3604
Author: dianqk <dianqk at dianqk.net>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/Coroutines/coro-catchswitch-cleanuppad.ll
M llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
M llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
Log Message:
-----------
[SimplifyCFG] Fold the contiguous wrapping cases into ICmp. (#161000)
Fixes #157113.
Take the following IR as an example; we know the destination of the `[1,
3]` cases is `%else`.
```llvm
define i32 @src(i8 range(i8 0, 6) %arg) {
switch i8 %arg, label %else [
i8 0, label %if
i8 4, label %if
i8 5, label %if
]
if:
ret i32 0
else:
ret i32 1
}
```
We can first try the non-wrapping range for both destinations, but I
don't see how that would be any better.
Proof: https://alive2.llvm.org/ce/z/acdWD4.
Commit: bea0225c304e3f8efbca48f8c5ee4b39d8f42e0d
https://github.com/llvm/llvm-project/commit/bea0225c304e3f8efbca48f8c5ee4b39d8f42e0d
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/TargetParser/TargetParser.cpp
Log Message:
-----------
[AMDGPU] Make cluster a target feature (#162040)
This replaces the original arch check.
Commit: a406eb460c05e1171971ed1dace2546e3901eb61
https://github.com/llvm/llvm-project/commit/a406eb460c05e1171971ed1dace2546e3901eb61
Author: Luo, Yuanke <lyk_03 at hotmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/Sema/SemaDecl.cpp
M clang/test/SemaCUDA/vararg.cu
Log Message:
-----------
[CUDA] Remove CUDAAllowVariadicFunctions option and its sema check (#161350)
Variadic argument for NVPTX has been support in
https://github.com/llvm/llvm-project/commit/486d00eca6b6ab470e8324b52cdf9f32023c1c9a
We can remove `CUDAAllowVariadicFunctions` option and its sema check. The CC1 option
`fcuda_allow_variadic_functions` is retained to not break the existing code building.
---------
Co-authored-by: Yuanke Luo <ykluo at birentech.com>
Commit: 550b2ef041ba16ee8b5f55b5f2307f501b2c15a0
https://github.com/llvm/llvm-project/commit/550b2ef041ba16ee8b5f55b5f2307f501b2c15a0
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M lldb/unittests/Target/CMakeLists.txt
R lldb/unittests/Target/Language.cpp
A lldb/unittests/Target/LanguageTest.cpp
Log Message:
-----------
[lldb][test][NFC] Rename Language.cpp to LanguageTest.cpp
So it's consistent with the other tests in this directory.
Also aligns with the source file header comment.
Commit: 5e92e7f4c0fb9ab92572fb974591d52266be8fc6
https://github.com/llvm/llvm-project/commit/5e92e7f4c0fb9ab92572fb974591d52266be8fc6
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/test/Transforms/SCCP/relax-range-checks.ll
Log Message:
-----------
[SCCP] Strengthen two-instruction range checks (#162008)
This patch implements the todo discussed in
https://github.com/llvm/llvm-project/pull/158495#discussion_r2349609838.
It also fixes a regression introduced by
https://github.com/llvm/llvm-project/pull/161000. See also
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2890#discussion_r2404016316.
IR diff: https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2892
Commit: 7185dd66c7740159797834d57e52cfe38cf6e050
https://github.com/llvm/llvm-project/commit/7185dd66c7740159797834d57e52cfe38cf6e050
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vbmi2vl.s
Log Message:
-----------
[X86][AVX512] Add missing mayLoad attribute to AVX512 instructions (#162036)
Fixes crashes reported in #157034.
Commit: 732a3662736db4ef75b02ddbcdad23385446cea9
https://github.com/llvm/llvm-project/commit/732a3662736db4ef75b02ddbcdad23385446cea9
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Log Message:
-----------
[NFC][AArch64] Flatten a branch on AArch64InstrInfo::copyPhysReg (#161138)
Simplifies the code and improves readability.
Commit: ebbc0e97b991c98bbcacf3d49b54685ef1a73188
https://github.com/llvm/llvm-project/commit/ebbc0e97b991c98bbcacf3d49b54685ef1a73188
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
A llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
Log Message:
-----------
[AMDGPU] Remove subtarget features for dynamic VGPRs (#160822)
Users of the backend are expected to enable dynamic VGPRs via the
`amdgpu-dynamic-vgpr-block-size` attribute instead of the subtarget
features (see https://github.com/llvm/llvm-project/pull/133444).
Commit: e573c795e4938440aa1ddb0371568be69eb08390
https://github.com/llvm/llvm-project/commit/e573c795e4938440aa1ddb0371568be69eb08390
Author: rdez13 <140968532+rdez13 at users.noreply.github.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
Log Message:
-----------
[clang][x86][bytecode] Replace interp__builtin_rotate with static bool interp__builtin_elementwise_int_binop callback #160289 (#161924)
Fixes #160289
Commit: bd8a7f9ef394c7f722fc8ae3f852311550669e56
https://github.com/llvm/llvm-project/commit/bd8a7f9ef394c7f722fc8ae3f852311550669e56
Author: Kirill Vedernikov <kvedernikov at nvidia.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/CodeGen/NVPTX/wmma-ptx87-sm120a.py
M llvm/test/CodeGen/NVPTX/wmma.py
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[NVPTX] Added more MMA intrinsics for F8F6F4 and FP64 types. (#156040)
This change adds more MMA intrinsics for F8F6F4 and FP64 types. The implementation is based on [PTX ISA version 9.0](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma). New restrictions were added for dtype/ctype combinations for MMA and sparse MMA intrinsics. MLIR restrictions for dtype/ctype MMA intrinsics were aligned with NVVM IR.
Commit: 38896d67e458cf4d3b5ce0c3742f48e97527c797
https://github.com/llvm/llvm-project/commit/38896d67e458cf4d3b5ce0c3742f48e97527c797
Author: sskzakaria <ssskzakaria at proton.me>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/Headers/avx512vlintrin.h
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Headers][X86] Add constexpr support for some AVX512 masked extension/truncation intrinsics. (#161984)
The following AVX[512] intrinsics are now constexpr:
* _mm_cvtepi32_epi8
* _mm_cvtepi32_epi16
* _mm_cvtepi64_epi8
* _mm_cvtepi64_epi16
* _mm_cvtepi64_epi32
* _mm256_cvtepi32_epi8
* _mm256_cvtepi32_epi16
* _mm256_cvtepi64_epi8
* _mm256_cvtepi64_epi16
* _mm256_cvtepi64_epi32
* _mm256_mask_cvtepi64_epi32
* _mm256_maskz_cvtepi64_epi32
Fixes #154539
Commit: a9dafc9bdcfc1090d0744d0c708c5d133bc0fd84
https://github.com/llvm/llvm-project/commit/a9dafc9bdcfc1090d0744d0c708c5d133bc0fd84
Author: Jonas Hahnfeld <jonas.hahnfeld at cern.ch>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
A clang/test/Modules/pr133057.cpp
Log Message:
-----------
[Sema] Compare canonical conversion function (#154158)
With lazy template loading, it is possible to find non-canonical
FunctionDecls, depending on when redecl chains are completed. This
is a problem for templated conversion operators that would allow to
call either the copy assignment or the move assignment operator.
This ambiguity is resolved by isBetterReferenceBindingKind (called
from CompareStandardConversionSequences) ranking rvalue refs over
lvalue refs.
Unfortunately, this fix is hard to test in isolation without the
changes in https://github.com/llvm/llvm-project/pull/133057 that
make lazy template loading more likely to complete redecl chains
at "inconvenient" times. The added reproducer passes before and
after this commit, but would have failed with the proposed changes
of the linked PR.
Kudos to Maksim Ivanov for providing an initial version of the
reproducer that I further simplified.
Commit: b023ca9ce9359c2195795401c6c146e12db84f0e
https://github.com/llvm/llvm-project/commit/b023ca9ce9359c2195795401c6c146e12db84f0e
Author: Vincent <llvm at viceroygroup.ca>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/docs/PDB/HashTable.rst
Log Message:
-----------
[llvm][docs] Fixed documentation (#158795)
fixes #158643
Commit: af2059791e5f37822cc2984c102d7a0358d58243
https://github.com/llvm/llvm-project/commit/af2059791e5f37822cc2984c102d7a0358d58243
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
A llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
Log Message:
-----------
Reapply "[llvm-exegesis] Exclude loads/stores from aliasing instruction set" (#156735) (#159366)
Move the mayLoad/mayStore checks out of hasMemoryOperands; there are
instructions with these properties that don't have operands.
This is relanding 899ee375e99c04ef2c4a67dc70b266c929ad43f4 with a
minor tweak.
Commit: 1bd9c1bde38acddd71bf52fd3748d4c7fc75e8ba
https://github.com/llvm/llvm-project/commit/1bd9c1bde38acddd71bf52fd3748d4c7fc75e8ba
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter-tests/lit.local.cfg
M cross-project-tests/debuginfo-tests/dexter/feature_tests/lit.local.cfg
Log Message:
-----------
[Dexter] Allow retries on all dexter tests to avoid lldb-dap flakiness (#161847)
This isn't pretty but should help us keep the bot stable while issues
such as #158306 and #158311 are investigated
Commit: 1087c1079f870518b6bf6e2f6ed764d3e90611ae
https://github.com/llvm/llvm-project/commit/1087c1079f870518b6bf6e2f6ed764d3e90611ae
Author: lonely eagle <2020382038 at qq.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
R mlir/test/Transforms/buffer-results-to-out-params-elim.mlir
A mlir/test/Transforms/buffer-results-to-out-params-hosit-dynamic-allocs.mlir
A mlir/test/Transforms/buffer-results-to-out-params-hosit-static-allocs.mlir
Log Message:
-----------
[mlir][bufferize] Add hoist-dynamic-allocs-option to buffer-results-to-out-params (#160985)
Add hoist-dynamic-allocs-option to buffer-results-to-out-params. This PR
supported that obtain the size of the dynamic shape memref through the
caller-callee relationship.
Commit: a9ca220e8138f39d504faa48ba771dd90fd89838
https://github.com/llvm/llvm-project/commit/a9ca220e8138f39d504faa48ba771dd90fd89838
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/SMEInstrFormats.td
R llvm/test/CodeGen/AArch64/spill-fill-zpr-predicates.mir
M llvm/test/CodeGen/AArch64/ssve-stack-hazard-remarks.ll
Log Message:
-----------
[AArch64][SME] Remove support for `-arch64-enable-zpr-predicate-spills` (#161819)
This was a stop-gap solution until we implemented
`-aarch64-split-sve-objects`. It was never enabled by default, and
likely saw no real-world use.
Let's remove this to reduce the maintenance burden.
Commit: a13ff2cb027eaeffe67241bbc7f7308affb3aae7
https://github.com/llvm/llvm-project/commit/a13ff2cb027eaeffe67241bbc7f7308affb3aae7
Author: Bonsthie <barnabe.bonnet at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir
A llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec256.mir
A llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec512.mir
A llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier.mir
A llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec256.mir
A llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec512.mir
A llvm/test/CodeGen/X86/GlobalISel/select-freeze.mir
Log Message:
-----------
[X86][GISel] Add missing legalization for G_IMPLICIT_DEF (#161699)
Legalize scalar and vector integer types for `G_IMPLICIT_DEF` at
SSE2/AVX2/AVX-512 widths. This is groundwork for upcoming `G_*_VECTOR`
legalization, since vector inserts/builds rely on undef bases.
Commit: 69761e761c8d37f4fa96af4483c37c436fa7d295
https://github.com/llvm/llvm-project/commit/69761e761c8d37f4fa96af4483c37c436fa7d295
Author: Martin Storsjö <martin at martin.st>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/test/Headers/arm-acle-header.c
M clang/test/Headers/arm-cde-header.c
M clang/test/Headers/arm-cmse-header.c
M clang/test/Headers/arm-fp16-header.c
M clang/test/Headers/arm-neon-header.c
A clang/test/Headers/system_reserved_names.h
M clang/test/Headers/x86-intrinsics-headers-clean.cpp
M clang/test/Headers/x86-intrinsics-headers.c
Log Message:
-----------
[clang] [test] Verify that intrinsic headers don't use unreserved names (#161817)
This mirrors a similar test that libcxx does, to make sure that the
libcxx headers don't use any unreserved symbols.
The header for polluting with defines is based very far on the libcxx
one; some parts of it could possibly be omitted, but I included most of
it for completeness here.
This should allow catching these issues earlier, to avoid issues like
#161808 and #98478 happening again.
Commit: 4ab25977ea47c31a8b68fd607ec5f985de722fd4
https://github.com/llvm/llvm-project/commit/4ab25977ea47c31a8b68fd607ec5f985de722fd4
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M orc-rt/include/orc-rt/SPSWrapperFunction.h
Log Message:
-----------
[orc-rt] Remove incorrect noexcept specifiers.
Conversions between Error/Expected and their serializable counterparts may
throw.
Commit: 93073af121051738937313111e069b61a3bd09db
https://github.com/llvm/llvm-project/commit/93073af121051738937313111e069b61a3bd09db
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
Log Message:
-----------
[LV] Move 3 functions into VPlanTransforms (NFC) (#158644)
Two of them are actually transforms, and the third is a dependent
static.
Commit: 830373372c6e6776149948dd8d3044f06ce9780f
https://github.com/llvm/llvm-project/commit/830373372c6e6776149948dd8d3044f06ce9780f
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
A openmp/runtime/test/transform/tile/do.F90
A openmp/runtime/test/transform/tile/do_2d.f90
A openmp/runtime/test/transform/tile/do_2d_varsizes.f90
R openmp/runtime/test/transform/tile/intfor.F90
R openmp/runtime/test/transform/tile/intfor_2d.f90
R openmp/runtime/test/transform/tile/intfor_2d_varsizes.F90
A openmp/runtime/test/transform/unroll/heuristic_do.f90
R openmp/runtime/test/transform/unroll/heuristic_intdo.f90
Log Message:
-----------
[OpenMP] Clean-up Fortran tests
* Use "do" for DO loops, there is no "for" in Fortran and it is always
integer
* Add -cpp to not rely on file name case
* Add "implicit none" safety
Commit: 23f010f1ab09263d79027c70d5f4cddfe0055ca9
https://github.com/llvm/llvm-project/commit/23f010f1ab09263d79027c70d5f4cddfe0055ca9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
Log Message:
-----------
[clang] SemaConcept.cpp - fix MSVC "not all control paths return a value" warnings. NFC. (#162060)
Commit: 93408f5312a555bad59c4f75d83970ddb48e07ad
https://github.com/llvm/llvm-project/commit/93408f5312a555bad59c4f75d83970ddb48e07ad
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Log Message:
-----------
[AArch64] determineSVEStackSizes - fix MSVC signed/unsigned comparison failure. NFC. (#162059)
Commit: 913ae2d37219edbf992277ad909a8fddd1c2371a
https://github.com/llvm/llvm-project/commit/913ae2d37219edbf992277ad909a8fddd1c2371a
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/docs/HowToReleaseLLVM.rst
Log Message:
-----------
[llvm][docs] Minor fixes and improvements for release process (#151956)
- The list numbering in [1] currently starts again after item 3 due to
the code-block.
- Remove mentions of Phabricator and Subversion.
- In final step of [2] remove mention of
llvm/utils/git/sync-release-repo.sh, which was removed in #73682.
- Add direct links to:
- www-releases repo.
- backporting doc [3].
- Getting Started page.
- RELEASE_TESTERS.txt.
- Release Sources GitHub workflow.
[1] https://llvm.org/docs/HowToReleaseLLVM.html#create-release-branch
[2]
https://llvm.org/docs/HowToReleaseLLVM.html#triaging-bug-reports-for-releases
[3]
https://llvm.org/docs/GitHub.html#backporting-fixes-to-the-release-branches
Commit: 10da6f05cc4828c02ceebc8d0e2d8fbb03363a12
https://github.com/llvm/llvm-project/commit/10da6f05cc4828c02ceebc8d0e2d8fbb03363a12
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
Log Message:
-----------
[X86] x86-shrink-wrap-unwind.ll - regenerate test checks (#162061)
Commit: 4b05a12e9c0de38f54a6440a2cfe3741780418aa
https://github.com/llvm/llvm-project/commit/4b05a12e9c0de38f54a6440a2cfe3741780418aa
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M libcxx/test/std/experimental/simd/simd.class/simd_unary.pass.cpp
Log Message:
-----------
[libc++] Fix simd_unary.pass.cpp with AppleClang
When using AppleClang the `clang` feature flag is not set, but the
compiler supports `-flax-vector-conversions=integer`. This adds another
`ADDITIONAL_COMPILE_FLAGS` for AppleClang to fix the CI.
Commit: 5547c0cff3eec029318317cb263b0ddc37c5bfd0
https://github.com/llvm/llvm-project/commit/5547c0cff3eec029318317cb263b0ddc37c5bfd0
Author: Steven Perron <stevenperron at google.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizeImplicitBinding.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/hlsl-resources/test_counters.ll
Log Message:
-----------
[SPIRV] Implement LLVM IR and backend for typed buffer counters (#161425)
This commit implements the backend portion of the typed buffer counter
proposal described in
https://github.com/llvm/wg-hlsl/blob/main/proposals/0023-typed-buffer-counters.md.
This is the second part of the implementation, focusing on the LLVM IR
and SPIR-V backend.
Specifically, this commit implements the "LLVM IR Generation and Backend
Handling"
section of the proposal. This includes:
- Adding the `llvm.spv.resource.counterhandlefromimplicitbinding` and
`llvm.spv.resource.counterhandlefrombinding` intrinsics.
- Implementing the selection of these intrinsics in the SPIRV backend to
generate the correct `OpVariable` and `OpDecorate` instructions for
the counter buffer.
- Handling `IncrementCounter` and `DecrementCounter` via a new
`llvm.spv.resource.updatecounter` intrinsic, which is lowered to
`OpAtomicIAdd`.
- Adding a new test file to verify the implementation.
Contributes to https://github.com/llvm/llvm-project/issues/137032
---------
Co-authored-by: Marcos Maronas <marcos.maronas at intel.com>
Commit: 5d7f324614d7a5c0de89cfe8295a9b2b7ef5d073
https://github.com/llvm/llvm-project/commit/5d7f324614d7a5c0de89cfe8295a9b2b7ef5d073
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
Log Message:
-----------
[SLP]Enable Shl as a base opcode in copyables (#156766)
Enables Shl matching for the nodes, where copyable can be modelled as
shl %v, 0
Commit: 1c5186c315fdc6a070c302fe78f0e18122b9038f
https://github.com/llvm/llvm-project/commit/1c5186c315fdc6a070c302fe78f0e18122b9038f
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M openmp/tools/omptest/src/OmptTester.cpp
Log Message:
-----------
[OpenMP][omptest] Enable missing callback (#161650)
The registration of this callback handler was disabled for some reason.
Local testing did not bring up any issues when I enabled it.
Side effect is: Silences current warning about unused function.
Commit: 7f43b80d85758037b61eaec01ef8aac934307dc6
https://github.com/llvm/llvm-project/commit/7f43b80d85758037b61eaec01ef8aac934307dc6
Author: Martin Storsjö <martin at martin.st>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
[libcxx] [ci] Stop manually installing ninja in the Windows build jobs (#161907)
Ninja is officially included among the preinstalled tools on the Windows
runners now.
This should reduce the risk for stray failures here; sometimes,
attempting to install Ninja through Chocolatey have caused spurious
failures.
Commit: 9a111ff91c5dc7d59e1fc9d35f3e43e1c5699120
https://github.com/llvm/llvm-project/commit/9a111ff91c5dc7d59e1fc9d35f3e43e1c5699120
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M orc-rt/include/orc-rt/SPSWrapperFunction.h
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
Log Message:
-----------
[orc-rt] Enable transparent SPS conversion for ptrs via ExecutorAddr. (#162069)
Allows SPS wrapper function calls and handles to use pointer arguments.
These will be converted to ExecutorAddr for serialization /
deserialization.
Commit: f8baf07c7cc2c85c2273606ecf5b15bc23228102
https://github.com/llvm/llvm-project/commit/f8baf07c7cc2c85c2273606ecf5b15bc23228102
Author: Lang Hames <lhames at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
Log Message:
-----------
[orc-rt] Clean up SPSWrapperFunction unittest names.
Drop the redundant 'Test' prefix and rename transparent serialization tests to
clarify their purpose.
Commit: 5e07093917fa84b3ee9d09189a34a0c750f68cb7
https://github.com/llvm/llvm-project/commit/5e07093917fa84b3ee9d09189a34a0c750f68cb7
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
Log Message:
-----------
[mlir][spirv] Simplify unreachable default cases in type switch. NFC. (#162010)
Use `DefaultUnreachable` from
https://github.com/llvm/llvm-project/pull/161970.
Commit: fee71a3474ed09eb06a0d2c10edad376cab61ced
https://github.com/llvm/llvm-project/commit/fee71a3474ed09eb06a0d2c10edad376cab61ced
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/variables.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
Log Message:
-----------
[mlir][tosa] Apply 'Symbol' trait to `tosa.variable` (#153223)
Implement SymbolOpInterface on tosa.variable so that it's declaration is
automatically inserted into its parents SymbolTable.
Verifiers for tosa.variable_read/write can now look up the symbol and
guarantee it exists, and duplicate names are caught at creation time.
Previously this was completed by walking the graph which could be
inefficient.
Unfortunately, the Symbol trait expects to find a symbol name via a
hard-coded attribute name "sym_name". Therefore, "name" is renamed
to"sym_name" and a getName() wrapper is provided for backwards
compatibility.
This change also restricts tosa.variable declarations to ops that carry
a SymbolTable (e.g. modules), rather than allowing them to be placed
inside a func.func.
Note: EXT-VARIABLE is an experimental extension in the TOSA
specification, so is not subject to backwards compatibility guarantees.
Commit: 5296d017381f5bb4e3b29644767b98ce336698ce
https://github.com/llvm/llvm-project/commit/5296d017381f5bb4e3b29644767b98ce336698ce
Author: marius doerner <marius.doerner1 at icloud.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
Log Message:
-----------
[clang][bytecode] Assert on virtual func call from array elem (#158502)
Fixes #152893.
An assert was raised when a constexpr virtual function was called from
an constexpr array element with -fexperimental-new-constant-interpreter
set.
Commit: 8bab6c4e8c4f9a7b32ac5dd94436922c84705a86
https://github.com/llvm/llvm-project/commit/8bab6c4e8c4f9a7b32ac5dd94436922c84705a86
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
M mlir/lib/Dialect/Linalg/Transforms/NamedToElementwise.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Interfaces/DataLayoutInterfaces.cpp
M mlir/lib/Rewrite/ByteCode.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/TypeToLLVM.cpp
M mlir/lib/Tools/PDLL/AST/NodePrinter.cpp
M mlir/lib/Tools/PDLL/AST/Nodes.cpp
M mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
Log Message:
-----------
[mlir] Simplify unreachable type switch cases. NFC. (#162032)
Use `DefaultUnreachable` from
https://github.com/llvm/llvm-project/pull/161970.
Commit: 542cba893018e6c7faebbc5c19e5c10034c160ea
https://github.com/llvm/llvm-project/commit/542cba893018e6c7faebbc5c19e5c10034c160ea
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenOpenACCRecipe.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCRecipe.h
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
A clang/test/CIR/CodeGenOpenACC/firstprivate-clause-recipes.cpp
Log Message:
-----------
[OpenACC][CIR] Handle firstprivate bounds recipe lowering (#161873)
These work the same as the other two (private and reduction) except that
the expression for the 'init' is a copy instead of a default/value init,
and in a separate region. This patch gets all of that correct, and
ensures we generate these as expected.
There is a little extra work to make sure that the bounds-loop
generation does 2 separate array index operations, otherwise this is
very much like the reduction implementation.
Commit: c6a4e84a10ae8b163c9cae3f9a49eb8077a499ff
https://github.com/llvm/llvm-project/commit/c6a4e84a10ae8b163c9cae3f9a49eb8077a499ff
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
Log Message:
-----------
AMDGPU: Remove unnecessary reference (#162085)
Commit: f31bc666f42bb6bf0a3312a1d2ec230c390e8171
https://github.com/llvm/llvm-project/commit/f31bc666f42bb6bf0a3312a1d2ec230c390e8171
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/IR/Globals.cpp
A llvm/test/Bitcode/thinlto-alias-addrspacecast.ll
Log Message:
-----------
[IR] Handle addrspacecast in findBaseObject() (#162076)
Make findBaseObject() look through addrspacecast, so that
getAliaseeObject() works with an aliasee that uses and addrspacecast.
This fixes a crash during module summary index emission.
Fixes https://github.com/llvm/llvm-project/issues/161646.
Commit: f3a952311c9d7cfe56fefe14c3ece777f679b164
https://github.com/llvm/llvm-project/commit/f3a952311c9d7cfe56fefe14c3ece777f679b164
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/pr162009.ll
Log Message:
-----------
[AArch64] Return Invalid partial reduction cost for i128 accumulator. (#162066)
PR #158641 introduced an issue where i128 accumulator types resulted
in a valid cost, because for a <2 x i128> type the code that
checks for unsupported type legalization would see a type action
of 'TypeSplitVector' which is supported, even though the legalised
type of <1 x i128> would require further scalarization.
This fixes https://github.com/llvm/llvm-project/issues/162009
Commit: 48db3fd7026737d0fefe376e08ffee2ad996163a
https://github.com/llvm/llvm-project/commit/48db3fd7026737d0fefe376e08ffee2ad996163a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-propagation.mir
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
Log Message:
-----------
AMDGPU: Stop handling AGPR case in getCrossCopyRegClass (#161800)
This isn't what this is for. In the sense this hook is concerned with,
you can copy between AGPRs. This only changes some DAG scheduling
decisions; later passes are responsible for dealing with the bad
agpr-agpr handling.
Commit: 4efe170d858eb54432f520abb4e7f0086236748b
https://github.com/llvm/llvm-project/commit/4efe170d858eb54432f520abb4e7f0086236748b
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
Log Message:
-----------
[llvm-exegesis] Disable load store aliasing test
Test added by #159366
This is causing objdump to crash more often than not on our 2 stage
SVE bots, disabling it and I will investigate tomorrow.
Could be the changes in the PR, or a pre-existing codegen or
llvm-objdump problem.
Commit: 919470311fbdf366e25156ea20227ac5b76ad618
https://github.com/llvm/llvm-project/commit/919470311fbdf366e25156ea20227ac5b76ad618
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Misc/amdgcn.languageOptsOpenCL.cl
Log Message:
-----------
clang/AMDGPU: Report some missing OpenCL 2.0 feature macros (#160826)
Report __opencl_c_program_scope_global_variables and
__opencl_c_device_enqueue as supported. These 2.0 features are
supported but were missing from the extension map.
__opencl_c_atomic_scope_all_devices should also be reported, but
that seems to not just work by adding it to the map for some
reason.
The existing test for these macros was also broken, since it was
missing CL3.0 run lines, so add those.
Commit: 47d74ca157b4381c98ec92aaf4c5c6303e5da387
https://github.com/llvm/llvm-project/commit/47d74ca157b4381c98ec92aaf4c5c6303e5da387
Author: Usha Gupta <usha.gupta at arm.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/include/llvm/Transforms/IPO/FunctionAttrs.h
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/test/Other/new-pm-lto-defaults.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_libfunc_address_taken.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_libfunc_no_address_taken.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_lto.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_multi_scc_indirect_recursion.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_multi_scc_indirect_recursion1.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_multinode_refscc.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_self_recursive_callee.ll
Log Message:
-----------
[FuncAttrs][LTO] Relax norecurse attribute inference during postlink LTO (#158608)
This PR, which supersedes
https://github.com/llvm/llvm-project/pull/139943, extends the scenarios
where the 'norecurse' attribute can be inferred.
Currently, the 'norecurse' attribute is only inferred if all called
functions also have this attribute. This change introduces a new pass in
the LTO pipeline, run after Whole Program Devirtualization, to broaden
the inference criteria. The new pass inspects all functions in the
module and sets a flag if any functions are external or have their
addresses taken (while ignoring those already marked norecurse). This
flag is then used with the existing conditions to enable inference in
more cases.
This enhancement allows 'norecurse' to be applied in situations where a
function calls a recursive function, but is not part of the same
recursion chain.
For example, foo can now be marked 'norecurse' in the following
scenarios:
`foo -> callee1 -> callee2 -> callee2`
In this case, foo and callee1 can both be marked 'norecurse' because
they're not part of the callee2 recursion.
Similarly, foo can be marked 'norecurse' here:
`foo -> callee1 -> callee2 -> callee1`
Here, foo is not part of the callee1 -> callee2 -> callee1 recursion
chain, so it can be marked 'norecurse'.
Commit: 6b5fecf93bb330079fd91f5729ef0eedb288c3a9
https://github.com/llvm/llvm-project/commit/6b5fecf93bb330079fd91f5729ef0eedb288c3a9
Author: Oleksandr "Alex" Zinenko <git at ozinenko.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M mlir/lib/Dialect/Transform/IR/TransformDialect.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/test/Dialect/Transform/ops-invalid.mlir
Log Message:
-----------
[mlir] transform dialect: don't crash in verifiers (#161098)
Fix crashes in the verifier of `transform.with_named_sequence` attribute
attached to a symbol table operation caused by it constructing a call
graph inside the symbol table. The call graph construction assumes calls
and callables, such as functions or named sequences, have been verified,
but it is not yet the case when the attribute verifier on the (parent)
symbol table operation runs. Trigger such verification manually before
constructing the call graph. This adds redundancy in verification, but
there is currently no mechanism to change the order of verificaiton. In
performance-critical scenarios, verification can be disabled altogether.
Remove unnecessary verfificaton from `transform::IncludeOp::getEffects`.
It was introduced along with the op definition as the op used to inspect
the body of callee, which assumed the body existed, to identify handle
consumption behavior. This was later evolved to having explicit argument
attributes on the callee, which handles the absence of such attributes
gracefully without the need for verification, but the verification was
never removed. It would have been causing infinite recursion if kept in
place.
Fixes #159646.
Fixes #159734.
Fixes #159736.
Commit: 2b153a4c93dafc36d237d63ac64376ef3494285f
https://github.com/llvm/llvm-project/commit/2b153a4c93dafc36d237d63ac64376ef3494285f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/EnumsGen.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/TosaUtilsGen.cpp
Log Message:
-----------
[NFC][MLIR][TableGen] Use ArrayRef instead of const vector reference (#162016)
Commit: 95215a3f0d5931fb47a0655cfb6825d8a904ce1e
https://github.com/llvm/llvm-project/commit/95215a3f0d5931fb47a0655cfb6825d8a904ce1e
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/CppGenUtilities.cpp
M mlir/tools/mlir-tblgen/CppGenUtilities.h
M mlir/tools/mlir-tblgen/DialectGen.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
Log Message:
-----------
[NFC][MLIR][TableGen] Change `emitSummaryAndDescComments` to write to os directly (#162014)
Change `emitSummaryAndDescComments` to directly write to the output
stream, avoiding creating large intermediate strings.
Commit: 23e35bd43cf18ee479e6d5df08189db4591c403c
https://github.com/llvm/llvm-project/commit/23e35bd43cf18ee479e6d5df08189db4591c403c
Author: Cameron McInally <cameron.mcinally at nyu.edu>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M flang/docs/FortranLLVMTestSuite.md
Log Message:
-----------
[Flang][Tests] Add GPL notice to GFortran test suite documentation. (#161912)
Add a GPL notice to the GFortran test suite documentation and redirect
to the LICENSE file distributed with the test suite.
Co-authored-by: Cameron McInally <cmcinally at nvidia.com>
Commit: 45c41247f82e5691425542de829d568cdc2fb580
https://github.com/llvm/llvm-project/commit/45c41247f82e5691425542de829d568cdc2fb580
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__ranges/iota_view.h
M libcxx/include/ranges
M libcxx/include/version
M libcxx/modules/std/ranges.inc
M libcxx/test/std/language.support/support.limits/support.limits.general/ranges.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/library/description/conventions/customization.point.object/cpo.compile.pass.cpp
A libcxx/test/std/ranges/range.factories/range.iota.view/indices.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++][ranges] P3060R3: Add `std::views::indices(n)` (#146823)
Implements [P3060R3](https://wg21.link/P3060R3)
Closes #148175
# References
- https://github.com/cplusplus/draft/issues/7966
- https://github.com/cplusplus/draft/pull/8006
- https://wg21.link/customization.point.object
- https://wg21.link/range.iota.overview
- https://wg21.link/ranges.syn
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: 35c57a778bbd25d4df92b4b0e172b2f2aa3bf4f3
https://github.com/llvm/llvm-project/commit/35c57a778bbd25d4df92b4b0e172b2f2aa3bf4f3
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/BasicFeatures/AggregateSplatCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/StructElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
M clang/test/SemaHLSL/Language/AggregateSplatCast-errors.hlsl
M clang/test/SemaHLSL/Language/ElementwiseCast-errors.hlsl
Log Message:
-----------
[HLSL] Add support for elementwise and aggregate splat casting struct types with bitfields (#161263)
Adds support for elementwise and aggregate splat casting struct types
with bitfields. Replacing existing Flattening function which used to
produce a list of GEPs representing a flattened object with one that
produces a list of LValues representing a flattened object. The LValues
can be used by EmitStoreThroughLValue and EmitLoadOfLValue, ensuring
bitfields are properly loaded and stored. This also simplifies the code
in the elementwise and aggregate splat casting functions.
Closes #125986
Commit: a663119455df2720e0c2b8b11fdb978b9d9dddb3
https://github.com/llvm/llvm-project/commit/a663119455df2720e0c2b8b11fdb978b9d9dddb3
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Fix verifier failures due to 93073af (#162097)
Follow up on 93073af ([LV] Move 3 functions into VPlanTransforms (NFC))
to not call runPass on the moved functions, as that results in verifier
failures.
Ref: https://lab.llvm.org/buildbot/#/builders/187/builds/12178
Commit: 6620e53511341703f3a2c54e4e9f1252d7d8dd1f
https://github.com/llvm/llvm-project/commit/6620e53511341703f3a2c54e4e9f1252d7d8dd1f
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/test/CIR/CodeGen/new.cpp
Log Message:
-----------
[CIR][NFC] Update Complex CXX new test to use regex (#162024)
Update Complex CXX new test to use regex for variable names
Commit: 1cc9a8c1272f428edcd4caf871cb66f973f4c13e
https://github.com/llvm/llvm-project/commit/1cc9a8c1272f428edcd4caf871cb66f973f4c13e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
Log Message:
-----------
AMDGPU: Stop using the wavemask register class for SCC cross class copies (#161801)
SCC should be copied to a 32-bit SGPR. Using a wave mask doesn't make
sense.
Commit: e9f3be63d3928b24f3667d8aaadfbee9d325015f
https://github.com/llvm/llvm-project/commit/e9f3be63d3928b24f3667d8aaadfbee9d325015f
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
Log Message:
-----------
[NFC][PowerPC] Cleanup isImm and getImmEncoding functions (#161567)
Refactor and replace explicit Imm `getImm*Encodng() | isU*Imm() |
isS*Imm()` functions to a generic one that takes a template.
This is in prep for followup batch to implement `paddis` which takes a
pcrel Imm == 32bits. Doing this
refactor so we don't have to copy and paste the same set of functions
again with only the bit length changes.
Commit: 9e8dda103425d355e06aca7e069050381ae84ceb
https://github.com/llvm/llvm-project/commit/9e8dda103425d355e06aca7e069050381ae84ceb
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/TargetParser/TargetParser.cpp
Log Message:
-----------
[NFC] Change spelling of cluster feature to "clusters" (#162103)
Commit: 44b2673544bf32ae498cfa22193090f9fd7dae24
https://github.com/llvm/llvm-project/commit/44b2673544bf32ae498cfa22193090f9fd7dae24
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/test/CIR/CodeGen/global-init.cpp
Log Message:
-----------
[CIR] Implement initial LoweringPrepare support for global ctors (#161452)
This adds the initial support for lowering the 'ctor' region of
cir.global operations to an init function which is called from a
TU-specific static initialization function.
This does not yet add an attribute to hold a list of global
initializers. That will be added in a future change.
Commit: 08e95405752e6d3475afdebe3bd5f2ff2ff17712
https://github.com/llvm/llvm-project/commit/08e95405752e6d3475afdebe3bd5f2ff2ff17712
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
A llvm/include/llvm/CAS/OnDiskDataAllocator.h
M llvm/lib/CAS/CMakeLists.txt
A llvm/lib/CAS/OnDiskDataAllocator.cpp
M llvm/unittests/CAS/CMakeLists.txt
A llvm/unittests/CAS/OnDiskDataAllocatorTest.cpp
Log Message:
-----------
[CAS] Add OnDiskDataAllocator (#161264)
Add OnDiskDataAllocator, which is the data pool implementation inside a
OnDiskCAS that stores data in a single file. It is a based on
MappedFileRegionArena and wrapped inside a CAS database file.
Commit: 27c207ef4c7ec11757c26ae11e3aa45cdb4dc90f
https://github.com/llvm/llvm-project/commit/27c207ef4c7ec11757c26ae11e3aa45cdb4dc90f
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
Log Message:
-----------
[NFC][SPIRV] GetElementPtrInst does not need a call to isInstructionTriviallyDead after replaceUsesofWith (#162045)
A getelementptr is always removable after replacing all its uses, since
it doesn't have side effects and always returns.
Commit: ebfb16a28512917b6346fd4e2b8b9b937c2df485
https://github.com/llvm/llvm-project/commit/ebfb16a28512917b6346fd4e2b8b9b937c2df485
Author: Nico Weber <thakis at chromium.org>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
R llvm/include/llvm/CAS/OnDiskDataAllocator.h
M llvm/lib/CAS/CMakeLists.txt
R llvm/lib/CAS/OnDiskDataAllocator.cpp
M llvm/unittests/CAS/CMakeLists.txt
R llvm/unittests/CAS/OnDiskDataAllocatorTest.cpp
Log Message:
-----------
Revert "[CAS] Add OnDiskDataAllocator (#161264)"
This reverts commit 08e95405752e6d3475afdebe3bd5f2ff2ff17712.
Doesn't build on some bots,
see comments on https://github.com/llvm/llvm-project/pull/161264
Commit: 134407d5f9d81d454c37400d163e2f1163ba0b8b
https://github.com/llvm/llvm-project/commit/134407d5f9d81d454c37400d163e2f1163ba0b8b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
Log Message:
-----------
AMDGPU: Add gfx1250 to sram-ecc elf header flags test (#162107)
Commit: 488e667707810cc3da167a56c83c3a928000e2c7
https://github.com/llvm/llvm-project/commit/488e667707810cc3da167a56c83c3a928000e2c7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-10-06 (Mon, 06 Oct 2025)
Changed paths:
M .github/new-prs-labeler.yml
M .github/workflows/libcxx-build-and-test.yaml
A .github/workflows/llvm-abi-tests.yml
R .github/workflows/llvm-tests.yml
M bolt/utils/dot2html/d3-graphviz-template.html
M clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SignedCharMisuseCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/signed-char-misuse.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/signed-char-misuse-with-option.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/BuiltinsNVPTX.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.h
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Sema/SemaConcept.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.h
A clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCRecipe.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCRecipe.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypeCache.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/CodeGen/TargetInfo.h
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGExprAgg.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateDeductionGuide.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Tooling/DependencyScanning/CMakeLists.txt
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.h
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/test/AST/ByteCode/cxx20.cpp
M clang/test/AST/ast-print-record-decl.c
A clang/test/CIR/CodeGen/address-space.c
M clang/test/CIR/CodeGen/complex.cpp
A clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CIR/CodeGen/global-init.cpp
M clang/test/CIR/CodeGen/new.cpp
A clang/test/CIR/CodeGen/paren-init-list.cpp
M clang/test/CIR/CodeGen/struct.cpp
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
A clang/test/CIR/CodeGenOpenACC/firstprivate-clause-recipes.cpp
M clang/test/CIR/IR/func.cir
A clang/test/CIR/IR/invalid-addrspace.cir
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/builtins-nvptx.c
M clang/test/CodeGenHLSL/BasicFeatures/AggregateSplatCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/ArrayElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/StructElementwiseCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/VectorElementwiseCast.hlsl
R clang/test/CodeGenHLSL/resources/AppendStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/resources/ConsumeStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/resources/RWStructuredBuffer-elementtype.hlsl
R clang/test/CodeGenHLSL/resources/StructuredBuffer-elementtype.hlsl
A clang/test/CodeGenHLSL/resources/StructuredBuffers-elementtype.hlsl
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/Driver/hip-options.hip
M clang/test/Driver/linker-wrapper.c
M clang/test/Headers/arm-acle-header.c
M clang/test/Headers/arm-cde-header.c
M clang/test/Headers/arm-cmse-header.c
M clang/test/Headers/arm-fp16-header.c
M clang/test/Headers/arm-neon-header.c
A clang/test/Headers/system_reserved_names.h
M clang/test/Headers/x86-intrinsics-headers-clean.cpp
M clang/test/Headers/x86-intrinsics-headers.c
M clang/test/Misc/amdgcn.languageOptsOpenCL.cl
A clang/test/Modules/pr133057.cpp
M clang/test/Parser/cxx0x-lambda-expressions.cpp
M clang/test/SemaCUDA/vararg.cu
M clang/test/SemaCXX/builtin-assume-aligned.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
M clang/test/SemaCXX/diagnose_if.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
M clang/test/SemaHLSL/Language/AggregateSplatCast-errors.hlsl
M clang/test/SemaHLSL/Language/ElementwiseCast-errors.hlsl
M clang/test/SemaTemplate/alias-template-deprecated.cpp
M clang/test/SemaTemplate/alias-templates.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
M clang/unittests/Format/FormatTestObjC.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/test/asan/TestCases/wcscat.cpp
M compiler-rt/test/asan/TestCases/wcscpy.cpp
M compiler-rt/test/asan/TestCases/wcsncat.cpp
M compiler-rt/test/asan/TestCases/wcsncpy.cpp
M cross-project-tests/debuginfo-tests/dexter-tests/lit.local.cfg
M cross-project-tests/debuginfo-tests/dexter/feature_tests/lit.local.cfg
M flang/docs/FortranLLVMTestSuite.md
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Parser/message.h
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Optimizer/Transforms/CUFComputeSharedMemoryOffsetsAndSize.cpp
M flang/lib/Parser/message.cpp
M flang/test/Fir/CUDA/cuda-shared-offset.mlir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
A flang/test/Lower/OpenMP/map-neg-alloca-derived-type-array.f90
M flang/test/Semantics/associated.f90
M flang/test/Semantics/intrinsics03.f90
M flang/test/Semantics/intrinsics04.f90
A flang/test/Semantics/type-parameter-constant.f90
M libc/config/linux/aarch64/headers.txt
M libc/config/linux/riscv/headers.txt
M libc/config/linux/x86_64/headers.txt
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/netinet-in-macros.h
A libc/include/netinet/in.h.def
A libc/include/netinet/in.yaml
M libc/shared/math.h
A libc/shared/math/exp2.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/common_constants.h
A libc/src/__support/math/exp2.h
M libc/src/math/generic/CMakeLists.txt
R libc/src/math/generic/common_constants.cpp
R libc/src/math/generic/common_constants.h
M libc/src/math/generic/exp2.cpp
M libc/src/math/generic/expm1.cpp
M libc/src/math/generic/expm1f.cpp
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log10f.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log1pf.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/log2f.cpp
M libc/src/math/generic/log_range_reduction.h
M libc/src/math/generic/logf.cpp
M libc/src/math/generic/pow.cpp
M libc/src/math/generic/powf.cpp
M libc/test/include/CMakeLists.txt
A libc/test/include/netinet_in_test.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M libclc/CMakeLists.txt
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/__ranges/iota_view.h
M libcxx/include/ranges
M libcxx/include/version
M libcxx/modules/std/ranges.inc
M libcxx/test/std/experimental/simd/simd.class/simd_unary.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/ranges.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/library/description/conventions/customization.point.object/cpo.compile.pass.cpp
A libcxx/test/std/ranges/range.factories/range.iota.view/indices.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M lldb/include/lldb/Host/JSONTransport.h
M lldb/include/lldb/Protocol/MCP/MCPError.h
M lldb/include/lldb/Protocol/MCP/Protocol.h
M lldb/include/lldb/Protocol/MCP/Server.h
M lldb/include/lldb/Protocol/MCP/Transport.h
M lldb/include/lldb/Target/Language.h
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/source/Host/common/JSONTransport.cpp
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp
M lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h
M lldb/source/Protocol/MCP/MCPError.cpp
M lldb/source/Protocol/MCP/Server.cpp
M lldb/source/Target/Language.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Protocol/ProtocolBase.h
M lldb/tools/lldb-dap/Transport.h
M lldb/unittests/DAP/DAPTest.cpp
M lldb/unittests/DAP/Handler/DisconnectTest.cpp
M lldb/unittests/DAP/TestBase.cpp
M lldb/unittests/DAP/TestBase.h
M lldb/unittests/Host/JSONTransportTest.cpp
M lldb/unittests/Host/posix/HostTest.cpp
M lldb/unittests/Protocol/ProtocolMCPServerTest.cpp
M lldb/unittests/Protocol/ProtocolMCPTest.cpp
M lldb/unittests/Target/CMakeLists.txt
A lldb/unittests/Target/LanguageTest.cpp
M lldb/unittests/TestingSupport/Host/JSONTransportTestUtilities.h
M llvm/docs/GettingStarted.rst
M llvm/docs/GitHub.rst
M llvm/docs/HowToReleaseLLVM.rst
M llvm/docs/LangRef.rst
M llvm/docs/PDB/HashTable.rst
M llvm/docs/ProgrammersManual.rst
M llvm/include/llvm/ADT/BitmaskEnum.h
M llvm/include/llvm/ADT/PointerUnion.h
M llvm/include/llvm/ADT/StringSwitch.h
M llvm/include/llvm/ADT/TypeSwitch.h
M llvm/include/llvm/ADT/bit.h
M llvm/include/llvm/Analysis/MemoryProfileInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/ValueMap.h
M llvm/include/llvm/MC/MCAsmInfo.h
M llvm/include/llvm/MC/MCAsmInfoELF.h
M llvm/include/llvm/MC/TargetRegistry.h
A llvm/include/llvm/Support/Jobserver.h
M llvm/include/llvm/Support/ScopedPrinter.h
M llvm/include/llvm/Support/ThreadPool.h
M llvm/include/llvm/Support/Threading.h
A llvm/include/llvm/TableGen/CodeGenHelpers.h
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/TargetSchedule.td
M llvm/include/llvm/Transforms/IPO/FunctionAttrs.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/MC/MCAsmInfoELF.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/CMakeLists.txt
A llvm/lib/Support/Jobserver.cpp
M llvm/lib/Support/Parallel.cpp
M llvm/lib/Support/ThreadPool.cpp
M llvm/lib/Support/Threading.cpp
A llvm/lib/Support/Unix/Jobserver.inc
A llvm/lib/Support/Windows/Jobserver.inc
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AArch64/SMEInstrFormats.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/ARM/ARMInstrCDE.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTX.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
M llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/RISCVGISel.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizeImplicitBinding.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/IPO/FunctionAttrs.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
A llvm/test/Bitcode/thinlto-alias-addrspacecast.ll
M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-sextinreg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-vashr-vlshr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-vector-shift.mir
M llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/arm64-vadd.ll
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/extract-vector-elt.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/fpclamptosat.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
M llvm/test/CodeGen/AArch64/machine-licm-sub-loop.ll
M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
M llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
M llvm/test/CodeGen/AArch64/peephole-and-tst.ll
M llvm/test/CodeGen/AArch64/reserveXreg-for-regalloc.ll
M llvm/test/CodeGen/AArch64/select_cc.ll
M llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
R llvm/test/CodeGen/AArch64/spill-fill-zpr-predicates.mir
M llvm/test/CodeGen/AArch64/ssve-stack-hazard-remarks.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/trampoline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-propagation.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.ll
A llvm/test/CodeGen/AMDGPU/pal-metadata-3.6-dvgpr.ll
M llvm/test/CodeGen/AMDGPU/pal-metadata-3.6.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sgpr-copy.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
M llvm/test/CodeGen/AMDGPU/true16-fold.mir
M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
M llvm/test/CodeGen/ARM/combine-movc-sub.ll
M llvm/test/CodeGen/ARM/extract-bits.ll
M llvm/test/CodeGen/ARM/extract-lowbits.ll
M llvm/test/CodeGen/ARM/fpclamptosat.ll
M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
M llvm/test/CodeGen/ARM/llround-conv.ll
M llvm/test/CodeGen/ARM/lround-conv.ll
A llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
A llvm/test/CodeGen/NVPTX/convert-sm103a.ll
M llvm/test/CodeGen/NVPTX/wmma-ptx87-sm120a.py
M llvm/test/CodeGen/NVPTX/wmma.py
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/pr69586.ll
M llvm/test/CodeGen/RISCV/rv64-trampoline.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/test_counters.ll
A llvm/test/CodeGen/SPIRV/pointers/ptrcast-bitcast.ll
M llvm/test/CodeGen/SystemZ/llvm.sincos.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination.ll
M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
M llvm/test/CodeGen/Thumb2/mve-phireg.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
M llvm/test/CodeGen/Thumb2/mve-qrintrsplat.ll
M llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
M llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
A llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir
A llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec256.mir
A llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier-vec512.mir
A llvm/test/CodeGen/X86/GlobalISel/select-constant-fold-barrier.mir
A llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec256.mir
A llvm/test/CodeGen/X86/GlobalISel/select-freeze-vec512.mir
A llvm/test/CodeGen/X86/GlobalISel/select-freeze.mir
M llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
M llvm/test/CodeGen/X86/delete-dead-instrs-with-live-uses.mir
M llvm/test/CodeGen/X86/fpclamptosat.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/inalloca-invoke.ll
M llvm/test/CodeGen/X86/licm-regpressure.ll
M llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
M llvm/test/Other/new-pm-lto-defaults.ll
A llvm/test/TableGen/ResolveSchedClass.td
M llvm/test/ThinLTO/X86/memprof-basic.ll
A llvm/test/ThinLTO/X86/memprof-dups.ll
M llvm/test/ThinLTO/X86/memprof_imported_internal.ll
M llvm/test/Transforms/Coroutines/coro-catchswitch-cleanuppad.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_libfunc_address_taken.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_libfunc_no_address_taken.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_lto.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_multi_scc_indirect_recursion.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_multi_scc_indirect_recursion1.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_multinode_refscc.ll
A llvm/test/Transforms/FunctionAttrs/norecurse_self_recursive_callee.ll
M llvm/test/Transforms/InstCombine/clamp-to-minmax.ll
M llvm/test/Transforms/InstCombine/select-and-cmp.ll
M llvm/test/Transforms/InstCombine/select-gep.ll
M llvm/test/Transforms/InstCombine/select-or-cmp.ll
M llvm/test/Transforms/InstSimplify/domcondition.ll
A llvm/test/Transforms/LoopVectorize/AArch64/pr162009.ll
A llvm/test/Transforms/NewGVN/pr159918.ll
M llvm/test/Transforms/PGOProfile/memprof.ll
M llvm/test/Transforms/SCCP/relax-range-checks.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/X86/ext-used-scalar-different-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SLPVectorizer/bool-logical-op-reduction-with-poison.ll
M llvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
M llvm/test/Transforms/SimplifyCFG/rangereduce.ll
M llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
M llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
M llvm/test/Transforms/SimplifyCFG/switch_create.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
A llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/Generic/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avx512vbmi2vl.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vbmi2.s
M llvm/test/tools/llvm-mca/X86/Znver4/resources-avx512vbmi2vl.s
M llvm/tools/llvm-c-test/debuginfo.c
M llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
M llvm/tools/llvm-mc/llvm-mc.cpp
M llvm/unittests/ADT/BitTest.cpp
M llvm/unittests/ADT/StringSwitchTest.cpp
M llvm/unittests/ADT/TypeSwitchTest.cpp
M llvm/unittests/Analysis/FunctionPropertiesAnalysisTest.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
M llvm/unittests/Analysis/MemoryProfileInfoTest.cpp
M llvm/unittests/Support/CMakeLists.txt
A llvm/unittests/Support/JobserverTest.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M llvm/utils/TableGen/Basic/TargetFeaturesEmitter.cpp
M llvm/utils/TableGen/CompressInstEmitter.cpp
M llvm/utils/TableGen/SubtargetEmitter.cpp
M llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni
M llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn
M llvm/utils/profcheck-xfail.txt
M mlir/docs/Tutorials/CreatingADialect.md
M mlir/include/mlir-c/Rewrite.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaUtilOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/TableGen/CodeGenHelpers.h
M mlir/include/mlir/TableGen/Dialect.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/Rewrite.cpp
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/lib/Conversion/PDLToPDLInterp/PredicateTree.cpp
M mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
M mlir/lib/Conversion/VectorToAMX/VectorToAMX.cpp
M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Conversion/XeVMToLLVM/XeVMToLLVM.cpp
M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferResultsToOutParams.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
M mlir/lib/Dialect/Linalg/Transforms/NamedToElementwise.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Transform/IR/TransformDialect.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/Interfaces/DataLayoutInterfaces.cpp
M mlir/lib/Rewrite/ByteCode.cpp
M mlir/lib/TableGen/CodeGenHelpers.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/TypeToLLVM.cpp
M mlir/lib/Tools/PDLL/AST/NodePrinter.cpp
M mlir/lib/Tools/PDLL/AST/Nodes.cpp
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Tosa/invalid_extension.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Tosa/variables.mlir
M mlir/test/Dialect/Tosa/verifier.mlir
M mlir/test/Dialect/Transform/ops-invalid.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
A mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
M mlir/test/Target/LLVMIR/nvvmir.mlir
R mlir/test/Transforms/buffer-results-to-out-params-elim.mlir
A mlir/test/Transforms/buffer-results-to-out-params-hosit-dynamic-allocs.mlir
A mlir/test/Transforms/buffer-results-to-out-params-hosit-static-allocs.mlir
M mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp
M mlir/test/python/integration/dialects/pdl.py
M mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp
M mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
M mlir/tools/mlir-tblgen/CppGenUtilities.cpp
M mlir/tools/mlir-tblgen/CppGenUtilities.h
M mlir/tools/mlir-tblgen/DialectGen.cpp
M mlir/tools/mlir-tblgen/EnumsGen.cpp
M mlir/tools/mlir-tblgen/OmpOpGen.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpInterfacesGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M mlir/tools/mlir-tblgen/TosaUtilsGen.cpp
A openmp/runtime/test/transform/tile/do.F90
A openmp/runtime/test/transform/tile/do_2d.f90
A openmp/runtime/test/transform/tile/do_2d_varsizes.f90
R openmp/runtime/test/transform/tile/intfor.f90
R openmp/runtime/test/transform/tile/intfor_2d.f90
R openmp/runtime/test/transform/tile/intfor_2d_varsizes.F90
A openmp/runtime/test/transform/unroll/heuristic_do.f90
R openmp/runtime/test/transform/unroll/heuristic_intdo.f90
M openmp/tools/omptest/src/OmptTester.cpp
M orc-rt/include/orc-rt/SPSWrapperFunction.h
M orc-rt/include/orc-rt/WrapperFunction.h
M orc-rt/unittests/CMakeLists.txt
R orc-rt/unittests/CommonTestUtils.cpp
M orc-rt/unittests/CommonTestUtils.h
M orc-rt/unittests/SPSWrapperFunctionTest.cpp
M orc-rt/unittests/bind-test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
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Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/af13804025b4...488e66770781
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