[all-commits] [llvm/llvm-project] 874428: [RISCV][GISel] Use relaxed_load/store in GISel ato...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 874428708f3bcf2fc8402b2aa0ca720c1b6cd3a6
      https://github.com/llvm/llvm-project/commit/874428708f3bcf2fc8402b2aa0ca720c1b6cd3a6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-10-02 (Thu, 02 Oct 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVGISel.td

  Log Message:
  -----------
  [RISCV][GISel] Use relaxed_load/store in GISel atomic patterns. NFC (#161712)

We have additional patterns for GISel because we need to make s16 and
s32 legal for load/store. GISel does not distinquish integer and FP
scalar types in LLT. We only know whether the load should be integer or
FP after register bank selection.

These patterns should have been updated to use relaxed_load/store when
the patterns in RISCVInstrInfoA.td were updated. Without this we will
miscompile loads/stores with strong memory ordering when Zalasr is
enabled.

This patch just fixes the miscompile, Zalasr will now cause a GISel
abort in some cases. A follow up patch will add additional GISel
patterns for Zalasr.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications