[all-commits] [llvm/llvm-project] c4e1bc: Greedy: Move physreg check when trying to recolor ...
Michael Kruse via All-commits
all-commits at lists.llvm.org
Thu Oct 2 09:53:04 PDT 2025
Branch: refs/heads/users/meinersbur/mlir_tile
Home: https://github.com/llvm/llvm-project
Commit: c4e1bca407f4cca7644937c117890fad157fec4b
https://github.com/llvm/llvm-project/commit/c4e1bca407f4cca7644937c117890fad157fec4b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
Log Message:
-----------
Greedy: Move physreg check when trying to recolor vregs (NFC) (#160484)
Instead of checking if the recoloring candidate is a virtual register,
avoid adding it to the candidates in the first place.
Commit: 9f5abd38dd1782a6fd3b8ed1c2f76aa62dc850b1
https://github.com/llvm/llvm-project/commit/9f5abd38dd1782a6fd3b8ed1c2f76aa62dc850b1
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
M llvm/test/CodeGen/AArch64/framelayout-sve.mir
M llvm/test/CodeGen/AArch64/spillfill-sve.mir
M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
Log Message:
-----------
[Codegen] Add a separate stack ID for scalable predicates (#142390)
This splits out "ScalablePredicateVector" from the "ScalableVector"
StackID this is primarily to allow easy differentiation between vectors
and predicates (without inspecting instructions).
This new stack ID is not used in many places yet, but will be used in a
later patch to mark stack slots that are known to contain predicates.
Co-authored-by: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Commit: 047f8c8ee08e6efc51c552b910a6fbec2baca189
https://github.com/llvm/llvm-project/commit/047f8c8ee08e6efc51c552b910a6fbec2baca189
Author: Corentin Jabot <corentinjabot at gmail.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/docs/InternalsManual.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTConcept.h
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaConcept.h
M clang/include/clang/Sema/Template.h
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/AST/ast-dump-concepts.cpp
M clang/test/AST/ast-dump-ctad-alias.cpp
M clang/test/CXX/drs/cwg25xx.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.id/p3.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/compound-requirement.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/nested-requirement.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/simple-requirement.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/type-requirement.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.atomic/constrant-satisfaction-conversions.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.normal/p1.cpp
M clang/test/CXX/temp/temp.param/p10-2a.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaCXX/cxx2c-template-template-param.cpp
M clang/test/SemaCXX/invalid-requirement-requires-expr.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaHLSL/BuiltIns/Buffers.hlsl
M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
M clang/test/SemaTemplate/concepts-recovery-expr.cpp
M clang/test/SemaTemplate/concepts-recursive-inst.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
M clang/test/SemaTemplate/instantiate-abbreviated-template.cpp
M clang/test/SemaTemplate/instantiate-expanded-type-constraint.cpp
M clang/test/SemaTemplate/instantiate-requires-expr.cpp
M clang/test/SemaTemplate/instantiate-template-argument.cpp
M clang/test/SemaTemplate/pr52970.cpp
M libcxx/test/libcxx/algorithms/cpp17_iterator_concepts.verify.cpp
Log Message:
-----------
Revert "[Clang] Normalize constraints before checking for satisfaction" (#161669)
Reverts llvm/llvm-project#141776
CI failures
https://lab.llvm.org/buildbot/#/builders/202/builds/3591
https://lab.llvm.org/buildbot/#/builders/55/builds/18066
https://lab.llvm.org/buildbot/#/builders/85/builds/14103
Commit: 706b79002e21b571888db7f275bf5ed00e7cce41
https://github.com/llvm/llvm-project/commit/706b79002e21b571888db7f275bf5ed00e7cce41
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
Log Message:
-----------
Greedy: Merge VirtRegMap queries into one use (NFC) (#160485)
Commit: b147019f8b11cd491f331bd707f764786792665e
https://github.com/llvm/llvm-project/commit/b147019f8b11cd491f331bd707f764786792665e
Author: Alejandro Álvarez Ayllón <alejandro.alvarez at sonarsource.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseDecl.cpp
A clang/test/Parser/recovery-after-expected-unqualified-id.cpp
Log Message:
-----------
[clang] Preserve `externs` following broken declarations (#161641)
Treat them as namespaces: if they are at the beginning of the line, they
are likely a good recovery point.
For instance, in
```cpp
1.3.0
extern "C" {
extern int foo();
extern "C++" {
namespace bar {
void baz();
};
}
}
namespace {}
```
Everything until `namespace`... is gone from the AST. Headers (like
libc's C++ `math.h`) can be included from an `extern "C"` context, and
they do an `extern "C++"` back again before including C++ headers (like
`__type_traits`).
However, a malformed declaration just before the include (as the orphan
`1.3.0` in the example) causes everything from these standard headers to
go missing. This patch updates the heuristic to try to recover from the
first `extern` keyword seen, pretty much as it is done for `namespace`.
CPP-4478
Commit: b92ff6b2099fa5103a0350028c6752ad953b9b8d
https://github.com/llvm/llvm-project/commit/b92ff6b2099fa5103a0350028c6752ad953b9b8d
Author: ravil-mobile <ravil.aviva.com at gmail.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[ROCDL] Added `rocdl.cvt.scale.pk8` ops (#161411)
This patch introduces some missing FP conversion instructions in the
ROCDL dialect
Specifically:
- Downscaling 8x packed F16, Bf16, Fp32 values to Fp8, Bf8, Fp4
Tests:
- Added lit-tests to check MLIR -> LLVM lowering
Commit: f98735f1264c9214a2efa2b05d48871e44cfd245
https://github.com/llvm/llvm-project/commit/f98735f1264c9214a2efa2b05d48871e44cfd245
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
Log Message:
-----------
Greedy: Use initializer list for recoloring candidates (NFC) (#160486)
Commit: 11b0cf8fbeaf8b2384f3ab4d7f6fe97bc7d3db63
https://github.com/llvm/llvm-project/commit/11b0cf8fbeaf8b2384f3ab4d7f6fe97bc7d3db63
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/test/CodeGen/X86/shift-i128.ll
Log Message:
-----------
Greedy: Take hints from copy to physical subreg (#160467)
Previously this took hints from subregister extract of physreg,
like %vreg.sub = COPY $physreg
This now also handles the rarer case:
$physreg_sub = COPY %vreg
Also make an accidental bug here before explicit; this was
only using the superregister as a hint if it was already
in the copy, and not if using the existing assignment. There are
a handful of regressions in that case, so leave that extension
for a future change.
Commit: daa4e57ccf38ff6ac22243e98a035c87b9f9f3ae
https://github.com/llvm/llvm-project/commit/daa4e57ccf38ff6ac22243e98a035c87b9f9f3ae
Author: Ikhlas Ajbar <iajbar at quicinc.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
A llvm/test/CodeGen/Hexagon/unaligned-vec-store.ll
Log Message:
-----------
[Hexagon] Add opcode V6_vS32Ub_npred_ai for offset validity check (#161618)
Check for a valid offset for unaligned vector store V6_vS32Ub_npred_ai.
isValidOffset() is updated to evaluate offset of this instruction.
Fixes #160647
Commit: c242aff2452fb662a7ea23954abe654b51182b8e
https://github.com/llvm/llvm-project/commit/c242aff2452fb662a7ea23954abe654b51182b8e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M flang/include/flang/Lower/OpenACC.h
M flang/include/flang/Lower/SymbolMap.h
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/SymbolMap.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/OpenACC/acc-host-data-cuda-device.f90
Log Message:
-----------
[flang][cuda][openacc] Create new symbol in host_data region for CUDA Fortran interop (#161613)
Commit: 197e77b33d344c162b8c87de8aa7ddd942f50874
https://github.com/llvm/llvm-project/commit/197e77b33d344c162b8c87de8aa7ddd942f50874
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/sbb.ll
Log Message:
-----------
[X86] Create special case for (a-b) - (a<b) -> sbb a, b (#161388)
Commit: a3594cd6442ee988c18249d96b8331f0a5331df7
https://github.com/llvm/llvm-project/commit/a3594cd6442ee988c18249d96b8331f0a5331df7
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M mlir/include/mlir/Bindings/Python/NanobindAdaptors.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/Bindings/Python/MainModule.cpp
Log Message:
-----------
[MLIR][Python] fixup Context and Location stubs and NanobindAdaptors (#161433)
add correct names for `NB_TYPE_CASTER(..., name)` so users of
`NanobindAdaptors.h` can generate the correct hints. Also fix a few
straggler stubs.
Commit: 32d03f3991bb03e976a25a3fa311f9a4e172dc5e
https://github.com/llvm/llvm-project/commit/32d03f3991bb03e976a25a3fa311f9a4e172dc5e
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
Log Message:
-----------
[Clang][Sema] Fix crash in CheckUsingDeclQualifier due to diagnostic missing an argument (#161277)
Crash report came in and it was pretty obvious the diagnostic line was
just missing an argument. I supplied the argument and added a test.
Fixes: https://github.com/llvm/llvm-project/issues/161072
Commit: 6632b2f377674864bd4bc05278bf90805d30665a
https://github.com/llvm/llvm-project/commit/6632b2f377674864bd4bc05278bf90805d30665a
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/test/DebugInfo/AArch64/asan-stack-vars.mir
M llvm/test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir
Log Message:
-----------
[AArch64] Prepare for split ZPR and PPR area allocation (NFCI) (#142391)
This patch attempts to refactor AArch64FrameLowering to allow the size
of the ZPR and PPR areas to be calculated separately. This will be used
by a subsequent patch to support allocating ZPRs and PPRs to separate
areas. This patch should be an NFC and is split out to make later
functional changes easier to spot.
Co-authored-by: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Commit: f646d766de4e7978feeced765b414dc7f905c5f1
https://github.com/llvm/llvm-project/commit/f646d766de4e7978feeced765b414dc7f905c5f1
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/reduction-order.ll
Log Message:
-----------
[LV] Extend test coverage for tail-folding with recurrences.
Add additional test coverage for tail-folding loops with first-order
recurrences and users outside the loop. Test a combination of
vectorization factors and interleave counts.
Also update check lines in reduction-order.ll and adjust naming for
clarity.
This adds extra test coverage for
https://github.com/llvm/llvm-project/pull/149042.
Commit: e3e0f69fca744f357d45c04d06038f6b566a0b90
https://github.com/llvm/llvm-project/commit/e3e0f69fca744f357d45c04d06038f6b566a0b90
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
Log Message:
-----------
[NFC][clang-sycl-linker] Avoid ambiguous call to CallingConv (#161682)
both llvm and clang namespace have CallingConv.
Add namespace prefix to avoid ambiguous call .
Commit: 235cd75c1429ad51cc3ad9728ccd8ffdc10742e3
https://github.com/llvm/llvm-project/commit/235cd75c1429ad51cc3ad9728ccd8ffdc10742e3
Author: LU-JOHN <John.Lu at amd.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
Log Message:
-----------
[AMDGPU] s_quadmask* implicitly defines SCC (#161582)
Fix s_quadmask* instruction description so that it defines SCC.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 5bbf72400cfeb8f4e205e9ff1c98d34d2997796c
https://github.com/llvm/llvm-project/commit/5bbf72400cfeb8f4e205e9ff1c98d34d2997796c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/test/CodeGen/X86/avx512ifma-builtins.c
M clang/test/CodeGen/X86/avx512ifmavl-builtins.c
M clang/test/CodeGen/X86/avxifma-builtins.c
Log Message:
-----------
[X86] Add bytecode / -fexperimental-new-constant-interpreter VPMADD52 intrinsics test coverage (#161684)
Inspired by test problems encountered on #161056
Commit: afb262855e755b499a733c2b84b6a1cb789b3b1f
https://github.com/llvm/llvm-project/commit/afb262855e755b499a733c2b84b6a1cb789b3b1f
Author: Joel E. Denny <jdenny.ornl at gmail.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/Transforms/Utils/LoopPeel.cpp
A llvm/test/Transforms/LoopUnroll/peel-branch-weights-freq.ll
M llvm/test/Transforms/LoopUnroll/peel-branch-weights.ll
M llvm/test/Transforms/LoopUnroll/peel-loop-pgo-deopt.ll
M llvm/test/Transforms/LoopUnroll/peel-loop-pgo.ll
M llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
Log Message:
-----------
[LoopPeel] Fix branch weights' effect on block frequencies (#128785)
[LoopPeel] Fix branch weights' effect on block frequencies
This patch implements the LoopPeel changes discussed in [[RFC] Fix Loop
Transformations to Preserve Block
Frequencies](https://discourse.llvm.org/t/rfc-fix-loop-transformations-to-preserve-block-frequencies/85785).
In summary, a loop's latch block can have branch weight metadata that
encodes an estimated trip count that is derived from application profile
data. Initially, the loop body's block frequencies agree with the
estimated trip count, as expected. However, sometimes loop
transformations adjust those branch weights in a way that correctly
maintains the estimated trip count but that corrupts the block
frequencies. This patch addresses that problem in LoopPeel, which it
changes to:
- Maintain branch weights consistently with the original loop for the
sake of preserving the total frequency of the original loop body.
- Store the new estimated trip count in the
`llvm.loop.estimated_trip_count` metadata, introduced by PR #148758.
Commit: ed12dc5e306c6d062c71e89f47756e771792f4fb
https://github.com/llvm/llvm-project/commit/ed12dc5e306c6d062c71e89f47756e771792f4fb
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/test/Lower/OpenMP/declare-mapper.f90
A offload/test/offloading/fortran/target-declare-mapper-parent-allocatable.f90
Log Message:
-----------
[Flang][OpenMP] Implicitly map nested allocatable components in derived types (#160766)
This PR adds support for nested derived types and their mappers to the
MapInfoFinalization pass.
- Generalize MapInfoFinalization to add child maps for arbitrarily
nested allocatables when a derived object is mapped via declare mapper.
- Traverse HLFIR designates rooted at the target block arg and build
full coordinate_of chains; append members with correct membersIndex.
This fixes #156461.
Commit: 5ed678a1d9b428780744098078dc52387b1e7a79
https://github.com/llvm/llvm-project/commit/5ed678a1d9b428780744098078dc52387b1e7a79
Author: Fred Tingaud <95592999+frederic-tingaud-sonarsource at users.noreply.github.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/include/clang/Analysis/CFG.h
M clang/lib/Analysis/CFG.cpp
M clang/unittests/Analysis/CFGTest.cpp
Log Message:
-----------
[CFG] Add a BuildOption to consider default branch of switch on covered enumerations (#161345)
By default, the `default:` branch (or the successor if there is no
`default` and cases return) of a switch on fully covered enumerations is
considered as "Unreachable". It is a sane assumption in most cases, but
not always. That commit allows to change such behavior when needed.
Commit: 407ecfe6a3278968519628956484b546621ff545
https://github.com/llvm/llvm-project/commit/407ecfe6a3278968519628956484b546621ff545
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
Log Message:
-----------
[CIR][NFC] Cleanup MissingFeature asserts in RecordLayoutBuilder (#161605)
This change cleans up some cir::MissingFeature asserts in
CIRGenRecordLayoutBuilder.cpp. In a couple of cases the asserts were
stale markers that we failed to remove when the correspond support was
implemented.
In one case, a cir::MissingFeature::bitfields() assert was ambiguous in
meaning and has been replaced by a comment and something more specific.
The missing feature in this case is just a bit of debug code to verify
certain bitfield-related conditions. This check should be added, but it
is not functionally required.
Commit: 3c8c500a191e81044beeb6ec566f6aebd202c3c3
https://github.com/llvm/llvm-project/commit/3c8c500a191e81044beeb6ec566f6aebd202c3c3
Author: Jacob Lalonde <jalalonde at fb.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M lldb/source/API/SBTarget.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
Log Message:
-----------
[LLDB][NFC] Fix variable casing issue (#161691)
Fixes some casing mistakes I added in #161581
Commit: c2ef022aa7413ddc9aba48fa6fbe6fbd0cb14e19
https://github.com/llvm/llvm-project/commit/c2ef022aa7413ddc9aba48fa6fbe6fbd0cb14e19
Author: Tom Tromey <tromey at adacore.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/test/DebugInfo/X86/dynamic-bitfield.ll
Log Message:
-----------
Omit member size from DWARF when desired (#161423)
Commit: 18997b5a8fafe3b176529b83700d00d5b5876335
https://github.com/llvm/llvm-project/commit/18997b5a8fafe3b176529b83700d00d5b5876335
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/lib/Support/APFloat.cpp
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
[ADT] Fix a bug in DoubleAPFloat::frexp (#161625)
Without this patch, we call APFloat::makeQuiet() in frexp like so:
Quiet.getFirst().makeQuiet();
The problem is that makeQuiet returns a new value instead of modifying
"*this" in place, so we end up discarding the newly returned value.
This patch fixes the problem by assigning the result back to
Quiet.getFirst().
We should put [[nodiscard]] on APFloat::makeQuiet, but I'll do that in
another patch.
Commit: b43648818768620b615ee06517d58b6fc5d39583
https://github.com/llvm/llvm-project/commit/b43648818768620b615ee06517d58b6fc5d39583
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/BitVector.h
Log Message:
-----------
[ADT] Use a C++17 fold expression in BitVector.h (NFC) (#161626)
This patch simplifies the assertion by replacing the std::all_of check
with a more direct C++17 fold expression.
Commit: 0dd8f322c1b40bdac469eec248e3b2b4e1043754
https://github.com/llvm/llvm-project/commit/0dd8f322c1b40bdac469eec248e3b2b4e1043754
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/ConcurrentHashtable.h
Log Message:
-----------
[ADT] Use structured bindings (NFC) (#161627)
Both Size and Count are just integers, so I am not using & here.
Commit: 7eb5c08ac3a5bc524a5fe4e2e91db3a5b1ffe3cd
https://github.com/llvm/llvm-project/commit/7eb5c08ac3a5bc524a5fe4e2e91db3a5b1ffe3cd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/include/llvm/ADT/DirectedGraph.h
Log Message:
-----------
[ADT] Use "= default" in DirectedGraph.h (#161628)
This patch drops user copy/move constructors and assignment operators
of DirectedGraph to adhere to the Rule of Zero.
Now, the original code:
DGraphType &operator=(const DGraphType &&G)
is most likely unintended -- a move assignment operator with const
r-value reference. This patch fixes that.
Commit: c0a2bead5b471497c42966a73548f7690de2f301
https://github.com/llvm/llvm-project/commit/c0a2bead5b471497c42966a73548f7690de2f301
Author: Kazu Hirata <kazu at google.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/docs/TableGen/ProgRef.rst
Log Message:
-----------
[llvm] Proofread TableGen/ProgRef.rst (#161629)
Commit: 25126117b5781e96453e5c5b1a9a6a6f8aa3989c
https://github.com/llvm/llvm-project/commit/25126117b5781e96453e5c5b1a9a6a6f8aa3989c
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/remat.ll
Log Message:
-----------
[RegAlloc] Add coverage leading to revert of pr160765 (#161614)
Essentially what happened is the following series of events:
1) We rematerialized the vmv.v.x into the loop.
2) As this was the last use of the instruction, we deleted the
instruction, and removed it from the original live range.
3) We split the live range for the remat.
4) We tried to rematerialize the uses of that split interval, and
crashed because the assert about the def being available in
the original live interval does not hold.
Commit: 7789e642981e5be03a48510204b460f110f200de
https://github.com/llvm/llvm-project/commit/7789e642981e5be03a48510204b460f110f200de
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-10-02 (Thu, 02 Oct 2025)
Changed paths:
M clang/docs/InternalsManual.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/ASTConcept.h
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/Analysis/CFG.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaConcept.h
M clang/include/clang/Sema/Template.h
M clang/lib/AST/ASTConcept.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/Analysis/CFG.cpp
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/test/AST/ast-dump-concepts.cpp
M clang/test/AST/ast-dump-ctad-alias.cpp
M clang/test/CXX/drs/cwg25xx.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.id/p3.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/compound-requirement.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/nested-requirement.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/simple-requirement.cpp
M clang/test/CXX/expr/expr.prim/expr.prim.req/type-requirement.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.atomic/constrant-satisfaction-conversions.cpp
M clang/test/CXX/temp/temp.constr/temp.constr.normal/p1.cpp
M clang/test/CXX/temp/temp.param/p10-2a.cpp
M clang/test/CodeGen/X86/avx512ifma-builtins.c
M clang/test/CodeGen/X86/avx512ifmavl-builtins.c
M clang/test/CodeGen/X86/avxifma-builtins.c
A clang/test/Parser/recovery-after-expected-unqualified-id.cpp
M clang/test/SemaCXX/cxx23-assume.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaCXX/cxx2c-template-template-param.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
M clang/test/SemaCXX/invalid-requirement-requires-expr.cpp
M clang/test/SemaCXX/overload-resolution-deferred-templates.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaHLSL/BuiltIns/Buffers.hlsl
M clang/test/SemaHLSL/BuiltIns/RWBuffers.hlsl
M clang/test/SemaTemplate/concepts-recovery-expr.cpp
M clang/test/SemaTemplate/concepts-recursive-inst.cpp
M clang/test/SemaTemplate/concepts.cpp
M clang/test/SemaTemplate/deduction-guide.cpp
M clang/test/SemaTemplate/instantiate-abbreviated-template.cpp
M clang/test/SemaTemplate/instantiate-expanded-type-constraint.cpp
M clang/test/SemaTemplate/instantiate-requires-expr.cpp
M clang/test/SemaTemplate/instantiate-template-argument.cpp
M clang/test/SemaTemplate/pr52970.cpp
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/unittests/Analysis/CFGTest.cpp
M flang/include/flang/Lower/OpenACC.h
M flang/include/flang/Lower/SymbolMap.h
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/SymbolMap.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Lower/OpenACC/acc-host-data-cuda-device.f90
M flang/test/Lower/OpenMP/declare-mapper.f90
M libcxx/test/libcxx/algorithms/cpp17_iterator_concepts.verify.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/ConcurrentHashtable.h
M llvm/include/llvm/ADT/DirectedGraph.h
M llvm/include/llvm/CodeGen/MIRYamlMapping.h
M llvm/include/llvm/CodeGen/MachineFrameInfo.h
M llvm/include/llvm/CodeGen/TargetFrameLowering.h
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/RegAllocGreedy.cpp
M llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.h
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir
M llvm/test/CodeGen/AArch64/framelayout-sve.mir
M llvm/test/CodeGen/AArch64/spillfill-sve.mir
M llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
A llvm/test/CodeGen/Hexagon/unaligned-vec-store.ll
M llvm/test/CodeGen/RISCV/rvv/remat.ll
M llvm/test/CodeGen/X86/sbb.ll
M llvm/test/CodeGen/X86/shift-i128.ll
M llvm/test/DebugInfo/AArch64/asan-stack-vars.mir
M llvm/test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir
M llvm/test/DebugInfo/X86/dynamic-bitfield.ll
A llvm/test/Transforms/LoopUnroll/peel-branch-weights-freq.ll
M llvm/test/Transforms/LoopUnroll/peel-branch-weights.ll
M llvm/test/Transforms/LoopUnroll/peel-loop-pgo-deopt.ll
M llvm/test/Transforms/LoopUnroll/peel-loop-pgo.ll
M llvm/test/Transforms/LoopUnroll/scev-invalidation-lcssa.ll
A llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/reduction-order.ll
M llvm/unittests/ADT/APFloatTest.cpp
M mlir/include/mlir/Bindings/Python/NanobindAdaptors.h
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/IRTypes.cpp
M mlir/lib/Bindings/Python/MainModule.cpp
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
A offload/test/offloading/fortran/target-declare-mapper-parent-allocatable.f90
Log Message:
-----------
Merge branch 'main' into users/meinersbur/mlir_tile
Compare: https://github.com/llvm/llvm-project/compare/bcc5cd5ac358...7789e642981e
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