[all-commits] [llvm/llvm-project] 24bc1a: [RISCV] Update SiFive7's scheduling models with th...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 24bc1a60978cf6871d3381dcf92211509f658c76
      https://github.com/llvm/llvm-project/commit/24bc1a60978cf6871d3381dcf92211509f658c76
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-09-26 (Fri, 26 Sep 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/vgather-vcompress.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vgather-vcompress.s

  Log Message:
  -----------
  [RISCV] Update SiFive7's scheduling models with their optimizations on permutation instructions (#160763)

In newer SiFIve7 cores like X390, permutation instructions like
vrgather.vv operates on LMUL smaller than a single DLEN could yield a
constant cycle. For slightly larger data that fits in the constraint of
`log2(SEW/8) + log2(LMUL) <= log2(DLEN / 32)`, these instructions can
also yield cycles that are proportional to the quadratic of LMUL, rather
than being proportional to VL.

Co-authored-by: Michael Maitland <michaeltmaitland at gmail.com>



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