[all-commits] [llvm/llvm-project] fde15c: [LoongArch] Enable more vector tests for 32-bit ta...

[hev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fde15cb3eeb68461c66f6b5b928c7093393496a0
      https://github.com/llvm/llvm-project/commit/fde15cb3eeb68461c66f6b5b928c7093393496a0
  Author: hev <wangrui at loongson.cn>
  Date:   2025-09-25 (Thu, 25 Sep 2025)

  Changed paths:
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
    M llvm/test/CodeGen/LoongArch/lasx/bitreverse.ll
    M llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecipe.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrte.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-invalid-imm.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-invalid-imm.ll
    A llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-d-invalid-imm.ll
    A llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-d.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-invalid-imm.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr.ll
    A llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl-ins-gr2vr-d.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl-ins-gr2vr.ll
    A llvm/test/CodeGen/LoongArch/lasx/intrinsic-replgr2vr-d.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-replgr2vr.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-set.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-setallnez.ll
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-setanyeqz.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-element.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-extract-pair-elements.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvrepl128vei.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvshuf.ll
    M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvshuf4i.ll
    M llvm/test/CodeGen/LoongArch/lasx/shuffle-as-permute-and-shuffle.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-add.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll
    M llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-rotate.ll
    M llvm/test/CodeGen/LoongArch/lasx/xvmskcond.ll
    M llvm/test/CodeGen/LoongArch/lsx/bitreverse.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcmp.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecipe.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrte.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-invalid-imm.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-invalid-imm.ll
    A llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-d-invalid-imm.ll
    A llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-d.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-invalid-imm.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr.ll
    A llvm/test/CodeGen/LoongArch/lsx/intrinsic-repl-ins-gr2vr-d.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-repl-ins-gr2vr.ll
    A llvm/test/CodeGen/LoongArch/lsx/intrinsic-replgr2vr-d.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-replgr2vr.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-set.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-setallnez.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-setanyeqz.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/extractelement.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vreplvei.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vshuf.ll
    M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vshuf4i.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-any-ext.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-rotate.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-shift.ll
    M llvm/test/CodeGen/LoongArch/lsx/vec-trunc.ll
    M llvm/test/CodeGen/LoongArch/lsx/vmskcond.ll
    M llvm/test/CodeGen/LoongArch/lsx/widen-shuffle-mask.ll

  Log Message:
  -----------
  [LoongArch] Enable more vector tests for 32-bit target (#160656)



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