[all-commits] [llvm/llvm-project] 4cace1: [ARM] Verify that disassembled instruction is corr...

[Sergei Barannikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4cace1ff0f9a144de9f46f4521d140080e4e284d
      https://github.com/llvm/llvm-project/commit/4cace1ff0f9a144de9f46f4521d140080e4e284d
  Author: Sergei Barannikov <barannikov88 at gmail.com>
  Date:   2025-09-19 (Fri, 19 Sep 2025)

  Changed paths:
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    M llvm/test/MC/Disassembler/ARM/arm-tests.txt

  Log Message:
  -----------
  [ARM] Verify that disassembled instruction is correct (#157360)

This change adds basic `MCInst` verification (checks the number of
operands) and fixes detected bugs.

* `RFE*` instructions have only one operand, but `DecodeRFEInstruction`
added two.
* `DecodeMVEModImmInstruction` and `DecodeMVEVCMP` added a `vpred`
operand, but this is what `AddThumbPredicate` normally does. This
resulted in an extra `vpred` operand.
* `DecodeMVEVADCInstruction` added an extra immediate operand.
* `getARMInstruction` added a `pred` operand to instructions that don't
have one (via `DecodePredicateOperand`).
* `AddThumb1SBit` appended an extra register operand to instructions
that don't modify CPSR (such as `tBL`).
* Instructions in `NEONDup` namespace have `pred` operand that the
generated code successfully decodes. The operand was added once again by
`getARMInstruction`/`getThumbInstruction` via `AddThumbPredicate`.

Functional changes extracted from #156540.



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