[all-commits] [llvm/llvm-project] de9a50: [bazel][mlir] Port #155951: amdgpu dialect deps (#...

Thu Sep 18 13:42:52 PDT 2025

  Branch: refs/heads/users/rampitec/09-18-_amdgpu_gfx1251_vop2_dpp_support
  Home:   https://github.com/llvm/llvm-project
  Commit: de9a50a8a4151e194559b38a7bd56a9aa5bd2539
      https://github.com/llvm/llvm-project/commit/de9a50a8a4151e194559b38a7bd56a9aa5bd2539
  Author: Jordan Rupprecht <rupprecht at google.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  [bazel][mlir] Port #155951: amdgpu dialect deps (#159633)

  Commit: e8311f8ebc18066e774832b9c594697f28b6ca60
      https://github.com/llvm/llvm-project/commit/e8311f8ebc18066e774832b9c594697f28b6ca60
  Author: Qiu Chaofan <qcf at ecnelises.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    A llvm/test/DebugInfo/X86/split-dwarf-inline.ll

  Log Message:
  -----------
  [DebugInfo] Emit skeleton to avoid mismatching inlining flags (#153568)

This actually reverts 418120556398c01550d42500d56e6d328290185b.

The original commit omits unit with all symbols inlined into current
one, which leads to crash when a module using split-dwarf inlined a
function from another module with mismatched split-dwarf-inlining
option. This revert guarantees that DIEs are created in both DWO and the
skeleton sections whenever split-dwarf is active.

  Commit: 3fe85ca4e024df9330f263a99a2552952a5520bc
      https://github.com/llvm/llvm-project/commit/3fe85ca4e024df9330f263a99a2552952a5520bc
  Author: Matheus Izvekov <mizvekov at gmail.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Sema/SemaTemplate.cpp
    M clang/test/SemaTemplate/temp_arg_template.cpp

  Log Message:
  -----------
  [clang] check constant template parameters in dependent contexts (#159463)

This patch makes sure constant template parameters are checked even in
dependent contexts.

This can for example diagnose narrowings earlier, but this is permitted
as these templates would have no valid instantiations.

  Commit: a3f901f70a028bf369586b6ab561371a63922ce0
      https://github.com/llvm/llvm-project/commit/a3f901f70a028bf369586b6ab561371a63922ce0
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s

  Log Message:
  -----------
  [RISCV] Update floating point load latency in SiFive7 scheduling model (#159462)

The latency of floating point loads in SiFive7 should be the same as
their integer counterparts.

Co-authored-by: Michael Maitland <michaeltmaitland at gmail.com>

  Commit: 1cee4fa968f985489a50b88b66bd392c35f0870e
      https://github.com/llvm/llvm-project/commit/1cee4fa968f985489a50b88b66bd392c35f0870e
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vector-integer-arithmetic.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetivli-lmul-sew-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetvli-lmul-sew-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX390/fractional-lmul-data.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-integer-arithmetic.s

  Log Message:
  -----------
  [RISCV] Update the vector integer division cycle in SiFive7 scheduling model (#159468)

Vector integer division in SiFive7 processes a single bit at a time up
to 4 elements. This patch updates to reflect this behavior.

Co-authored-by: Michael Maitland <michaeltmaitland at gmail.com>

  Commit: 1c95d80ba68efd2ca9a0336529ea5fb7dc871417
      https://github.com/llvm/llvm-project/commit/1c95d80ba68efd2ca9a0336529ea5fb7dc871417
  Author: barsolo2000 <barsolo at meta.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M lldb/include/lldb/Core/Opcode.h
    M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
    M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
    M lldb/unittests/Instruction/CMakeLists.txt
    A lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp

  Log Message:
  -----------
  RISCV enable assembly unwinding (#158161)

**Added emulator unwinding support for RISCV files.**

Emulated Instructions:
ADD (addi sp, sp, imm)
STORE (sd ra, offset(sp))
LOAD (ld ra, offset(sp)).

We had to overwrite SetInstructions() since UnwindAssemblyInstEmulation
calls EvaluateInstruction() directly after calling SetInstruction(), but
it never calls ReadInstruction(). This means that the m_decoded member
variable in the instruction emulator is never properly initialized. By
overriding SetInstruction(), we decode the instruction bytes and set
m_decoded directly. This ensures that subsequent emulation (including
unwinding) operates on the correct instruction.

We also had to change the the OpCode GetOpcodeBytes function since
recent changes made it so GetOpcodeBytes will return None for type
eType16_32Tuples (an alternative and longer way, would've been to type
check during the overwritten SetInstruction() and call a DataExtractor
with .GetU16(&offset) to set the inst_data.

Added a test - TestSimpleRiscvFunction (took inspiration from:
[link](https://github.com/llvm/llvm-project/blob/main/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp))

[----------] 1 test from TestRiscvInstEmulation
[ RUN      ] TestRiscvInstEmulation.TestSimpleRiscvFunction
[       OK ] TestRiscvInstEmulation.TestSimpleRiscvFunction (1 ms)
[----------] 1 test from TestRiscvInstEmulation (1 ms total)

[----------] Global test environment tear-down
[==========] 63 tests from 5 test suites ran. (11 ms total)
[  PASSED  ] 63 tests.

---------

Co-authored-by: Bar Soloveychik <barsolo at fb.com>

  Commit: e3c7b7f806559a361d2cf8374d65230c75bb5829
      https://github.com/llvm/llvm-project/commit/e3c7b7f806559a361d2cf8374d65230c75bb5829
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/VOP1Instructions.td
    M llvm/test/CodeGen/AMDGPU/dpp64_combine.mir
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.gfx1251.ll
    A llvm/test/MC/AMDGPU/gfx1251_asm_vop1_dpp16.s
    A llvm/test/MC/AMDGPU/gfx1251_asm_vop1_err.s
    A llvm/test/MC/AMDGPU/gfx1251_err.s
    M llvm/test/MC/AMDGPU/gfx9-asm-err.s
    A llvm/test/MC/Disassembler/AMDGPU/gfx1251_dasm_vop1_dpp16.txt

  Log Message:
  -----------
  [AMDGPU] gfx1251 VOP1 dpp support (#159637)

  Commit: ace386e3d64c07227769f106d054717b89d1bc5d
      https://github.com/llvm/llvm-project/commit/ace386e3d64c07227769f106d054717b89d1bc5d
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2025-09-18 (Thu, 18 Sep 2025)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Sema/SemaTemplate.cpp
    M clang/test/SemaTemplate/temp_arg_template.cpp
    M lldb/include/lldb/Core/Opcode.h
    M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
    M lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h
    M lldb/unittests/Instruction/CMakeLists.txt
    A lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp
    M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    A llvm/test/DebugInfo/X86/split-dwarf-inline.ll
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/scalar-load-store.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vector-integer-arithmetic.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetivli-lmul-sew-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX280/vsetvli-lmul-sew-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX390/fractional-lmul-data.s
    M llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-integer-arithmetic.s
    M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel

  Log Message:
  -----------
  Merge branch 'main' into users/rampitec/09-18-_amdgpu_gfx1251_vop2_dpp_support

Compare: https://github.com/llvm/llvm-project/compare/344bfe15f023...ace386e3d64c

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