[all-commits] [llvm/llvm-project] 0700dd: GlobalISel: Relax verifier between physreg and typ...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/global-isel/relax-verifier-copy-physreg-mismatched-types
  Home:   https://github.com/llvm/llvm-project
  Commit: 0700dddc2628645d217d85a7787f414d8a42b9a7
      https://github.com/llvm/llvm-project/commit/0700dddc2628645d217d85a7787f414d8a42b9a7
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-09-17 (Wed, 17 Sep 2025)

  Changed paths:
    M llvm/lib/CodeGen/MachineVerifier.cpp
    A llvm/test/MachineVerifier/AMDGPU/test_copy_physregs_llt_virtreg.mir
    M llvm/test/MachineVerifier/test_copy_physregs_x86.mir

  Log Message:
  -----------
  GlobalISel: Relax verifier between physreg and typed vreg

Accept mismatched register size and type size if the type is legal
for the register class.

For AMDGPU boolean registers have 2 possible interpretations depending
on the use context type. e.g., these are both equally valid:

  %0:_(s1) = COPY $vcc
  %1:_(s64) = COPY $vcc

vcc is a 64-bit register, which can be interpreted as a 1-bit or 64-bit
value depending on the use context. SelectionDAG has never required exact
match between the register size and the used value type. You can assign
a type with a smaller size to a larger register class. Relax the verifier
to match.  There are several hacks holding together these copies in
various places, and this is preparation to remove one of them.

The x86 test change is from what I would consider an X86 usage bug. X86
defines an FR32 register class and F16 register class, but the F16 register
class is functionally an alias of F32 with the same members and size. There's
no need to have the F16 class.



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