[all-commits] [llvm/llvm-project] ea59be: [ValueTracking] Don't take sign bit from NaN opera...
Ryotaro Kasuga via All-commits
all-commits at lists.llvm.org
Tue Sep 16 11:48:45 PDT 2025
Branch: refs/heads/users/kasuga-fj/da-fix-exact-siv-ovfl-2
Home: https://github.com/llvm/llvm-project
Commit: ea59be552f1db4f8f2e8a3edd909f17802339970
https://github.com/llvm/llvm-project/commit/ea59be552f1db4f8f2e8a3edd909f17802339970
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/is_fpclass.ll
Log Message:
-----------
[ValueTracking] Don't take sign bit from NaN operands (#157250)
Closes https://github.com/llvm/llvm-project/issues/157238.
Commit: 66a8f47066caad76458190d820b7f4bea7c602c5
https://github.com/llvm/llvm-project/commit/66a8f47066caad76458190d820b7f4bea7c602c5
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLPVectorizer][NFC] Save stride in a map. (#157706)
In order to avoid recalculating stride of strided load twice save it in
a map.
Commit: 3c7c8929d415ab773c88e7e0a668930738f98e56
https://github.com/llvm/llvm-project/commit/3c7c8929d415ab773c88e7e0a668930738f98e56
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/test/TableGen/HwModeEncodeDecode3.td
M llvm/test/TableGen/RegisterEncoder.td
M llvm/utils/TableGen/CodeEmitterGen.cpp
Log Message:
-----------
[TableGen][CodeEmitter] Refactor addCodeToMergeInOperand (NFC) (#158674)
* Use streams to avoid dealing with std::string
* Print operand masks in hex
* Make the output more succinct
Commit: 666e4313ebc03587f27774139ad8f780bac15c3e
https://github.com/llvm/llvm-project/commit/666e4313ebc03587f27774139ad8f780bac15c3e
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
Log Message:
-----------
[NFC][LV] Improve ee with sideeffects legality test (#158275)
Addressing postcommit comments for
54fc5367f63cca8e011d93bbd55764b0a7ecbbd5
Commit: 33c33d0e0d143fb6197f191921d2b6e4470855da
https://github.com/llvm/llvm-project/commit/33c33d0e0d143fb6197f191921d2b6e4470855da
Author: jiang1997 <jieke at live.cn>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/invalid.mlir
Log Message:
-----------
[MLIR] Use IntValidAlignment for alignment attributes (#158137)
This PR refactors alignment validation in MLIR's MemRef and SPIRV
dialects:
- Use `IntValidAlignment` for consistent type safety across MemRef and
SPIRV dialects
- Eliminate duplicate validation logic in `MemRefOps.cpp`
- Adjust error messages in `invalid.mlir` to match improved validation
This is the first of two PRs addressing issue #155677.
Commit: 311d78f2a1d80fd6b7700a0199c146accd2c7d3c
https://github.com/llvm/llvm-project/commit/311d78f2a1d80fd6b7700a0199c146accd2c7d3c
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M offload/test/offloading/force-usm.cpp
Log Message:
-----------
[OpenMP] Fix force-usm test after #157182 (#159095)
The refactoring lead to an additional data transfer. This changes the
assumed transfers in the check-strings to work with that changed
behavior.
Commit: e7101dac9cbdad08696a05b4b73ed76c20a6f2fc
https://github.com/llvm/llvm-project/commit/e7101dac9cbdad08696a05b4b73ed76c20a6f2fc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/JIT.h
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/JIT.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
Log Message:
-----------
[Offload] Copy loaded images into managed storage (#158748)
Summary:
Currently we have this `__tgt_device_image` indirection which just takes
a reference to some pointers. This was all find and good when the only
usage of this was from a section of GPU code that came from an ELF
constant section. However, we have expanded beyond that and now need to
worry about managing lifetimes. We have code that references the image
even after it was loaded internally. This patch changes the
implementation to instaed copy the memory buffer and manage it locally.
This PR reworks the JIT and other image handling to directly manage its
own memory. We now don't need to duplicate this behavior externally at
the Offload API level. Also we actually free these if the user unloads
them.
Upside, less likely to crash and burn. Downside, more latency when
loading an image.
Commit: 148e099b39a25ea4336faeef485c53819b269fc2
https://github.com/llvm/llvm-project/commit/148e099b39a25ea4336faeef485c53819b269fc2
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-target-default-as.mlir
Log Message:
-----------
[MLIR][OpenMP] Set default address space for OpenMPIRBuilder (#158689)
Extension of https://github.com/llvm/llvm-project/pull/158152 for MLIR.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: ce073a9445a2eaf5810ea734e2dcad6f14441218
https://github.com/llvm/llvm-project/commit/ce073a9445a2eaf5810ea734e2dcad6f14441218
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
R llvm/test/TableGen/AsmPredicateCondsEmission.td
A llvm/test/TableGen/DecoderEmitter/AsmPredicateCondsEmission.td
A llvm/test/TableGen/DecoderEmitter/DecoderEmitterBitwidthSpecialization.td
A llvm/test/TableGen/DecoderEmitter/DecoderEmitterFnTable.td
A llvm/test/TableGen/DecoderEmitter/VarLenDecoder.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission2.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission3.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission4.td
R llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td
R llvm/test/TableGen/DecoderEmitterFnTable.td
R llvm/test/TableGen/VarLenDecoder.td
R llvm/test/TableGen/trydecode-emission.td
R llvm/test/TableGen/trydecode-emission2.td
R llvm/test/TableGen/trydecode-emission3.td
R llvm/test/TableGen/trydecode-emission4.td
Log Message:
-----------
[NFC][TableGen] Move decoder tests to DecoderEmitter directory (#159040)
Commit: 334013b090eef5b97cef8bc1817ed9ff67680488
https://github.com/llvm/llvm-project/commit/334013b090eef5b97cef8bc1817ed9ff67680488
Author: James Y Knight <jyknight at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/Statistic.h
Log Message:
-----------
Mark STATISTIC variables as maybe_unused when stats are disabled. (#159103)
PR #159045 made the constructor constexpr, which allows
`-Wunused-variable` to trigger. However, we don't really care if a
statistic is unused if `LLVM_ENABLE_STATS` is 0.
Commit: b3fa92fd4edce2d9be61eb289a179a98bcf13880
https://github.com/llvm/llvm-project/commit/b3fa92fd4edce2d9be61eb289a179a98bcf13880
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen][Decoder] Make predicate/decocder generation functions return a string (NFC) (#159089)
These functions will see more uses in a future patch.
This also resolves a FIXME.
Commit: 2771d35e2aaf76cf3716954d6094a822e56dfda5
https://github.com/llvm/llvm-project/commit/2771d35e2aaf76cf3716954d6094a822e56dfda5
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[NFC ]Add a helper function isTailCall for getting libcall in SelectionDAG (#155256)
Based on comment of
https://github.com/llvm/llvm-project/pull/153600#discussion_r2285729269,
Add a helper function isTailCall for getting libcall in SelectionDAG.
Commit: 7e71877835a567ada4d0e57413a5f64de3545033
https://github.com/llvm/llvm-project/commit/7e71877835a567ada4d0e57413a5f64de3545033
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/STLExtras.h
M llvm/unittests/ADT/STLExtrasTest.cpp
Log Message:
-----------
[ADT] Wrapper for `std::accumulate` accepting a `range`. (#158702)
Commit: a4c5a747c5507d0c45524e45082389089fa9a791
https://github.com/llvm/llvm-project/commit/a4c5a747c5507d0c45524e45082389089fa9a791
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
Log Message:
-----------
AMDGPU: Regenerate baseline test checks for some gfx12 mc tests (#159098)
Commit: 44b686e52ec462c173d0b114172db2a783215116
https://github.com/llvm/llvm-project/commit/44b686e52ec462c173d0b114172db2a783215116
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
A llvm/test/CodeGen/AArch64/pr157252.mir
Log Message:
-----------
[AArch64] Unfold adds when eliminating frame index with scalable offset (#158597)
Fixes https://github.com/llvm/llvm-project/issues/157252.
Peephole optimization tends to fold:
```
add %gpr1, %stack, 0
subs %gpr2, %gpr1, 0
```
to
```
adds %gpr2, %stack, 0
```
This patch undoes the fold in `rewriteAArch64FrameIndex` to process
`adds` on the stack object.
Commit: a42aac5f83e272f83207844dde1530b86e6fcf2b
https://github.com/llvm/llvm-project/commit/a42aac5f83e272f83207844dde1530b86e6fcf2b
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/DebugSSAUpdater.h
Log Message:
-----------
[DebugInfo] Fix memory leak in DebugSSAUpdater (#159107)
Fixes an issue in commit 3946c50, PR #135349.
The DebugSSAUpdater class performs raw pointer allocations. It frees
these properly in reset(), but does not do so in its destructor - as an
immediate fix, this patch adds a destructor which frees the allocations
correctly.
I'll be merging this immediately to fix the issue, but will be open to
post-commit review and/or producing a better fix in a follow-up commit.
Commit: eeced0d073ee387d98e39fdcada2277ad81cd4a9
https://github.com/llvm/llvm-project/commit/eeced0d073ee387d98e39fdcada2277ad81cd4a9
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-snop-padding.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
Log Message:
-----------
[AMDGPU] Use larger immediate values in S_NOP (#158990)
The S_NOP instruction has an immediate operand which is one less than
the number of cycles to delay for. The maximum value that may be encoded
in this field was increased in GFX8 and again in GFX12.
Commit: 175bab32d7f37bfb854b89c0da7e9f4aa427bc70
https://github.com/llvm/llvm-project/commit/175bab32d7f37bfb854b89c0da7e9f4aa427bc70
Author: Mikołaj Piróg <mikolaj.maciej.pirog at intel.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/test/CodeGen/X86/avx512-fma.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
M llvm/test/CodeGen/X86/dag-combiner-fma-folding.ll
M llvm/test/CodeGen/X86/fma-do-not-commute.ll
M llvm/test/CodeGen/X86/fma_patterns.ll
M llvm/test/CodeGen/X86/fma_patterns_wide.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
Log Message:
-----------
[X86] Don't rely on global -fp-contract=fast on X86 CodeGen tests (#158026)
IR has the `contract` to indicate that contraction is allowed. Testing
shouldn't rely on global flag to perform contraction. This is a
prerequisite before making backends rely only on the IR to perform
contraction. See more here:
https://discourse.llvm.org/t/allowfpopfusion-vs-sdnodeflags-hasallowcontract/80909/5
Commit: beb6bab87e6370087049bb900155d5ca164acc15
https://github.com/llvm/llvm-project/commit/beb6bab87e6370087049bb900155d5ca164acc15
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in LowerGpuOpsToROCDLOps.cpp (NFC)
Commit: f017bcb3e375843dc146eda823fcdd4c95a10153
https://github.com/llvm/llvm-project/commit/f017bcb3e375843dc146eda823fcdd4c95a10153
Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp
M mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-khr-coop-matrix.mlir
Log Message:
-----------
[mlir][gpu][spirv] Add conversion for gpu.subgroup_mma_elementwise mulf (#158832)
gpu.subgroup_mma_elementwise supports mulf op type. Add conversion for it.
Commit: babdad3fdbc66b4992654f9b7dc0fa4da85bd843
https://github.com/llvm/llvm-project/commit/babdad3fdbc66b4992654f9b7dc0fa4da85bd843
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-17 (Wed, 17 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
Log Message:
-----------
AMDGPU: Try to unspill VGPRs after rewriting MFMAs to AGPR form (#154323)
After replacing VGPR MFMAs with the AGPR form, we've alleviated VGPR
pressure which may have triggered spills during allocation. Identify
these spill slots, and try to reassign them to newly freed VGPRs,
and replace the spill instructions with copies.
Fixes #154260
Commit: 9865f7ec2bb15f3d8aa25c7e9305393422597dc5
https://github.com/llvm/llvm-project/commit/9865f7ec2bb15f3d8aa25c7e9305393422597dc5
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/WinogradConv2D.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in WinogradConv2D.cpp (NFC)
Commit: 30633f30894129919050f24fdd1f8f6bc46beae0
https://github.com/llvm/llvm-project/commit/30633f30894129919050f24fdd1f8f6bc46beae0
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M clang-tools-extra/clang-include-fixer/IncludeFixer.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang-tools-extra/include-cleaner/unittests/RecordTest.cpp
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/ChainedIncludesSource.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/Rewrite/FrontendActions.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp
M clang/lib/Testing/TestAST.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/tools/clang-import-test/clang-import-test.cpp
M clang/tools/clang-installapi/ClangInstallAPI.cpp
M clang/tools/driver/cc1_main.cpp
M clang/unittests/AST/ExternalASTSourceTest.cpp
M clang/unittests/CodeGen/TestCompiler.h
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/CodeGenActionTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/FrontendActionTest.cpp
M clang/unittests/Frontend/OutputStreamTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Support/TimeProfilerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
Log Message:
-----------
[clang] Initialize the file system explicitly (#158381)
This PR is a part of the effort to make the VFS used in the compiler
more explicit and consistent.
Instead of creating the VFS deep within the compiler (in
`CompilerInstance::createFileManager()`), clients are now required to
explicitly call `CompilerInstance::createVirtualFileSystem()` and
provide the base VFS from the outside.
This PR also helps in breaking up the dependency cycle where creating a
properly configured `DiagnosticsEngine` requires a properly configured
VFS, but creating properly configuring a VFS requires the
`DiagnosticsEngine`.
Both `CompilerInstance::create{FileManager,Diagnostics}()` now just use
the VFS already in `CompilerInstance` instead of taking one as a
parameter, making the VFS consistent across the instance sub-object.
Commit: 08a58b2cea3c11cb94b565e50a85de4d7b78fe65
https://github.com/llvm/llvm-project/commit/08a58b2cea3c11cb94b565e50a85de4d7b78fe65
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
A llvm/test/Transforms/InstCombine/redundant-fcmp.ll
Log Message:
-----------
[InstCombine] Optimize redundant floating point comparisons in `or`/`and` inst's (#158097)
Resolves #157371
We can eliminate one of the `fcmp` when we have two same `olt` or `ogt`
instructions matched in `or`/`and` simplification.
Commit: 3388d40684742e950b3c5d1d2dafe5a40695cfc1
https://github.com/llvm/llvm-project/commit/3388d40684742e950b3c5d1d2dafe5a40695cfc1
Author: quic-k <kushpal at qti.qualcomm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
A compiler-rt/cmake/caches/hexagon-builtins-baremetal.cmake
Log Message:
-----------
[cmake] Add cmake file for hexagon-builtins baremetal (#151500)
This will be used to build hexagon-builtins for baremetal.
Signed-off-by: Kushal Pal <kushpal at qti.qualcomm.com>
Commit: d2fbca8a85991019c061cc83f18d3030e843d0d7
https://github.com/llvm/llvm-project/commit/d2fbca8a85991019c061cc83f18d3030e843d0d7
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/test/Lower/HLFIR/eoshift.f90
Log Message:
-----------
[flang] Allow polymorphic type mismatch for hlfir.eoshift. (#158718)
When the ARRAY has polymorphic type, its element type may not match
the element type of BOUNDARY.
Fixes #158382.
Commit: 6aab826e2334fe454c5e2349d871f16d7d011a4c
https://github.com/llvm/llvm-project/commit/6aab826e2334fe454c5e2349d871f16d7d011a4c
Author: guan jian <148229859+rez5427 at users.noreply.github.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/AArch64/xor-min-max.ll
Log Message:
-----------
[DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) (#155141)
Hi, I compared the following LLVM IR with GCC and Clang, and there is a small difference between the two. The LLVM IR is:
```
define i64 @test_smin_neg_one(i64 %a) {
%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1)
%retval.0 = xor i64 %1, -1
ret i64 %retval.0
}
```
GCC generates:
```
cmp x0, 0
csinv x0, xzr, x0, ge
ret
```
Clang generates:
```
cmn x0, #1
csinv x8, x0, xzr, lt
mvn x0, x8
ret
```
Clang keeps flipping x0 through x8 unnecessarily.
So I added the following folds to DAGCombiner:
fold (xor (smax(x, C), C)) -> select (x > C), xor(x, C), 0
fold (xor (smin(x, C), C)) -> select (x < C), xor(x, C), 0
alive2: https://alive2.llvm.org/ce/z/gffoir
---------
Co-authored-by: Yui5427 <785369607 at qq.com>
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: ee66d967db6b812ed82a14dda369a3cae79f6632
https://github.com/llvm/llvm-project/commit/ee66d967db6b812ed82a14dda369a3cae79f6632
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen][DecoderEmitter] Inline a couple of trivial functions (NFC) (#159099)
Commit: 3ef066f8a369e1fe10f5408d535ce782fb39490f
https://github.com/llvm/llvm-project/commit/3ef066f8a369e1fe10f5408d535ce782fb39490f
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen][DecoderEmitter] Change SmallSetVector to SetVector (NFC) (#159108)
SmallSetVector is too optimistic, there are usually more than 16 unique
decoders and predicates. Modernize `typedef` to `using` while here.
Commit: 341cdbc9703d3cdd151f897b63548387f0017f49
https://github.com/llvm/llvm-project/commit/341cdbc9703d3cdd151f897b63548387f0017f49
Author: Janek van Oirschot <janek.vanoirschot at amd.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/imm.ll
Log Message:
-----------
[AMDGPU] Elide bitcast fold i64 imm to build_vector (#154115)
Elide bitcast combine to build_vector in case of i64 immediate that can
be materialized through 64b mov
Commit: f9f62ef4ae555a86878411e696b8b747851fc337
https://github.com/llvm/llvm-project/commit/f9f62ef4ae555a86878411e696b8b747851fc337
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/BasicAliasAnalysis.h
M llvm/include/llvm/Analysis/TypeBasedAliasAnalysis.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
A llvm/test/Transforms/InstCombine/may-alias-errno.ll
Log Message:
-----------
[AA] Refine ModRefInfo taking into account `errnomem` location
Ensure alias analyses mask out `errnomem` location, refining the
resulting modref info, when the given access/location does not
alias errno. This may occur either when TBAA proves there is no
alias with errno (e.g., float TBAA for the same root would be
disjoint with the int-only compatible TBAA node for errno); or
if the memory access size is larger than the integer size, or
when the underlying object is a potentially-escaping alloca.
Previous discussion: https://discourse.llvm.org/t/rfc-modelling-errno-memory-effects/82972.
Commit: 3eea01e73117c2b916930cd64c1acbcdc5ace44d
https://github.com/llvm/llvm-project/commit/3eea01e73117c2b916930cd64c1acbcdc5ace44d
Author: Damian Heaton <Damian.Heaton at arm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/sve2p1-dots-partial-reduction.ll
Log Message:
-----------
[AArch64] Add ISel support for partial reductions to use SVE2.1 udot/sdot (#158310)
This allows dot products with scalable 8xi16 vectors (and fixed-length
vectors which are converted into a scalable vector) accumulating into a
4xi32 vector to lower into a single instruction (`udot`/`sdot`), rather
than a sequence of `umlalb`s and `umlalt`s`.
Commit: 3938ce96ad97acd26f4a7610d5cd3b2dac796c29
https://github.com/llvm/llvm-project/commit/3938ce96ad97acd26f4a7610d5cd3b2dac796c29
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/Twine.h
Log Message:
-----------
[ADT] Update comments in Twine.h (NFC) (#158783)
Twine now stores integers by value, so this patch updates comments
accordingly.
Commit: b27bb09f6d02e750c4126aeffb7a2ecf0d6ab783
https://github.com/llvm/llvm-project/commit/b27bb09f6d02e750c4126aeffb7a2ecf0d6ab783
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M clang/include/clang/AST/TypeBase.h
Log Message:
-----------
[AST] Simplify TypeIsArrayType (NFC) (#158784)
This patch simplifies replaces TypeIsArrayType. If
std::is_same<ArrayType, ArrayType> is true, then
std::is_base_of<ArrayType, ArrayType> must also be true, so
std::is_base_of<ArrayType, ArrayType> alone is sufficient.
Commit: 096b8a8b89f3234972770e0581e059073d106b7c
https://github.com/llvm/llvm-project/commit/096b8a8b89f3234972770e0581e059073d106b7c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/PackedVector.h
M llvm/unittests/ADT/PackedVectorTest.cpp
Log Message:
-----------
[ADT] Fix an indexing bug in PackedVector (#158785)
PackedVector is like std::vector<int> except that we can store small
elements (e.g. 2-bit elements) in a packed manner using a BitVector as
the underlying storage.
The problem is that for bit size 3 and beyond, the calculation of
indices into the underlying BitVector is not correct. For example,
around line 50, we see a "for" loop to retrieve an unsigned integer
value:
for (unsigned i = 0; i != BitNum-1; ++i)
val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i));
Suppose that BitNum is 4 (that is, 4-bit item). Here is the mapping
between the PackedVector index and the corresponding BitVector
indices.
Idx 0: 0, 1, 2, 3
Idx 1: 8, 9, 10, 11
Idx 2: 16, 17, 18, 19
That is, we use 4 bits out of every 8 bits. This is because the index
calculation uses "<<". The index should really be Idx * BitNum + i.
FWIW, all the methods in PackedVector consistently use the shift-based
index calculation, so the user would never encounter a bug except
possibly as excessive storage use.
This patch fixes the index calculation. Now, in size(), I didn't want
to do integer division:
return Bits.size() / BitNum;
so this patch adds a separate variable NumElements to keep track of
the number of elements.
The unit test checks for the expected size of the underlying
BitVector.
Commit: 99a0139e28f7c69583684efb1907451fc9d0b0bf
https://github.com/llvm/llvm-project/commit/99a0139e28f7c69583684efb1907451fc9d0b0bf
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/Support/AMDHSAKernelDescriptor.h
Log Message:
-----------
[Support] Remove offsetof in AMDHSAKernelDescriptor.h (#158786)
This patch removes offsetof. Note that we already include <cstddef>
and that <cstddef> defines offsetof.
Commit: 3fe05ba24fcaeeb0280e9c364d1b193aadbd2348
https://github.com/llvm/llvm-project/commit/3fe05ba24fcaeeb0280e9c364d1b193aadbd2348
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/docs/GarbageCollection.rst
Log Message:
-----------
[llvm] Proofread GarbageCollection.rst (#158787)
Commit: 0864965e54a2ae050898ca0a3bb1d07f8fabe954
https://github.com/llvm/llvm-project/commit/0864965e54a2ae050898ca0a3bb1d07f8fabe954
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen][DecoderEmitter] Replace opcode mask with booleans (NFC) (#159113)
Extracted from #155889, which removes inclusion of `MCDecoderOps.h`.
Commit: c3fb2e1cee954338acb83955b157e0a2e82a4849
https://github.com/llvm/llvm-project/commit/c3fb2e1cee954338acb83955b157e0a2e82a4849
Author: yonghong-song <yhs at fb.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
A llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFInstrInfo.cpp
M llvm/lib/Target/BPF/BPFInstrInfo.h
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFMCInstLower.cpp
M llvm/lib/Target/BPF/BPFMCInstLower.h
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/lib/Target/BPF/BPFSubtarget.h
A llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.cpp
A llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.h
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/CMakeLists.txt
A llvm/test/CodeGen/BPF/jump_table_blockaddr.ll
A llvm/test/CodeGen/BPF/jump_table_global_var.ll
A llvm/test/CodeGen/BPF/jump_table_switch_stmt.ll
Log Message:
-----------
[BPF] Support Jump Table (#149715)
Add jump table (switch statement and computed goto) support for BPF
backend.
A `gotox <reg>` insn is implemented and the `<reg>` holds the target
insn where the gotox will go.
For a switch statement like
```
...
switch (ctx->x) {
case 1: ret_user = 18; break;
case 20: ret_user = 6; break;
case 16: ret_user = 9; break;
case 6: ret_user = 16; break;
case 8: ret_user = 14; break;
case 30: ret_user = 2; break;
default: ret_user = 1; break;
}
...
```
and the final binary
```
The final binary:
4: 67 01 00 00 03 00 00 00 r1 <<= 0x3
5: 18 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r2 = 0x0 ll
0000000000000028: R_BPF_64_64 BPF.JT.0.0
7: 0f 12 00 00 00 00 00 00 r2 += r1
...
Symbol table:
4: 0000000000000000 240 OBJECT GLOBAL DEFAULT 4 BPF.JT.0.0
5: 0000000000000000 4 OBJECT GLOBAL DEFAULT 6 ret_user
6: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND bar
7: 00000000000000f0 256 OBJECT GLOBAL DEFAULT 4 BPF.JT.0.1
and
[ 4] .jumptables PROGBITS 0000000000000000 0001c8 0001f0 00 0 0 1
```
Note that for the above example, `-mllvm -bpf-min-jump-table-entries=5`
should be in compilation flags as the current default
bpf-min-jump-table-entries is 13. For example.
```
clang --target=bpf -mcpu=v4 -O2 -mllvm -bpf-min-jump-table-entries=5 -S -g test.c
```
For computed goto like
```
int foo(int a, int b) {
__label__ l1, l2, l3, l4;
void *jt1[] = {[0]=&&l1, [1]=&&l2};
void *jt2[] = {[0]=&&l3, [1]=&&l4};
int ret = 0;
goto *jt1[a % 2];
l1: ret += 1;
l2: ret += 3;
goto *jt2[b % 2];
l3: ret += 5;
l4: ret += 7;
return ret;
}
```
The final binary:
```
12: bf 23 20 00 00 00 00 00 r3 = (s32)r2
13: 67 03 00 00 03 00 00 00 r3 <<= 0x3
14: 18 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r2 = 0x0 ll
0000000000000070: R_BPF_64_64 BPF.JT.0.0
16: 0f 32 00 00 00 00 00 00 r2 += r3
17: bf 11 20 00 00 00 00 00 r1 = (s32)r1
18: 67 01 00 00 03 00 00 00 r1 <<= 0x3
19: 18 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r3 = 0x0 ll
0000000000000098: R_BPF_64_64 BPF.JT.0.1
21: 0f 13 00 00 00 00 00 00 r3 += r1
[ 4] .jumptables PROGBITS 0000000000000000 000160 000020 00 0 0 1
4: 0000000000000000 16 OBJECT GLOBAL DEFAULT 4 BPF.JT.0.0
5: 0000000000000010 16 OBJECT GLOBAL DEFAULT 4 BPF.JT.0.1
```
A more complicated test with both switch-statement triggered jump table
and compute gotos:
```
$ cat test3.c
struct simple_ctx {
int x;
int y;
int z;
};
int ret_user, ret_user2;
void bar(void);
int foo(struct simple_ctx *ctx, struct simple_ctx *ctx2, int a, int b)
{
__label__ l1, l2, l3, l4;
void *jt1[] = {[0]=&&l1, [1]=&&l2};
void *jt2[] = {[0]=&&l3, [1]=&&l4};
int ret = 0;
goto *jt1[a % 2];
l1: ret += 1;
l2: ret += 3;
goto *jt2[b % 2];
l3: ret += 5;
l4: ret += 7;
bar();
switch (ctx->x) {
case 1: ret_user = 18; break;
case 20: ret_user = 6; break;
case 16: ret_user = 9; break;
case 6: ret_user = 16; break;
case 8: ret_user = 14; break;
case 30: ret_user = 2; break;
default: ret_user = 1; break;
}
return ret;
}
```
Compile with
```
clang --target=bpf -mcpu=v4 -O2 -S test3.c
clang --target=bpf -mcpu=v4 -O2 -c test3.c
```
The binary:
```
/* For computed goto */
13: bf 42 20 00 00 00 00 00 r2 = (s32)r4
14: 67 02 00 00 03 00 00 00 r2 <<= 0x3
15: 18 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r1 = 0x0 ll
0000000000000078: R_BPF_64_64 BPF.JT.0.1
17: 0f 21 00 00 00 00 00 00 r1 += r2
18: bf 32 20 00 00 00 00 00 r2 = (s32)r3
19: 67 02 00 00 03 00 00 00 r2 <<= 0x3
20: 18 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r3 = 0x0 ll
00000000000000a0: R_BPF_64_64 BPF.JT.0.2
22: 0f 23 00 00 00 00 00 00 r3 += r2
/* For switch statement */
39: 67 01 00 00 03 00 00 00 r1 <<= 0x3
40: 18 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 r2 = 0x0 ll
0000000000000140: R_BPF_64_64 BPF.JT.0.0
42: 0f 12 00 00 00 00 00 00 r2 += r1
```
You can see jump table symbols are all different.
Commit: 1327288324c5084a6f09100fa78f2e084836a282
https://github.com/llvm/llvm-project/commit/1327288324c5084a6f09100fa78f2e084836a282
Author: Alexey Karyakin <akaryaki at quicinc.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
A llvm/test/CodeGen/Hexagon/vsubsat.ll
Log Message:
-----------
[Hexagon] Lowering saturating subtraction (#158726)
Saturating arithmetic can be expressed by llvm.uadd/usub.sat generic
intrinsics.
Commit: b22448c9ba90efb3a2a6a7bdb8ffeeee9fcabb62
https://github.com/llvm/llvm-project/commit/b22448c9ba90efb3a2a6a7bdb8ffeeee9fcabb62
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
A llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
Log Message:
-----------
[PowerPC] Add intrinsic definition for load and store with Right Length Left-justified (#148873)
Commit: e75e28ad3c9558c2cca32cd16cd5681b5219ff8d
https://github.com/llvm/llvm-project/commit/e75e28ad3c9558c2cca32cd16cd5681b5219ff8d
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-parse-tree.cpp
M flang/test/Parser/OpenMP/bind-clause.f90
M flang/test/Parser/OpenMP/declare-reduction-multi.f90
M flang/test/Parser/OpenMP/declare-reduction-unparse.f90
M flang/test/Parser/OpenMP/do-tile-size.f90
M flang/test/Parser/OpenMP/doacross-clause.f90
M flang/test/Parser/OpenMP/if-clause.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
M flang/test/Parser/OpenMP/lastprivate-clause.f90
M flang/test/Parser/OpenMP/linear-clause.f90
M flang/test/Parser/OpenMP/loop-transformation-construct01.f90
M flang/test/Parser/OpenMP/loop-transformation-construct02.f90
M flang/test/Parser/OpenMP/loop-transformation-construct03.f90
M flang/test/Parser/OpenMP/masked-unparse.f90
M flang/test/Parser/OpenMP/master-unparse.f90
M flang/test/Parser/OpenMP/order-clause01.f90
M flang/test/Parser/OpenMP/ordered-depend.f90
M flang/test/Parser/OpenMP/reduction-modifier.f90
M flang/test/Parser/OpenMP/target-loop-unparse.f90
M flang/test/Parser/OpenMP/taskloop.f90
M flang/test/Parser/OpenMP/tile-size.f90
M flang/test/Parser/OpenMP/tile.f90
M flang/test/Parser/OpenMP/transparent-clause.f90
M flang/test/Parser/OpenMP/unroll-full.f90
M flang/test/Parser/OpenMP/unroll-heuristic.f90
M flang/test/Parser/OpenMP/unroll-partial.f90
M flang/test/Semantics/OpenMP/simd-only.f90
Log Message:
-----------
[flang][OpenMP] Use OmpDirectiveSpecification in Omp[Begin|End]LoopDi… (#159087)
…rective
This makes accessing directive components, such as directive name or the
list of clauses simpler and more uniform across different directives. It
also makes the parser simpler, since it reuses existing parsing
functionality.
The changes are scattered over a number of files, but they all share the
same nature:
- getting the begin/end directive from OpenMPLoopConstruct,
- getting the llvm::omp::Directive enum, and the source location,
- getting the clause list.
Commit: 0cf668889823e7dc526b0b3039c22452f61538f2
https://github.com/llvm/llvm-project/commit/0cf668889823e7dc526b0b3039c22452f61538f2
Author: Fangrui Song <i at maskray.me>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/include/llvm/MC/MCContext.h
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCParser/MCAsmParser.cpp
M llvm/lib/MC/MCParser/MCAsmParserExtension.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCParser/WasmAsmParser.cpp
A llvm/test/CodeGen/X86/symbol-name.ll
M llvm/test/MC/ELF/cgprofile.s
M llvm/test/MC/ELF/symbol-names.s
Log Message:
-----------
MC: Better handle backslash-escaped symbols (#158780)
The MCContext::getOrCreateSymbol change in #138817 was a workaround.
With #158106, we can replace `getOrCreateSymbol` with `parseSymbol`, in
llvm/lib/MC/MCParser to handle backslash-escaped symbols.
Commit: 4be1099607c97b9f28cd30d56149e7c6428c216c
https://github.com/llvm/llvm-project/commit/4be1099607c97b9f28cd30d56149e7c6428c216c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
Log Message:
-----------
[RISCV] Improve fixed vector handling in isCtpopFast. (#158380)
Previously we considered fixed vectors fast if Zvbb or Zbb is
enabled. Zbb only helps if the vector type will end up being
scalarized.
Commit: ba5ca37f40b82e287a3e0469fb0f0ea48b651aca
https://github.com/llvm/llvm-project/commit/ba5ca37f40b82e287a3e0469fb0f0ea48b651aca
Author: John Harrison <harjohn at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M lldb/source/Host/common/Socket.cpp
M lldb/tools/lldb-mcp/lldb-mcp.cpp
Log Message:
-----------
[lldb-mcp] Launch lldb on demand, if needed. (#158701)
Adding support for launching lldb with `-O protocol start MCP` if a
valid ~/.lldb/lldb-mcp-*.json` file is not found.
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 371048ef220719a5aa89ba5cf05cc212e659af40
https://github.com/llvm/llvm-project/commit/371048ef220719a5aa89ba5cf05cc212e659af40
Author: Igor Wodiany <igor.wodiany at imgtec.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/docs/Dialects/SPIR-V.md
Log Message:
-----------
[mlir][spirv][nfc] Update documentation to describe the testing strategy (#158962)
Commit: d0c0986387b333589951c29e2b5205d08c67c668
https://github.com/llvm/llvm-project/commit/d0c0986387b333589951c29e2b5205d08c67c668
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/test/python/CMakeLists.txt
Log Message:
-----------
[MLIR][Python] add `not` to `MLIR_PYTHON_TEST_DEPENDS` (#159124)
[lit complains if these aren't
found](https://github.com/llvm/llvm-project/blob/95fc948c0a07953ae9d0973854336e197e36d349/llvm/utils/lit/lit/llvm/config.py#L466-L482)
(even if they're not used by a test...) so make sure to include all of
them in `MLIR_PYTHON_TEST_DEPENDS`.
Commit: 55e6b3260dcb2b2131317516bf63cc81bd9f5bed
https://github.com/llvm/llvm-project/commit/55e6b3260dcb2b2131317516bf63cc81bd9f5bed
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
Log Message:
-----------
[gn build] Port c3fb2e1cee95
Commit: 7bc91f3580836c13cfcf511147585a5f2f00a7f5
https://github.com/llvm/llvm-project/commit/7bc91f3580836c13cfcf511147585a5f2f00a7f5
Author: bd1976bris <Ben.Dunbobbin at sony.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M clang/test/Driver/DTLTO/dtlto.c
M clang/test/Driver/DTLTO/ps5-dtlto.c
Log Message:
-----------
[DTLTO][TEST] XFAIL Clang driver tests for Multicall toolchains (#159129)
Previously I masked issues with Multicall + DTLTO (see #148908) due to
an incomplete understanding of how the Multicall toolchain works.
This patch reverts those incorrect changes and instead marks the
affected tests XFAIL when running under Multicall.
Issue #159125 tracks fixing DTLTO with Multicall.
Commit: 40f2da5c04042dcf6ae8dfc757d31a32da7f329e
https://github.com/llvm/llvm-project/commit/40f2da5c04042dcf6ae8dfc757d31a32da7f329e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Add hasREV8Like helper to RISCVSubtarget. NFC (#158775)
Commit: f209d63b042e3b3455b67ecb08908135dd9d31fe
https://github.com/llvm/llvm-project/commit/f209d63b042e3b3455b67ecb08908135dd9d31fe
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Log Message:
-----------
[SelectionDAGBuilder][PPC] Use getShiftAmountConstant. (#158400)
The PowerPC changes are caused by shifts created by different IR
operations being CSEd now. This allows consecutive loads to be turned
into vectors earlier. This has effects on the ordering of other combines
and legalizations. This leads to some improvements and some regressions.
Commit: 198ea2332584bf838a893522b870e1bf033ce7a4
https://github.com/llvm/llvm-project/commit/198ea2332584bf838a893522b870e1bf033ce7a4
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/CMakeLists.txt
Log Message:
-----------
[CAS] Disable OnDiskCAS build on Solaris (#159122)
OnDiskCAS implementation receives error `No record locks available`
on Solaris. Disable building on Solaris for now to fix buildbot failure.
Commit: b8efe1c64746e832bc3313ec2f6a23f09f2d2dd9
https://github.com/llvm/llvm-project/commit/b8efe1c64746e832bc3313ec2f6a23f09f2d2dd9
Author: Vy Nguyen <vyng at google.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M clang/test/Driver/clang_f_opts.c
Log Message:
-----------
[clang][nfc] Fix tests to avoid writing output to unreachable location (#159138)
Note: this was originally done in (#158698) but was reverted in the
pr/158844 (which re-applied the original rev)
Commit: b76dc2b9ba7d402d1c9909b87322f2b0008ce3a6
https://github.com/llvm/llvm-project/commit/b76dc2b9ba7d402d1c9909b87322f2b0008ce3a6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M libc/src/__support/CPP/simd.h
M libc/src/__support/CPP/type_traits/is_unsigned.h
M libc/src/string/memory_utils/generic/inline_strlen.h
M libc/test/src/__support/CPP/simd_test.cpp
Log Message:
-----------
[libc] Clean up mask helpers after allowing implicit conversions (#158681)
Summary:
I landed a change in clang that allows integral vectors to implicitly
convert to boolean ones. This means I can simplify the interface and
remove the need to cast to bool on every use. Also do some other
cleanups of the traits.
Commit: 0648c5183f3202060862cd6cba8e6f2395052929
https://github.com/llvm/llvm-project/commit/0648c5183f3202060862cd6cba8e6f2395052929
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
Log Message:
-----------
AMDGPU: Fix some broken regclass numbers in mir tests (#159102)
Commit: 9e9edb583400ffc647622445459d700d0ad61b3d
https://github.com/llvm/llvm-project/commit/9e9edb583400ffc647622445459d700d0ad61b3d
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/CAS/OnDiskCommon.cpp
Log Message:
-----------
[CAS] Fix build for older macOS SDK (before 13.0) (#159133)
Fix a build failure and back-deployment problem for macOS before 13.0.
Commit: 3c4ab4fdefcbd34106163899d7e2914246328616
https://github.com/llvm/llvm-project/commit/3c4ab4fdefcbd34106163899d7e2914246328616
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaConvertIntegerTypeToSignless.cpp
M mlir/test/Dialect/Tosa/tosa-convert-integer-type-to-signless.mlir
Log Message:
-----------
[mlir][tosa] Handle unsigned constants in `TosaConvertIntegerTypeToSignless` (#156483)
This commit fixes handling of unsigned constant data in the
`TosaConvertIntegerTypeToSignless` pass. Previously, the type of the
"values" attribute would remain unsigned, which caused an error in the
const ops verifier:
```
error: 'tosa.const' op expected same attr/result element types
%input_zp = "tosa.const"() {values = dense<17> : tensor<1xui8>} : () -> tensor<1xui8>
^
note: see current operation: %0 = "tosa.const"() <{values = dense<17> : tensor<1xui8>}> : () -> tensor<1xi8>
```
Now the constant data in "values" is transformed to signless as well.
Commit: 181979822743ddaf4c197e1587c0c89b5f4240a4
https://github.com/llvm/llvm-project/commit/181979822743ddaf4c197e1587c0c89b5f4240a4
Author: Druzhkov Sergei <serzhdruzhok at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/README.md
M lldb/tools/lldb-dap/package.json
Log Message:
-----------
[lldb-dap] Add stdio redirection (#158609)
As far as I understand, lldb-dap does not currently support stdio
redirection. I have added support for this via a new field in the launch
configuration named `stdio`. It was inspired by the same named field in
[CodeLLDB](https://github.com/vadimcn/codelldb/blob/master/MANUAL.md#stdio-redirection).
Commit: f854009307d3f3750d3358510ef632571683acb5
https://github.com/llvm/llvm-project/commit/f854009307d3f3750d3358510ef632571683acb5
Author: Akhil Goel <akhil.goel at intel.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
Log Message:
-----------
[mlir][arith][NFC] Minor Revisions to Comments (#158757)
This is a minor nitpick PR to fix a few comments.
Commit: 46fd8d0db2f7f7361823efae067edddb6acc237c
https://github.com/llvm/llvm-project/commit/46fd8d0db2f7f7361823efae067edddb6acc237c
Author: Amit Kumar Pandey <pandey.kumaramit2023 at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M compiler-rt/lib/dfsan/dfsan.cpp
M compiler-rt/lib/fuzzer/FuzzerCorpus.h
M compiler-rt/lib/fuzzer/FuzzerDriver.cpp
M compiler-rt/lib/fuzzer/FuzzerLoop.cpp
M compiler-rt/lib/hwasan/hwasan_report.cpp
Log Message:
-----------
Reapply "[NFC] Fix CodeQL violations in compiler-rt. (#157793)" (#157913) (#159097)
Fix below buildbot failure.
```
/var/lib/buildbot/fuchsia-x86_64-linux/llvm-project/compiler-rt/lib/fuzzer/FuzzerDriver.cpp:172:42: error: use of undeclared identifier 'uint'
172 | Printf("Flag: %s %u\n", Name, (uint)Val);
```
Replace uint with uint32_t cast.
This reverts commit 8062b166762b51f1c3a9168e7031babde3e330a8.
Commit: fd59fd563f342c8900b0d6ff5039741cb263b6ed
https://github.com/llvm/llvm-project/commit/fd59fd563f342c8900b0d6ff5039741cb263b6ed
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
[AMDGPU] Add aperture classes to VS_64 (#158823)
Should not do anything.
Commit: 90d96b3e9c90cccefe1c1af75b57de1b8e248c42
https://github.com/llvm/llvm-project/commit/90d96b3e9c90cccefe1c1af75b57de1b8e248c42
Author: Druzhkov Sergei <serzhdruzhok at gmail.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M lldb/tools/lldb-dap/Protocol/ProtocolEvents.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolEvents.h
M lldb/unittests/DAP/ProtocolTypesTest.cpp
Log Message:
-----------
[NFC][lldb-dap] Fix typo in invalidated event (#158338)
Fixed a typo in the `invalidated` event according to
[DAP](https://microsoft.github.io/debug-adapter-protocol/specification#Events_Invalidated)
specification. While the field is `frameId` elsewhere, it must be
`stackFrameId` in this event.
Commit: dd56becdbc31cce16973172f0a447207ddf67861
https://github.com/llvm/llvm-project/commit/dd56becdbc31cce16973172f0a447207ddf67861
Author: Steven Wu <stevenwu at apple.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M llvm/lib/CAS/MappedFileRegionArena.cpp
Log Message:
-----------
[CAS] Fix alignment error from MappedFileRegionArena (#159128)
Fix a bug that when an alignment error can happen when reading a slice
of file from existing MappedFileRegionArena.
Commit: e24f90190c772b6fdd915cd0a2e55cbd468c3024
https://github.com/llvm/llvm-project/commit/e24f90190c772b6fdd915cd0a2e55cbd468c3024
Author: Brad Smith <brad at comstyle.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M clang/lib/Driver/ToolChains/FreeBSD.h
M clang/test/Driver/aarch64-features.c
Log Message:
-----------
[Driver] Enable outline atomics for FreeBSD/aarch64 (#156089)
Commit: f74583fbe8f4aed755a8c0882cb40cd629e0d598
https://github.com/llvm/llvm-project/commit/f74583fbe8f4aed755a8c0882cb40cd629e0d598
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-09-16 (Tue, 16 Sep 2025)
Changed paths:
M offload/plugins-nextgen/common/src/PluginInterface.cpp
Log Message:
-----------
[offload] Fix build with debug libomptarget (#159144)
Currently get this error
```
offload/plugins-nextgen/common/src/PluginInterface.cpp:859:63: error: member reference type 'StringRef' is not a pointer; did you mean to use '.'?
```
We pass the full image binary now so we can't really print anything
useful here.
Seems introduced in https://github.com/llvm/llvm-project/pull/158748.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Co-authored-by: Joseph Huber <huberjn at outlook.com>
Commit: 7779882b4d27c231fbadc718734d5fc44bb44629
https://github.com/llvm/llvm-project/commit/7779882b4d27c231fbadc718734d5fc44bb44629
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-09-17 (Wed, 17 Sep 2025)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll
Log Message:
-----------
[DA] Add option to run only SIV routines (#157084)
This patch introduces a new option, `da-run-siv-routines-only`, which
runs only the SIV family routines in the DA. This is useful for testing
(regression tests, not dependence tests) as it helps detect behavioral
changes in the SIV routines. Actually, regarding the test cases added in
#157085, fixing the incorrect result requires changes across multiple
functions (at a minimum, `exactSIVtest`, `gcdMIVtest` and
`symbolicRDIVtest`). It is difficult to address all of them at once.
This patch also generates the CHECK directives using the new option for
`ExactSIV.ll` as it is necessary for subsequent patches. However, I
believe it will also be useful for other `xxSIV.ll` tests. Notably, the
SIV family routines tend to be affected by other routines, as they are
typically invoked at the beginning of the overall analysis.
Commit: 028ddb1883f7537a720aa2b78017752ac43e0fb4
https://github.com/llvm/llvm-project/commit/028ddb1883f7537a720aa2b78017752ac43e0fb4
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-09-17 (Wed, 17 Sep 2025)
Changed paths:
M clang-tools-extra/clang-include-fixer/IncludeFixer.cpp
M clang-tools-extra/clangd/Compiler.cpp
M clang-tools-extra/include-cleaner/unittests/RecordTest.cpp
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Frontend/CompilerInstance.h
M clang/lib/Driver/ToolChains/FreeBSD.h
M clang/lib/Frontend/ASTUnit.cpp
M clang/lib/Frontend/ChainedIncludesSource.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Frontend/Rewrite/FrontendActions.cpp
M clang/lib/Interpreter/Interpreter.cpp
M clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp
M clang/lib/Testing/TestAST.cpp
M clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/test/Driver/DTLTO/dtlto.c
M clang/test/Driver/DTLTO/ps5-dtlto.c
M clang/test/Driver/aarch64-features.c
M clang/test/Driver/clang_f_opts.c
M clang/tools/clang-import-test/clang-import-test.cpp
M clang/tools/clang-installapi/ClangInstallAPI.cpp
M clang/tools/driver/cc1_main.cpp
M clang/unittests/AST/ExternalASTSourceTest.cpp
M clang/unittests/CodeGen/TestCompiler.h
M clang/unittests/Driver/ToolChainTest.cpp
M clang/unittests/Frontend/CodeGenActionTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M clang/unittests/Frontend/FrontendActionTest.cpp
M clang/unittests/Frontend/OutputStreamTest.cpp
M clang/unittests/Serialization/ForceCheckFileInputTest.cpp
M clang/unittests/Serialization/ModuleCacheTest.cpp
M clang/unittests/Serialization/NoCommentsTest.cpp
M clang/unittests/Serialization/PreambleInNamedModulesTest.cpp
M clang/unittests/Support/TimeProfilerTest.cpp
M clang/unittests/Tooling/DependencyScanning/DependencyScannerTest.cpp
A compiler-rt/cmake/caches/hexagon-builtins-baremetal.cmake
M compiler-rt/lib/dfsan/dfsan.cpp
M compiler-rt/lib/fuzzer/FuzzerCorpus.h
M compiler-rt/lib/fuzzer/FuzzerDriver.cpp
M compiler-rt/lib/fuzzer/FuzzerLoop.cpp
M compiler-rt/lib/hwasan/hwasan_report.cpp
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/parse-tree.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Lower/OpenMP/Utils.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/canonicalize-omp.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/rewrite-parse-tree.cpp
M flang/test/Lower/HLFIR/eoshift.f90
M flang/test/Parser/OpenMP/bind-clause.f90
M flang/test/Parser/OpenMP/declare-reduction-multi.f90
M flang/test/Parser/OpenMP/declare-reduction-unparse.f90
M flang/test/Parser/OpenMP/do-tile-size.f90
M flang/test/Parser/OpenMP/doacross-clause.f90
M flang/test/Parser/OpenMP/if-clause.f90
M flang/test/Parser/OpenMP/in-reduction-clause.f90
M flang/test/Parser/OpenMP/lastprivate-clause.f90
M flang/test/Parser/OpenMP/linear-clause.f90
M flang/test/Parser/OpenMP/loop-transformation-construct01.f90
M flang/test/Parser/OpenMP/loop-transformation-construct02.f90
M flang/test/Parser/OpenMP/loop-transformation-construct03.f90
M flang/test/Parser/OpenMP/masked-unparse.f90
M flang/test/Parser/OpenMP/master-unparse.f90
M flang/test/Parser/OpenMP/order-clause01.f90
M flang/test/Parser/OpenMP/ordered-depend.f90
M flang/test/Parser/OpenMP/reduction-modifier.f90
M flang/test/Parser/OpenMP/target-loop-unparse.f90
M flang/test/Parser/OpenMP/taskloop.f90
M flang/test/Parser/OpenMP/tile-size.f90
M flang/test/Parser/OpenMP/tile.f90
M flang/test/Parser/OpenMP/transparent-clause.f90
M flang/test/Parser/OpenMP/unroll-full.f90
M flang/test/Parser/OpenMP/unroll-heuristic.f90
M flang/test/Parser/OpenMP/unroll-partial.f90
M flang/test/Semantics/OpenMP/simd-only.f90
M libc/src/__support/CPP/simd.h
M libc/src/__support/CPP/type_traits/is_unsigned.h
M libc/src/string/memory_utils/generic/inline_strlen.h
M libc/test/src/__support/CPP/simd_test.cpp
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/source/Commands/CommandObjectTarget.cpp
M lldb/source/Host/common/Socket.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/tools/lldb-dap/Handler/RequestHandler.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolEvents.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolEvents.h
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolRequests.h
M lldb/tools/lldb-dap/README.md
M lldb/tools/lldb-dap/package.json
M lldb/tools/lldb-mcp/lldb-mcp.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M llvm/CMakeLists.txt
M llvm/docs/GarbageCollection.rst
M llvm/include/llvm/ADT/PackedVector.h
M llvm/include/llvm/ADT/STLExtras.h
M llvm/include/llvm/ADT/Statistic.h
M llvm/include/llvm/ADT/Twine.h
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/BasicAliasAnalysis.h
M llvm/include/llvm/Analysis/TypeBasedAliasAnalysis.h
M llvm/include/llvm/IR/IntrinsicsPowerPC.td
M llvm/include/llvm/MC/MCContext.h
M llvm/include/llvm/Support/AMDHSAKernelDescriptor.h
M llvm/include/llvm/Transforms/Utils/DebugSSAUpdater.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CAS/MappedFileRegionArena.cpp
M llvm/lib/CAS/OnDiskCommon.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/COFFMasmParser.cpp
M llvm/lib/MC/MCParser/ELFAsmParser.cpp
M llvm/lib/MC/MCParser/MCAsmParser.cpp
M llvm/lib/MC/MCParser/MCAsmParserExtension.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCParser/WasmAsmParser.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
M llvm/lib/Target/BPF/BPFAsmPrinter.cpp
A llvm/lib/Target/BPF/BPFAsmPrinter.h
M llvm/lib/Target/BPF/BPFISelLowering.cpp
M llvm/lib/Target/BPF/BPFISelLowering.h
M llvm/lib/Target/BPF/BPFInstrInfo.cpp
M llvm/lib/Target/BPF/BPFInstrInfo.h
M llvm/lib/Target/BPF/BPFInstrInfo.td
M llvm/lib/Target/BPF/BPFMCInstLower.cpp
M llvm/lib/Target/BPF/BPFMCInstLower.h
M llvm/lib/Target/BPF/BPFSubtarget.cpp
M llvm/lib/Target/BPF/BPFSubtarget.h
A llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.cpp
A llvm/lib/Target/BPF/BPFTargetLoweringObjectFile.h
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/BPF/CMakeLists.txt
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/CodeGen/AArch64/pr157252.mir
A llvm/test/CodeGen/AArch64/sve2p1-dots-partial-reduction.ll
A llvm/test/CodeGen/AArch64/xor-min-max.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/acc-ldst.ll
M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-snop-padding.mir
M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/imm.ll
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.i8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.xf32.gfx942.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.iterative.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards-mfma-scale.gfx950.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-loop.ll
M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
A llvm/test/CodeGen/BPF/jump_table_blockaddr.ll
A llvm/test/CodeGen/BPF/jump_table_global_var.ll
A llvm/test/CodeGen/BPF/jump_table_switch_stmt.ll
A llvm/test/CodeGen/Hexagon/vsubsat.ll
M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
A llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/X86/avx512-fma.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-vfmac-fadd.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll
M llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc.ll
M llvm/test/CodeGen/X86/dag-combiner-fma-folding.ll
M llvm/test/CodeGen/X86/fma-do-not-commute.ll
M llvm/test/CodeGen/X86/fma_patterns.ll
M llvm/test/CodeGen/X86/fma_patterns_wide.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
A llvm/test/CodeGen/X86/symbol-name.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/ELF/cgprofile.s
M llvm/test/MC/ELF/symbol-names.s
R llvm/test/TableGen/AsmPredicateCondsEmission.td
A llvm/test/TableGen/DecoderEmitter/AsmPredicateCondsEmission.td
A llvm/test/TableGen/DecoderEmitter/DecoderEmitterBitwidthSpecialization.td
A llvm/test/TableGen/DecoderEmitter/DecoderEmitterFnTable.td
A llvm/test/TableGen/DecoderEmitter/VarLenDecoder.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission2.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission3.td
A llvm/test/TableGen/DecoderEmitter/trydecode-emission4.td
R llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td
R llvm/test/TableGen/DecoderEmitterFnTable.td
M llvm/test/TableGen/HwModeEncodeDecode3.td
M llvm/test/TableGen/RegisterEncoder.td
R llvm/test/TableGen/VarLenDecoder.td
R llvm/test/TableGen/trydecode-emission.td
R llvm/test/TableGen/trydecode-emission2.td
R llvm/test/TableGen/trydecode-emission3.td
R llvm/test/TableGen/trydecode-emission4.td
M llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test-vec.ll
M llvm/test/Transforms/InstCombine/is_fpclass.ll
A llvm/test/Transforms/InstCombine/may-alias-errno.ll
A llvm/test/Transforms/InstCombine/redundant-fcmp.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/unittests/ADT/PackedVectorTest.cpp
M llvm/unittests/ADT/STLExtrasTest.cpp
M llvm/utils/TableGen/CodeEmitterGen.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/Target/BPF/BUILD.gn
M mlir/docs/Dialects/SPIR-V.md
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCooperativeMatrixOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVMemoryOps.td
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/GPUToSPIRV/WmmaOpsToSPIRV.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/WinogradConv2D.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaConvertIntegerTypeToSignless.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/GPUToSPIRV/wmma-ops-to-spirv-khr-coop-matrix.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/Tosa/tosa-convert-integer-type-to-signless.mlir
A mlir/test/Target/LLVMIR/openmp-target-default-as.mlir
M mlir/test/python/CMakeLists.txt
M offload/liboffload/src/OffloadImpl.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/JIT.h
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/src/JIT.cpp
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/cuda/src/rtl.cpp
M offload/plugins-nextgen/host/src/rtl.cpp
M offload/test/offloading/force-usm.cpp
Log Message:
-----------
Merge branch 'main' into users/kasuga-fj/da-fix-exact-siv-ovfl-2
Compare: https://github.com/llvm/llvm-project/compare/6a3a5fcb1b0d...028ddb1883f7
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