[all-commits] [llvm/llvm-project] 4ebd20: [LegalizeTypes][X86] Use getShiftAmountConstant in...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4ebd2023291d47402ecd170864df9ea541ea33ba
      https://github.com/llvm/llvm-project/commit/4ebd2023291d47402ecd170864df9ea541ea33ba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-09-12 (Fri, 12 Sep 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp

  Log Message:
  -----------
  [LegalizeTypes][X86] Use getShiftAmountConstant in ExpandIntRes_SIGN_EXTEND. (#158388)

This ensures we don't need to fixup the shift amount later.

Unfortunately, this enabled the
(SRA (SHL X, ShlConst), SraConst) -> (SRA (sext_in_reg X), SraConst -
ShlConst) combine in combineShiftRightArithmetic for some cases in
is_fpclass-fp80.ll. So we need to also update checkSignTestSetCCCombine
to look through sign_extend_inreg to prevent a regression.



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