[all-commits] [llvm/llvm-project] e8eeda: AMDGPU: Relax legal register operand constraint

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/use-getCommonSubClass-isLegalRegOperand
  Home:   https://github.com/llvm/llvm-project
  Commit: e8eeda9f675746825789531249303f605e749135
      https://github.com/llvm/llvm-project/commit/e8eeda9f675746825789531249303f605e749135
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-09-11 (Thu, 11 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/fold-sgpr-copy.mir

  Log Message:
  -----------
  AMDGPU: Relax legal register operand constraint

Find a common subclass instead of directly checking for a subclass
relationship. This fixes folding logic for unaligned register defs
into aligned use contexts. e.g., a vreg_64 def into an av_64_align2
use should be able to find the common subclass vreg_align2. This
avoids regressions in future patches.

Checking the subclass was also redundant on the subregister path;
getMatchingSuperRegClass is sufficient.



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