[all-commits] [llvm/llvm-project] 5fa539: [AMDGPU] Extending wave reduction intrinsics for `...

Aaditya via All-commits all-commits at lists.llvm.org
Wed Sep 10 06:02:18 PDT 2025


  Branch: refs/heads/users/easyonaadit/amdgpu/wave-reduce-intrinsics-bitwise
  Home:   https://github.com/llvm/llvm-project
  Commit: 5fa53924fcf5ad6083185d332349354a6cc074eb
      https://github.com/llvm/llvm-project/commit/5fa53924fcf5ad6083185d332349354a6cc074eb
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll

  Log Message:
  -----------
  [AMDGPU] Extending wave reduction intrinsics for `i64` types - 1

Supporting Min/Max Operations: `min`, `max`, `umin`, `umax`


  Commit: cb7ca6ea8ace1168442bbea35ccdb15f33ae2bb3
      https://github.com/llvm/llvm-project/commit/cb7ca6ea8ace1168442bbea35ccdb15f33ae2bb3
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  Log Message:
  -----------
  Addressing Review Comments


  Commit: 11c9ebc8f57a1a63cb8f94d69d5805d48ce1945a
      https://github.com/llvm/llvm-project/commit/11c9ebc8f57a1a63cb8f94d69d5805d48ce1945a
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll

  Log Message:
  -----------
  Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.


  Commit: 82095acd811c75266e1cee96fadfb153283fb16c
      https://github.com/llvm/llvm-project/commit/82095acd811c75266e1cee96fadfb153283fb16c
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll

  Log Message:
  -----------
  [AMDGPU] Extending wave reduction intrinsics for `i64` types - 2

Supporting Arithemtic Operations: `add`, `sub`


  Commit: bc4afc9ebafb271bffcd03751d2ff8701fa60544
      https://github.com/llvm/llvm-project/commit/bc4afc9ebafb271bffcd03751d2ff8701fa60544
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll

  Log Message:
  -----------
  Marking dead scc


  Commit: 634c7e198fbc093b077232939180e8551a743f41
      https://github.com/llvm/llvm-project/commit/634c7e198fbc093b077232939180e8551a743f41
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll

  Log Message:
  -----------
  Checking for targets with native 64-bit `add`/`sub` support


  Commit: e1760a2867c6420d5d252a966f469d174a4fca69
      https://github.com/llvm/llvm-project/commit/e1760a2867c6420d5d252a966f469d174a4fca69
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll

  Log Message:
  -----------
  [AMDGPU] Extending wave reduction intrinsics for `i64` types - 3

Supporting Arithemtic Operations: `and`, `or`, `xor`


  Commit: 67819a140924caf7364f99cc87956b6f3fbc208c
      https://github.com/llvm/llvm-project/commit/67819a140924caf7364f99cc87956b6f3fbc208c
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll

  Log Message:
  -----------
  Removing Redundant Instructions


  Commit: 4565c046b6baad67dcf4bc870535c949387cfdbb
      https://github.com/llvm/llvm-project/commit/4565c046b6baad67dcf4bc870535c949387cfdbb
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  Log Message:
  -----------
  Removing `break` before `else`


  Commit: 84a7b6a77e2a5930e2f88805a5a36038edebf625
      https://github.com/llvm/llvm-project/commit/84a7b6a77e2a5930e2f88805a5a36038edebf625
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  Log Message:
  -----------
  Running Clang Format


  Commit: 5dc17b147b5d54ff15292dd30141a40adba56c0c
      https://github.com/llvm/llvm-project/commit/5dc17b147b5d54ff15292dd30141a40adba56c0c
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  Log Message:
  -----------
  Directly checking for S_XOR_B32


  Commit: ac6e7ceedbdd4601a88885d6c72bbf405d6da5ce
      https://github.com/llvm/llvm-project/commit/ac6e7ceedbdd4601a88885d6c72bbf405d6da5ce
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2025-09-10 (Wed, 10 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll

  Log Message:
  -----------
  Code Formating


Compare: https://github.com/llvm/llvm-project/compare/3150da45b452...ac6e7ceedbdd

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