[all-commits] [llvm/llvm-project] 698f39: [RISCV] Remove post-decoding instruction adjustmen...

[Sergei Barannikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 698f39bc195905a84fdb696dfaa1cde006f7238f
      https://github.com/llvm/llvm-project/commit/698f39bc195905a84fdb696dfaa1cde006f7238f
  Author: Sergei Barannikov <barannikov88 at gmail.com>
  Date:   2025-09-04 (Thu, 04 Sep 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoC.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXwch.td

  Log Message:
  -----------
  [RISCV] Remove post-decoding instruction adjustments (#156360)

Some instructions implicitly define/use X2 (SP) register, but instead of
being present in the Defs/Uses lists, it is sometimes modeled as an
explicit operand with SP register class.
Since the operand is not encoded into the instruction, it cannot be
disassembled, and we have `RISCVDisassembler::addSPOperands()` that
addresses the issue by mutating the (incompletely) decoded instruction.

This change makes the operand decodable by adding `bits<0>` field for
that operand to relevant instruction encodings and removes
`RISCVDisassembler::addSPOperands()`.



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