[all-commits] [llvm/llvm-project] 81035c: [clang-format] Allow short function body on a sing...
Congcong Cai via All-commits
all-commits at lists.llvm.org
Thu Sep 4 07:15:28 PDT 2025
Branch: refs/heads/users/ccc/clang-tidy/query-check
Home: https://github.com/llvm/llvm-project
Commit: 81035c31cd7d0f65ef650474c0d585131f958bda
https://github.com/llvm/llvm-project/commit/81035c31cd7d0f65ef650474c0d585131f958bda
Author: 闫立栋 <yldhome2d2 at gmail.com>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M clang/lib/Format/UnwrappedLineFormatter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Allow short function body on a single line (#151428)
Fix #145161
Commit: c168ce20f51cbc6b094aa1c75dc01efd42c4031f
https://github.com/llvm/llvm-project/commit/c168ce20f51cbc6b094aa1c75dc01efd42c4031f
Author: Mircea Trofin <mtrofin at google.com>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M llvm/lib/Analysis/DevelopmentModeInlineAdvisor.cpp
Log Message:
-----------
[mlgo] Fix bad merge of #156120 with 0082cf41de11 (#156134)
Commit: 3e6ec475b756559560cba4a16c2bc755aa8caee5
https://github.com/llvm/llvm-project/commit/3e6ec475b756559560cba4a16c2bc755aa8caee5
Author: David Tenty <daltenty at ibm.com>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M llvm/cmake/modules/GetHostTriple.cmake
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
M llvm/tools/lto/CMakeLists.txt
Log Message:
-----------
[CMake][AIX] quote the string AIX `if` conditions
This is a follow on to #154537, which quoted the CMAKE_SYSTEM_NAME to avoid expanding it again when that CMAKE_SYSTEM_NAME expands to AIX.
But by the same logic, we also need to quote the plain string AIX as well.
Commit: cc5e8967ab1ae04ccbb6a8678dcd4ef0d5c5ccdf
https://github.com/llvm/llvm-project/commit/cc5e8967ab1ae04ccbb6a8678dcd4ef0d5c5ccdf
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/docs/CodeGenerator.rst
M llvm/include/llvm/Target/Target.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/EvergreenInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/R600Instructions.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPDInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/PowerPC/PPCInstrVSX.td
M llvm/lib/Target/PowerPC/README_P9.txt
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/VE/VEInstrInfo.td
M llvm/lib/Target/VE/VEInstrVec.td
M llvm/utils/TableGen/CodeEmitterGen.cpp
M llvm/utils/TableGen/Common/CodeGenInstruction.cpp
M llvm/utils/TableGen/Common/CodeGenInstruction.h
Log Message:
-----------
[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)
I believe it became no-op with the removal of the "positionally encoded
operands" functionality (b87dc356 is the last commit in the series).
There are no changes in the generated files.
Commit: 35a3ae3137800c14f63fb76c3dd4d429546269f6
https://github.com/llvm/llvm-project/commit/35a3ae3137800c14f63fb76c3dd4d429546269f6
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/EvergreenInstructions.td
Log Message:
-----------
Remove an unused field (follow up to cc5e8967)
Commit: 4880940c8474d5ea996a24a6bebe557283e9f2e1
https://github.com/llvm/llvm-project/commit/4880940c8474d5ea996a24a6bebe557283e9f2e1
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
A mlir/test/Dialect/GPU/broadcast-speculatability.mlir
M mlir/test/Dialect/GPU/int-range-interface.mlir
M mlir/test/Dialect/GPU/ops.mlir
Log Message:
-----------
[mlir][gpu] Add `subgroup_broadcast` op (#152808)
`subgroup_broadcast` allow to broadcast the value from one lane to all
lanes in subgroup.
Supported modes:
* `first_active_lane` - broadcast value from the first active lane in
subgroup.
* `specific_lane` - broadcast value from the specified lane, lane index
must be within subgroup.
* `any_lane` - if `src` value is uniform across all the subgroup lanes
return it unchanged, otherwise result is poison. This variant
essentially an uniformity hint for the compiler, conveying that specific
value is uniform across all subgroup lanes. Dropping `any_lane`
broadcast should not change the code semantics.
Commit: 257975fada8bb40f729976a9caa06d2bbb4e9f12
https://github.com/llvm/llvm-project/commit/257975fada8bb40f729976a9caa06d2bbb4e9f12
Author: Denzel-Brian Budii <73462654+chios202 at users.noreply.github.com>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M mlir/include/mlir/Query/Matcher/SliceMatchers.h
Log Message:
-----------
[mlir] Fix node numbering order in SliceMatchers example (#155684)
After reviewing this again, it looks like I missed some nodes. Node 7
uses node 1 and 5 as well.
Commit: 4d21f664db63a30e331696a28b9c340a2f059997
https://github.com/llvm/llvm-project/commit/4d21f664db63a30e331696a28b9c340a2f059997
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
Be smarter about the GLIBCXX_USE_CXX11_ABI default (#155781)
It appears that unconditionally using GLIBCXX_USE_CXX11_ABI=0 is slow on
modern libstdc++, while using GLIBCXX_USE_CXX11_ABI=1 breaks old
buildbots, so use the compiler default unless asked to do differently.
Commit: e68d66a1afea79d19f8b3f9b8bea6b4ff38685b7
https://github.com/llvm/llvm-project/commit/e68d66a1afea79d19f8b3f9b8bea6b4ff38685b7
Author: dong jianqiang <dongjianqiang2 at huawei.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M compiler-rt/lib/builtins/crtbegin.c
Log Message:
-----------
[compiler-rt] Make __EH_FRAME_LIST__ const to avoid RW .eh_frame mapping (#155764) (#155955)
In crtbegin.c, `__EH_FRAME_LIST__` was previously declared as a writable
array of pointers. This caused the linker to place .eh_frame into a
segment with read-write permissions, leading to larger virtual memory
footprint at runtime (e.g. .eh_frame mapped into both LOAD and RELRO).
Changing it to `static void * const __EH_FRAME_LIST__[]` ensures that
the section is treated as read-only, matching GCC’s behavior with
`__EH_FRAME_BEGIN__`. This prevents unnecessary RW mappings of .eh_frame
while preserving the intended semantics.
Fixes: #155764
Commit: aa491fceb696255372485ab53a1ec73ee3198fcf
https://github.com/llvm/llvm-project/commit/aa491fceb696255372485ab53a1ec73ee3198fcf
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/xop-builtins.c
Log Message:
-----------
[X86] Add constexpr handling for XOP/AVX512 rotate by immediate intrinsics (#156047)
Commit: fe6b611d58c8fd0b3ab82d3e083787d10fb32acd
https://github.com/llvm/llvm-project/commit/fe6b611d58c8fd0b3ab82d3e083787d10fb32acd
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
Log Message:
-----------
[RISCV] Unaligned vec mem => prefer alt opc vec
Return `true` in `RISCVTTIImpl::preferAlternateOpcodeVectorization` if
subtarget supports unaligned memory accesses.
Commit: 3aae4bd13dc4dd2e983b1fa11e1b8c0bf153ed14
https://github.com/llvm/llvm-project/commit/3aae4bd13dc4dd2e983b1fa11e1b8c0bf153ed14
Author: Laxman Sole <laxmansole at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h
A llvm/test/DebugInfo/debug-bool-const-location.ll
Log Message:
-----------
Emit DW_OP_lit0/1 for constant boolean values (#155539)
Backends like NVPTX use -1 to indicate `true` and 0 to indicate `false`
for boolean values. Machine instruction `#DBG_VALUE` also uses -1 to
indicate a `true` boolean constant.
However, during the DWARF generation, booleans are treated as unsigned
variables, and the debug_loc expression, like `DW_OP_lit0; DW_OP_not` is
emitted for the `true` value.
This leads to the debugger printing `255` instead of `true` for constant
boolean variables.
This change emits `DW_OP_lit1` instead of `DW_OP_lot0; DW_OP_not`.
Commit: 247da3c80fad21f8b40d796900673e9bd3ed00f5
https://github.com/llvm/llvm-project/commit/247da3c80fad21f8b40d796900673e9bd3ed00f5
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M clang-tools-extra/clang-tidy/.clang-tidy
M clang-tools-extra/clang-tidy/readability/UppercaseLiteralSuffixCheck.cpp
Log Message:
-----------
[clang-tidy][NFC] Enable 'readability-redundant-declaration' check in clang-tidy config (#156164)
Closes https://github.com/llvm/llvm-project/issues/156163
Commit: 1b37b9e6d788d7058381b68b5ab265bcb6181335
https://github.com/llvm/llvm-project/commit/1b37b9e6d788d7058381b68b5ab265bcb6181335
Author: Shashi Shankar <shashishankar1687 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
A llvm/test/CodeGen/AArch64/bti-ehpad.ll
M llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
A llvm/test/CodeGen/AArch64/wineh-bti-funclet.ll
M llvm/test/CodeGen/AArch64/wineh-bti.ll
Log Message:
-----------
[AArch64][BTI] Add BTI at EH entries. (#155308)
Mark EH landing pads as indirect-branch targets (BTI j) and treat WinEH
funclet entries as call-like (BTI c). Add lit tests for ELF and COFF.
Tests:
Adds lit tests: bti-ehpad.ll and wineh-bti-funclet.ll.
Fixes: #149267
Signed-off-by: Shashi Shankar <shashishankar1687 at gmail.com>
Commit: 101216dfdd88a716bfe2bf734e7c94c8fe227f1d
https://github.com/llvm/llvm-project/commit/101216dfdd88a716bfe2bf734e7c94c8fe227f1d
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h
R llvm/test/DebugInfo/debug-bool-const-location.ll
Log Message:
-----------
Revert "Emit DW_OP_lit0/1 for constant boolean values" (#156172)
Reverts llvm/llvm-project#155539
Failing on buildbots with:
```
Step 7 (test-build-stage1-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: DebugInfo/debug-bool-const-location.ll' FAILED ********************
Exit Code: 1
Command Output (stderr):
--
/home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/build/stage1/bin/llc /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm-project/llvm/test/DebugInfo/debug-bool-const-location.ll -O3 -filetype=obj -o - | /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/build/stage1/bin/llvm-dwarfdump - | /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/build/stage1/bin/FileCheck /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm-project/llvm/test/DebugInfo/debug-bool-const-location.ll # RUN: at line 2
+ /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/build/stage1/bin/llc /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm-project/llvm/test/DebugInfo/debug-bool-const-location.ll -O3 -filetype=obj -o -
+ /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/build/stage1/bin/llvm-dwarfdump -
+ /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/build/stage1/bin/FileCheck /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm-project/llvm/test/DebugInfo/debug-bool-const-location.ll
/home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm-project/llvm/test/DebugInfo/debug-bool-const-location.ll:7:10: error: CHECK: expected string not found in input
; CHECK: {{.*}} DW_OP_lit0
^
<stdin>:27:54: note: scanning from here
[0x0000000000000018, 0x0000000000000020): DW_OP_lit1, DW_OP_stack_value
^
<stdin>:28:41: note: possible intended match here
[0x0000000000000020, 0x0000000000000034): DW_OP_reg3 X3)
^
Input file: <stdin>
Check file: /home/buildbots/llvm-external-buildbots/workers/ppc64le-lld-multistage-test/ppc64le-lld-multistage-test/llvm-project/llvm/test/DebugInfo/debug-bool-const-location.ll
-dump-input=help explains the following input dump.
Input was:
<<<<<<
.
.
.
22: DW_AT_decl_line (5)
23: DW_AT_external (true)
24:
25: 0x0000003f: DW_TAG_variable
26: DW_AT_location (0x00000000:
27: [0x0000000000000018, 0x0000000000000020): DW_OP_lit1, DW_OP_stack_value
check:7'0 X~~~~~~~~~~~~~~~~~~~ error: no match found
28: [0x0000000000000020, 0x0000000000000034): DW_OP_reg3 X3)
check:7'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
check:7'1 ? possible intended match
29: DW_AT_name ("arg")
check:7'0 ~~~~~~~~~~~~~~~~~~~~
30: DW_AT_decl_file ("test")
check:7'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~
31: DW_AT_decl_line (5)
check:7'0 ~~~~~~~~~~~~~~~~~~~~~
32: DW_AT_type (0x0000004f "bool")
check:7'0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
33:
check:7'0 ~
.
```
Commit: 912ce2631ff397660236a7dc35247f390b1d7818
https://github.com/llvm/llvm-project/commit/912ce2631ff397660236a7dc35247f390b1d7818
Author: Roman <gameroman.official at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M clang/test/AST/HLSL/RootSignatures-AST.hlsl
M clang/test/Modules/safe_buffers_optout.cpp
M lldb/include/lldb/Target/CoreFileMemoryRanges.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Transforms/Utils/IRNormalizer.cpp
M mlir/lib/Bindings/Python/IRAttributes.cpp
M mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir
M mlir/tools/mlir-tblgen/EnumsGen.cpp
Log Message:
-----------
[NFC] Fix typos 'seperate' -> 'separate' (#144368)
Correct few typos: 'seperate' -> 'separate' .
Commit: cacab8a86fc2c6107cf7e9edb746f9634a6aa97a
https://github.com/llvm/llvm-project/commit/cacab8a86fc2c6107cf7e9edb746f9634a6aa97a
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen][Decoder] Simplify parseFixedLenOperands (NFCI) (#156181)
Use information from CGIOperandList instead of re-parsing operand dags
from scratch.
Commit: 62ff9ac4c68f48c089528105259c68943ab176de
https://github.com/llvm/llvm-project/commit/62ff9ac4c68f48c089528105259c68943ab176de
Author: Michael Kruse <llvm-project at meinersbur.de>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M openmp/runtime/src/CMakeLists.txt
Log Message:
-----------
[OpenMP] Use Clang resource dir only in bootstrapping build (#156018)
In an LLVM_ENABLE_PROJECTS=openmp build, the LLVM build tree in which
just-built Clang is available, but in contrast to an
LLVM_ENABLE_RUNTIMES=openmp build, is not the compiler that openmp is
built with (CMAKE_CXX_COMPILER). The latter compiler (which might also
be gcc) will not look into the resource directory of just-built Clang,
where the OpenMP headers are installed. There may not even be a
just-built Clang without LLVM_ENABLE_PROJECTS=clang.
We cannot add the OpenMP header output directory to the search path
which also include's Clang's internal headers that will conflict with
CMAKE_CXX_COMPILER's internal headers. The only choice left is to use
what the OpenMP standalone build does: Use CMAKE_CURRENT_BINARY_DIR
which is added unconditionally to the header search path to compile
openmp itself.
Commit: 1bbac057f6de10db683e70c8c966809ad576b93e
https://github.com/llvm/llvm-project/commit/1bbac057f6de10db683e70c8c966809ad576b93e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/c.c
Log Message:
-----------
[clang][bytecode] Fix ignoring comparisons in C (#156180)
Our comparison ops always return bool, and we do the pop before the
conversion to in in C.
Fixes #156178
Commit: 981f25a8a8623ff89e3c48e36fd94f2e58b7b8c0
https://github.com/llvm/llvm-project/commit/981f25a8a8623ff89e3c48e36fd94f2e58b7b8c0
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/ARM/ARMInstrFormats.td
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrNEON.td
M llvm/lib/Target/ARM/ARMInstrThumb.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/Lanai/LanaiInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.h
Log Message:
-----------
[TableGen] Require complex operands in InstAlias to be specified as DAGs (#136411)
Currently, complex operands of an instruction are flattened in the resulting DAG of `InstAlias`.
This change makes it required to specify complex operands in `InstAlias` as sub-DAGs:
```
InstAlias<"foo $rd, $rs1, $rs2", (Inst RC:$rd, (ComplexOp RC:$rs1, GR0, 42), SimpleOp:$rs2)>;
```
instead of
```
InstAlias<"foo $rd, $rs1, $rs2", (Inst RC:$rd, RC:$rs1, GR0, 42, SimpleOp:$rs2)>;
```
The advantages of the new syntax are improved readability and more robust type checking, although it is a bit more verbose.
Commit: 5a33bc54228456780c29a935775e16d1bd8723c3
https://github.com/llvm/llvm-project/commit/5a33bc54228456780c29a935775e16d1bd8723c3
Author: XChy <xxs_chy at outlook.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-vpmadd52.ll
Log Message:
-----------
[X86] Fold vpmadd52h/l for pattern X * 0 + Y --> Y (#156086)
Resolves comment in
https://github.com/llvm/llvm-project/pull/155494#issuecomment-3227735091
Commit: e78ac808d586ae0df8cba2394f2bc04ed61d03f9
https://github.com/llvm/llvm-project/commit/e78ac808d586ae0df8cba2394f2bc04ed61d03f9
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Implement VAArgExpr for ComplexType (#156092)
This change adds support VAArgExpr for ComplexExpr
Issue: https://github.com/llvm/llvm-project/issues/141365
Commit: f6157c71ab645f7db8564193d33690e28a9839eb
https://github.com/llvm/llvm-project/commit/f6157c71ab645f7db8564193d33690e28a9839eb
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/include/llvm/ADT/StringMap.h
Log Message:
-----------
[ADT] Remove a meaningless std::move (NFC) (#156138)
std::move on StringRef is not useful because it's copied anyway.
Commit: d2fda70afc77f37f99936d5257989b5367033f07
https://github.com/llvm/llvm-project/commit/d2fda70afc77f37f99936d5257989b5367033f07
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Log Message:
-----------
[AArch64] Remove an unnecessary cast (NFC) (#156139)
getOpcode() already returns unsigned.
Commit: 1dd7a09272c11dea5bfcd26c7844dd30ba3249ed
https://github.com/llvm/llvm-project/commit/1dd7a09272c11dea5bfcd26c7844dd30ba3249ed
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/docs/BigEndianNEON.rst
Log Message:
-----------
[llvm] Proofread BigEndianNEON.rst (#156141)
Commit: 1948aa12f536cec56eed8559126af77a191a0aaf
https://github.com/llvm/llvm-project/commit/1948aa12f536cec56eed8559126af77a191a0aaf
Author: Matthias Springer <me at m-sp.org>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
Log Message:
-----------
[flang] Do not use dialect conversion in `AffineDialectPromotion` (#156171)
This pass uses the rewriter API incorrectly: it calls
`replaceAllUsesWith`. This will start failing with #155244.
Instead of a dialect conversion, use the walk-patterns driver, which is
also more efficient.
Commit: 47ddd941a9de4068d4cfa63c41e1978f439c862b
https://github.com/llvm/llvm-project/commit/47ddd941a9de4068d4cfa63c41e1978f439c862b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M mlir/lib/Dialect/Shard/Interfaces/ShardingInterface.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for performance-unnecessary-value-param in ShardingInterface.cpp (NFC)
Commit: 5d74c045eddc1ba00846ce6ef7df3584d439b007
https://github.com/llvm/llvm-project/commit/5d74c045eddc1ba00846ce6ef7df3584d439b007
Author: dyung <douglas.yung at sony.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M clang/test/AST/ByteCode/vectors.cpp
Log Message:
-----------
Fixup test added in #155573 to work when the compiler defaults to C++20. (#156166)
The test added in #155573 assumes the compiler defaults to the current
default of C++17. If the compiler is changed to default to C++20, the
test fails because the expected warnings about a construct being a C++20
extension are no longer emitted. This change fixes up the test to work
in either C++17 or C++20 mode by disabling the warning and removing the
check for it as this is not what is being tested here.
Commit: 494079416080717fba23461f7208f2eae7bd4fb1
https://github.com/llvm/llvm-project/commit/494079416080717fba23461f7208f2eae7bd4fb1
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in Partition.cpp (NFC)
Commit: 2af45d3d6e28ae610e32c46b98980437e5dc39ec
https://github.com/llvm/llvm-project/commit/2af45d3d6e28ae610e32c46b98980437e5dc39ec
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/BufferViewFlowOpInterfaceImpl.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for performance-unnecessary-value-param in BufferViewFlowOpInterfaceImpl.cpp (NFC)
Commit: 91dd13b3497783c82e226c1d6f98965dbc2aba65
https://github.com/llvm/llvm-project/commit/91dd13b3497783c82e226c1d6f98965dbc2aba65
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for performance-move-const-arg in SPIRVTypes.cpp (NFC)
Commit: d39772cb053c194ef809f3ca765f37237c4e1956
https://github.com/llvm/llvm-project/commit/d39772cb053c194ef809f3ca765f37237c4e1956
Author: Abdullah Mohammad Amin <abdullahmohammad155 at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M lldb/include/lldb/Core/Disassembler.h
M lldb/source/Core/Disassembler.cpp
Log Message:
-----------
[lldb] Refactor variable annotation logic in Disassembler::PrintInstructions (#156118)
This patch is a follow-up to
[#152887](https://github.com/llvm/llvm-project/pull/152887), addressing
review comments that came in after the original change was merged.
- Move `VarState` definition out of `PrintInstructions` into a private
helper, with member comments placed before fields.
- Introduce a `VariableAnnotator` helper class to encapsulate state and
logic for live variable tracking across instructions.
- Replace `seen_this_inst` flag with a map-diff approach: recompute the
current variable set per instruction and diff against the previous set.
- Use `nullptr` instead of an empty `ProcessSP` when calling
`ABI::FindPlugin`.
- Narrow `Block*` scope with `if (Block *B = ...)`.
- Set `DIDumpOptions::PrintRegisterOnly` directly from
`static_cast<bool>(abi_sp)`.
- Prefer `emplace_back` over `push_back` for event strings.
- General cleanup to match LLVM coding style and reviewer feedback.
This makes the annotation code easier to read and consistent with
LLVM/LLDB conventions while preserving functionality.
Commit: 2824b3c00efe79873bc1cbe8181c8c65da134996
https://github.com/llvm/llvm-project/commit/2824b3c00efe79873bc1cbe8181c8c65da134996
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll
Log Message:
-----------
[SLP] Try to recalculate deps only for nodes with previously valid deps
Need to recalculate the dependencies only for nodes, which have valid
deps before they gets cleared because of the copyable nodes. Otherwise,
no need to recaculate the dependencies to prevent a crash.
Commit: 6dfd8d0ab46e64d0c30d2b9c60f212b50171fc9d
https://github.com/llvm/llvm-project/commit/6dfd8d0ab46e64d0c30d2b9c60f212b50171fc9d
Author: Thurston Dang <thurston at google.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/Windows/heaprealloc_alloc_zero.cpp
Log Message:
-----------
[asan] Rewrite Windows/heaprealloc_alloc_zero check to avoid dereference (#156211)
The test currently checks that 1-byte is allocated when malloc(0) is
called, by dereferencing the pointer.
https://github.com/llvm/llvm-project/pull/155943 changed ASan to
consider the dereference to be a heap buffer overflow. This patch
changes the test to check the allocated size is still 1-byte, but not
dereference the pointer.
This aims to fix the breakage reported in
https://github.com/llvm/llvm-project/pull/155943#issuecomment-3239543505
It also enables the test for 64-bit Windows.
Commit: fc925ed067acf8afcf2d7f86183260ed856b6734
https://github.com/llvm/llvm-project/commit/fc925ed067acf8afcf2d7f86183260ed856b6734
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
Log Message:
-----------
[CodeGen] Remove a dead assignment (NFC) (#156202)
TRI is set to the same value a couple of lines below.
Commit: 1956941cee24e30addc0dc121891b6577dbddba0
https://github.com/llvm/llvm-project/commit/1956941cee24e30addc0dc121891b6577dbddba0
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMBlockPlacement.cpp
Log Message:
-----------
[ARM] Remove an unnecessary cast (NFC) (#156203)
getInstrInfo() already returns const ARMBaseInstrInfo *.
Commit: 0a16d1a754c247199ee2a77feaea7a94a60f8dfd
https://github.com/llvm/llvm-project/commit/0a16d1a754c247199ee2a77feaea7a94a60f8dfd
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M mlir/CMakeLists.txt
M mlir/examples/standalone/CMakeLists.txt
M mlir/examples/standalone/python/CMakeLists.txt
M mlir/test/Examples/standalone/test.toy
Log Message:
-----------
[MLIR][Python] fix standalone example/test (#156197)
Fix some things in `standalone` in order to unblock
https://github.com/llvm/llvm-project/pull/155741.
Commit: eb39605192d36806ec0d41c8c54b0817be5d80c5
https://github.com/llvm/llvm-project/commit/eb39605192d36806ec0d41c8c54b0817be5d80c5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/no-schedule-terminate-inst.ll
Log Message:
-----------
[SLP]Do not schedule terminate copyable from main op basic block
If the copyable instruction is a terminate instruction from the same
block, as the potential main instruction, such instruction cannot be
copyable and the value list cannot be modeled as instructions with same
(and copyables) opcodes.
Fixes #155183
Commit: 31c9198ea0f9651b8d18548d4a4bff252680f804
https://github.com/llvm/llvm-project/commit/31c9198ea0f9651b8d18548d4a4bff252680f804
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
Log Message:
-----------
[RISCV] Add test coverage for reassociation with poison generating flags
The 'add' case is correct, the 'or' case is coverage for an upcoming
change to fix a bug w.r.t flag preservation.
Commit: f3f717bbfa61600703b3b2149ebdb87fbee2dbac
https://github.com/llvm/llvm-project/commit/f3f717bbfa61600703b3b2149ebdb87fbee2dbac
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
Log Message:
-----------
[RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191)
This node reads the lower 32 bits, shifts it right arithmetically
then sign extends to i64. If we know some of the lower 32 bits we
can propagate that information.
For the test case I had to find something that didn't get optimized
before type legalizaton and didn't get type legalized to a sign
extended value. The bswap gets type legalized to (lshr (bswap), 32).
Commit: 1d8fdda7b0a9f47c443600bca6af2bc141e4abf7
https://github.com/llvm/llvm-project/commit/1d8fdda7b0a9f47c443600bca6af2bc141e4abf7
Author: Michał Górny <mgorny at gentoo.org>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M openmp/tools/omptest/CMakeLists.txt
Log Message:
-----------
[openmp] Fix missing include directory in omptest tool (#156194)
Add missing `LIBOMP_INCLUDE_DIR` include directory to fix build failures
in omptest, as reported
in
https://github.com/llvm/llvm-project/pull/154786#issuecomment-3223481804.
Thanks fo @jprotze for the suggested fix.
Signed-off-by: Michał Górny <mgorny at gentoo.org>
Commit: 4a6435397ba587022ecafa772cd504b8659da2fb
https://github.com/llvm/llvm-project/commit/4a6435397ba587022ecafa772cd504b8659da2fb
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-08-30 (Sat, 30 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
M llvm/test/CodeGen/X86/pr67333.ll
Log Message:
-----------
[SelectionDAG] Add computeKnownBits for ISD::ROTL/ROTR. (#156142)
Commit: 06d758537d4c6db8857deeb0de53786767233492
https://github.com/llvm/llvm-project/commit/06d758537d4c6db8857deeb0de53786767233492
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Target/ARC/ARCInstrFormats.td
M llvm/lib/Target/ARC/ARCInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/Lanai/LanaiInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen][Decoder] Remove special case of single sub-op dag (#156175)
If a custom operand has MIOperandInfo with >= 2 sub-operands, it is
required that either the operand or its sub-operands have a decoder
method (depending on usage). Require this for single sub-operand
operands as well, since there is no good reason not to.
There are no changes in the generated files.
Commit: bfc841108211f3739591b1583913ebe78c7cfd92
https://github.com/llvm/llvm-project/commit/bfc841108211f3739591b1583913ebe78c7cfd92
Author: Hirofumi Nakamura <k.nakamura.hirofumi at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTestTableGen.cpp
Log Message:
-----------
[clang-format] Fix TableGen nested DAGArg format (#155837)
Fixes https://github.com/llvm/llvm-project/issues/154634.
Allow inserting space before DAGArg's opener paren when nested.
Commit: c5f0b8bf327ac86b5beafeeadaf5278afb707545
https://github.com/llvm/llvm-project/commit/c5f0b8bf327ac86b5beafeeadaf5278afb707545
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/switch_create.ll
Log Message:
-----------
[SimplifyCFG] Support trunc nuw in chain of comparisons. (#155087)
proof: https://alive2.llvm.org/ce/z/5PNCds
Commit: b161e8d7dff06d8fb410de897f1a3f0c561ec509
https://github.com/llvm/llvm-project/commit/b161e8d7dff06d8fb410de897f1a3f0c561ec509
Author: flovent <flbven at protonmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/container-size-empty.cpp
Log Message:
-----------
[clang-tidy] Ignore default ctor with user provided argument in `readability-container-size-empty` (#154782)
Closes #154762
Commit: 9bb9206d8e50ffcc6e1d6f18b577a1603429358c
https://github.com/llvm/llvm-project/commit/9bb9206d8e50ffcc6e1d6f18b577a1603429358c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-container-size-empty in VectorTransforms.cpp (NFC)
Commit: 731f4d904cea958423dccb9dc427278a98615994
https://github.com/llvm/llvm-project/commit/731f4d904cea958423dccb9dc427278a98615994
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in TensorOps.cpp (NFC)
Commit: 917f078adb3ffab4cf50aec3e13c977c092d7754
https://github.com/llvm/llvm-project/commit/917f078adb3ffab4cf50aec3e13c977c092d7754
Author: xin liu <navy.xliu at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Transforms/remove-dead-values.mlir
Log Message:
-----------
[mlir][Transforms] Allow RemoveDeadValues to process a function whose the last block is not the exit. (#156123)
'processFuncOp' queries the number of returned values of a function
using the terminator of the last block's getNumOperands(). It presumes
the last block is the exit. It is not always the case.
This patch fixes the bug by querying from FunctionInterfaceOp directly.
Commit: 2b4fff6521c26697e81adf99ad6dca2676d53a5d
https://github.com/llvm/llvm-project/commit/2b4fff6521c26697e81adf99ad6dca2676d53a5d
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/Thumb2/abds-crash.ll
Log Message:
-----------
[TargetLowering] Only freeze LHS and RHS if they are used multiple times in expandABD (#156193)
Not all paths in expandABD are using LHS and RHS twice.
Commit: b369237c98906891f9e56fd4be4109a25b79e3e9
https://github.com/llvm/llvm-project/commit/b369237c98906891f9e56fd4be4109a25b79e3e9
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for bugprone-argument-comment in ArmSMEToSCF.cpp (NFC)
Commit: 63d9e3c114756a3b892d4352313c6dff48b6d560
https://github.com/llvm/llvm-project/commit/63d9e3c114756a3b892d4352313c6dff48b6d560
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Log Message:
-----------
[NFC][ARM][MC] Rearrange decoder functions 2/N (#155464)
Move some of the non-static-decode functions to the end of the file.
Note: moving `ARMDisassembler::AddThumbPredicate` the same way causes
the diff to be non-trivial, so not doing that here.
Commit: 865f9566c383eede4e55d73924fda2ade917324a
https://github.com/llvm/llvm-project/commit/865f9566c383eede4e55d73924fda2ade917324a
Author: Kajetan Puchalski <kajetan.puchalski at arm.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_vector_1op.ll
Log Message:
-----------
[AArch64][SDAG] Add f16 -> i16 rounding NEON conversion intrinsics (#155851)
Add dedicated .i16.f16 formats for rounding NEON conversion intrinsics
in order to avoid issues with incorrect overflow behaviour caused by
using .i32.f16 formats to perform the same conversions.
Added intrinsic formats:
i16 @llvm.aarch64.neon.fcvtzs.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtzu.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtas.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtau.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtms.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtmu.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtns.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtnu.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtps.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtpu.i16.f16(half)
Backend side of the solution to
https://github.com/llvm/llvm-project/issues/154343
---------
Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Commit: 1f2d461e26c4c7fdad922b1b62f2aced58844ce1
https://github.com/llvm/llvm-project/commit/1f2d461e26c4c7fdad922b1b62f2aced58844ce1
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][MC][DecoderEmitter] Simplify loop to find the best filter (#156237)
We can just use `max_element` on the array of filters.
Commit: c6b340e5603dc1dee12f91b930836f78f97e7c31
https://github.com/llvm/llvm-project/commit/c6b340e5603dc1dee12f91b930836f78f97e7c31
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Emit remarks for vectorization decision before execute (NFCI).
Move the emission of remarks for the vectorization decision before
executing the plan, in preparation for
https://github.com/llvm/llvm-project/pull/154510.
Commit: ff77c73d5dabf9bffb245ee236945c984bdbc900
https://github.com/llvm/llvm-project/commit/ff77c73d5dabf9bffb245ee236945c984bdbc900
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-simplify-boolean-expr in LowerContractToNeonPatterns.cpp (NFC)
Commit: 86c4ef506d96468d3f4c196a61767c40ce180d2e
https://github.com/llvm/llvm-project/commit/86c4ef506d96468d3f4c196a61767c40ce180d2e
Author: David Green <david.green at arm.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-index-const-step-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-imm.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
Log Message:
-----------
[AArch64] Add patterns for sub from add negative immediates (#156024)
`sub 3` will be canonicalized in llvm to `add -3`. This adds some
tablegen patterns for add from a negative immediate so that we can still
generate sub imm SVE instructions.
The alternative is to add a isel combine, which seemed to work but
created problems for mad and index patterns. This version does still
need to add a lower-than-default Complexity to the ComplexPatterns to
ensure that index was selected over sub-imm + index, as the default
Complexity on ComplexPatterns is quite high.
Fixes #155928
Commit: 0aac22758a81a98d9612ed1ad4853d9e434e8451
https://github.com/llvm/llvm-project/commit/0aac22758a81a98d9612ed1ad4853d9e434e8451
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
Log Message:
-----------
[LV] Correctly cost chains of replicating calls in legacy CM.
Check for scalarized calls in needsExtract to fix a divergence between
legacy and VPlan-based cost model.
The legacy cost model was missing a check for scalarized calls in
needsExtract, which meant if incorrectly assumed the result of a
scalarized call needs extracting.
Exposed by https://github.com/llvm/llvm-project/pull/154617.
Fixes https://github.com/llvm/llvm-project/issues/156091.
Commit: 04b0658453d6e22a227c2678fe89c52049d1308d
https://github.com/llvm/llvm-project/commit/04b0658453d6e22a227c2678fe89c52049d1308d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
Log Message:
-----------
[mlir] Fix warnings
This patch fixes:
mlir/lib/Dialect/Tensor/IR/TensorOps.cpp:3205:13: error: unused
function 'printInferType' [-Werror,-Wunused-function]
mlir/lib/Dialect/Tensor/IR/TensorOps.cpp:3210:1: error: unused
function 'parseInferType' [-Werror,-Wunused-function]
Commit: e3512fb39b55febba8d24e86704f0c9977d60568
https://github.com/llvm/llvm-project/commit/e3512fb39b55febba8d24e86704f0c9977d60568
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/docs/BranchWeightMetadata.rst
Log Message:
-----------
[llvm] Proofread LangRef.rst (#156204)
Commit: 34fbf1f0b79750f69d391cf9f778d8bca2ca5f05
https://github.com/llvm/llvm-project/commit/34fbf1f0b79750f69d391cf9f778d8bca2ca5f05
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/include/llvm/ProfileData/MemProfYAML.h
M llvm/test/tools/llvm-profdata/memprof-yaml.test
Log Message:
-----------
[memprof] Make the AllocSites and CallSites sections optional in YAML (#156226)
This patch makes the AllocSites and CallSites sections optional in the
YAML format. This is useful for situations where a function has only
one section.
Commit: 2259a80c7d6d27879f4ecac31bafaf2cff778430
https://github.com/llvm/llvm-project/commit/2259a80c7d6d27879f4ecac31bafaf2cff778430
Author: AZero13 <gfunni234 at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
Log Message:
-----------
[ARM] Simplify LowerCMP (NFC) (#156198)
Pass the opcode directly.
Commit: 9f620b8f62c4a0bdbf066c6f86ff9f38a6acd932
https://github.com/llvm/llvm-project/commit/9f620b8f62c4a0bdbf066c6f86ff9f38a6acd932
Author: Seraphimt <svet58585 at mail.ru>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Log Message:
-----------
[InstCombine] Slightly optimize visitFcmp (NFC) (#156097)
Studying the code related to float found a slightly optimal sequence of
actions.
Commit: d63dd5eed0ea2f34bcf8b178211f8771ea75dec7
https://github.com/llvm/llvm-project/commit/d63dd5eed0ea2f34bcf8b178211f8771ea75dec7
Author: bursow <75187874+bursow at users.noreply.github.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M clang/test/CodeGen/X86/avx512cd-builtins.c
M clang/test/CodeGen/X86/avx512vlcd-builtins.c
Log Message:
-----------
feat: Add AVX512 support for constant interpreter test (#156227)
Adds test coverage for `fexperimental-new-constant-interpreter` to
`avx512cd-builtins.c` and `avx512vlcd-builtins.c` as part of the work to
ensure all x86 intrinsics are handled correctly by the new interpreter.
Part of #155814.
Commit: e5a4ea20c5b6b37f7fd944b5ef7395d0623d4bdb
https://github.com/llvm/llvm-project/commit/e5a4ea20c5b6b37f7fd944b5ef7395d0623d4bdb
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/RISCV/reduced-copyable-element.ll
Log Message:
-----------
[SLP]Do not remove reduced value, if it is a copyable
If the value is checked for the reduction and it is a copyable element
in a root node, it should not be deleted, since it may still be used
after vectorization.
Fixes #155512
Commit: b1d2c627b175778321cf3aea3aa5a1c5d922a2b5
https://github.com/llvm/llvm-project/commit/b1d2c627b175778321cf3aea3aa5a1c5d922a2b5
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Unconditionally run attachRuntimeChecks (NFCI).
Instead of conditionally executing attachRuntimeChecks, directly check
if the blocks to be added are still disconnected.
Commit: 7730ebce8e8fa84db4da04a7d8fe1977ccbf28ff
https://github.com/llvm/llvm-project/commit/7730ebce8e8fa84db4da04a7d8fe1977ccbf28ff
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/revectorize-phis.ll
Log Message:
-----------
[SLP]Do not to try to revectorize previously vectorized phis in loops
No need to try to revectorize previously vectorized phis in loops, it leads to
a compile time blow-up.
Fixes #155998
Commit: b062aad57a4191330e692f385125f9e9292b9033
https://github.com/llvm/llvm-project/commit/b062aad57a4191330e692f385125f9e9292b9033
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
Log Message:
-----------
[CodeGen] Drop disjoint flag when reassociating (#156218)
This fixes a latent miscompile. To understand why the flag can't be
preserved, consider the case where a0=0, a1=0, a2=-1, and s3=-1.
Commit: c65d6cb0a1f2dad03c8f11891b5bacb51180c490
https://github.com/llvm/llvm-project/commit/c65d6cb0a1f2dad03c8f11891b5bacb51180c490
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[SelectionDAG] Return std::optional<unsigned> from getValidShiftAmount and friends. NFC (#156224)
Instead of std::optional<uint64_t>. Shift amounts must be less than or
equal to our maximum supported bit widths which fit in unsigned. Most of
the callers already assumed it fit in unsigned.
Commit: 13aff91e7c1c11055792d7126930d43acb2d514f
https://github.com/llvm/llvm-project/commit/13aff91e7c1c11055792d7126930d43acb2d514f
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll
Log Message:
-----------
Revert "[VPlan] Support plans with vector pointers in narrowInterleaveGroups."
This reverts commit 806a797c52d8018639f5cdcce5eb375b17c87f5e as it
introduced a miscompile.
Commit: a6e6487048097dff09ae764c678e9adc8d1d6263
https://github.com/llvm/llvm-project/commit/a6e6487048097dff09ae764c678e9adc8d1d6263
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
M llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
Log Message:
-----------
[Mips][XCore] Use MCRegisterClass::getRegister() instead of begin()+RegNo. NFC
Commit: 6332e2bac8810b24349ef04d91b5567d14b1117e
https://github.com/llvm/llvm-project/commit/6332e2bac8810b24349ef04d91b5567d14b1117e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Tools/mlir-reduce/MlirReduceMain.cpp
Log Message:
-----------
[MLIR] Add --allow-unregistered-dialect to mlir-reduce (#156245)
Fixes #155544
Commit: 465b17c45007b3030f918098cc801f065508e732
https://github.com/llvm/llvm-project/commit/465b17c45007b3030f918098cc801f065508e732
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
Log Message:
-----------
[VPlan] Support scalable VFs in narrowInterleaveGroups. (#154842)
Update narrowInterleaveGroups to support scalable VFs. After the
transform, the vector loop will process a single iteration of the
original vector loop for fixed-width vectors and vscale iterations for
scalable vectors.
Commit: a5fe4e44800c4e2772ca2c3a07f36692ff32e57d
https://github.com/llvm/llvm-project/commit/a5fe4e44800c4e2772ca2c3a07f36692ff32e57d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/Detail/Var.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in Var.cpp (NFC)
Commit: 0bdb915f9aa5128532a819b09d29a75ee0d6297a
https://github.com/llvm/llvm-project/commit/0bdb915f9aa5128532a819b09d29a75ee0d6297a
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-else-after-return in OpenMPToLLVMIRTranslation.cpp (NFC)
Commit: eef79c8b49aa45458bbaf895603385a7819cc182
https://github.com/llvm/llvm-project/commit/eef79c8b49aa45458bbaf895603385a7819cc182
Author: Muhammad Omair Javaid <omair.javaid at linaro.org>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M lldb/test/API/python_api/basename/TestGetBaseName.py
Log Message:
-----------
[lldb][test] Mark TestGetBaseName.py as expected failure on Windows
TestGetBaseName.py introduced in PR #155939 is failing on windows
LLDB bots. This patch adds @expectedFailureAll(oslist=["windows"])
decorator to mark it as an expected failure on Windows to make
buildbots green while the underlying issue is investigated.
(see: https://lab.llvm.org/buildbot/#/builders/141/builds/11176).
Commit: 5109361d4aeeb0227e86a7f016eb773d28dd9957
https://github.com/llvm/llvm-project/commit/5109361d4aeeb0227e86a7f016eb773d28dd9957
Author: Owen Pan <owenpiano at gmail.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M polly/lib/External/CMakeLists.txt
Log Message:
-----------
[polly][CMake] Replace `elseif ()` with `else ()`
The no-argument elseif resulted in the warning below:
CMake Warning (dev) at polly/lib/External/CMakeLists.txt:30 (elseif):
ELSEIF called with no arguments, it will be skipped.
Commit: a49030e493b76bc2b294d36709c7ed84aef557f4
https://github.com/llvm/llvm-project/commit/a49030e493b76bc2b294d36709c7ed84aef557f4
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M clang-tools-extra/clang-tidy/readability/UppercaseLiteralSuffixCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/stdfloat
M clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-c23.c
A clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-cxx23.cpp
R clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-float16.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point-opencl-half.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-hexadecimal-floating-point.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-custom-list.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-ms.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer.cpp
Log Message:
-----------
[clang-tidy] Teach `readability-uppercase-literal-suffix` about C++23 and C23 suffixes (#148275)
Clang doesn't actually support any of the new floating point types yet
(except for `f16`). I've decided to add disabled tests for them, so that
when the support comes, we can flip the switch and support them with no
delay.
Commit: 2e122990391b2ba062e6308a12cfedf7206270ba
https://github.com/llvm/llvm-project/commit/2e122990391b2ba062e6308a12cfedf7206270ba
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/test/Driver/cl-options.c
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/Target/TargetLoweringObjectFile.cpp
M llvm/test/Transforms/SampleProfile/pseudo-probe-callee-profile-mismatch.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-dangle2.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-desc-guid.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-instsched.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-invoke.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-missing-probe.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-no-debug-info.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-peep.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch-error.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch-thinlto.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-slotindex.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-matching-LCS.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-matching-lto.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-matching.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-renaming-recursive.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-renaming.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-toplev-func.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-verify.ll
Log Message:
-----------
[PseudoProbe] Support emitting to COFF object (#123870)
RFC:
https://discourse.llvm.org/t/rfc-support-pseudo-probe-for-windows-coff/83820
Support emitting pseudo probe to .pseudo_probe and .pseudo_probe_desc
COFF sections.
Commit: e57f0e928d7b92f536a646d8ba1c26916b09e67e
https://github.com/llvm/llvm-project/commit/e57f0e928d7b92f536a646d8ba1c26916b09e67e
Author: Wu Yingcong <yingcong.wu at intel.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M libunwind/src/DwarfParser.hpp
A libunwind/test/eh_frame_fde_pc_range.pass.cpp
Log Message:
-----------
[libunwind] fix pc range condition check bug (#154902)
There is an off-by-one error with current condition check for PC fallen
into the range or not. There is another check within libunwind that use
the correct checks in
https://github.com/llvm/llvm-project/blob/5050da7ba18fc876f80fbeaaca3564d3b4483bb8/libunwind/src/UnwindCursor.hpp#L2757
```
if ((fdeInfo.pcStart <= pc) && (pc < fdeInfo.pcEnd))
```
Commit: a428b3081a1aa73e3fddb70127ba3e0fb85d6e3d
https://github.com/llvm/llvm-project/commit/a428b3081a1aa73e3fddb70127ba3e0fb85d6e3d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M clang-tools-extra/clang-tidy/fuchsia/MultipleInheritanceCheck.cpp
M clang/lib/Driver/OffloadBundler.cpp
M llvm/include/llvm/ADT/StringMap.h
M llvm/unittests/ADT/StringMapTest.cpp
Log Message:
-----------
[ADT] Refactor StringMap iterators (NFC) (#156137)
StringMap has four iterator classes:
- StringMapIterBase
- StringMapIterator
- StringMapConstIterator
- StringMapKeyIterator
This patch consolidates the first three into one class, namely
StringMapIterBase, adds a boolean template parameter to indicate
desired constness, and then use "using" directives to specialize the
common class:
using const_iterator = StringMapIterBase<ValueTy, true>;
using iterator = StringMapIterBase<ValueTy, false>;
just like how we simplified DenseMapIterator.
Remarks:
- This patch drops CRTP and iterator_facade_base for simplicity. For
fairly simple forward iterators, iterator_facade_base doesn't buy us
much. We just have to write a few "using" directives and operator!=
manually.
- StringMapIterBase has a SFINAE-based constructor to construct a
const iterator from a non-const one just like DenseMapIterator.
- We now rely on compiler-generated copy and assignment operators.
Commit: 3c822ea7a8e276792905858e8780500f45cda589
https://github.com/llvm/llvm-project/commit/3c822ea7a8e276792905858e8780500f45cda589
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/include/llvm/ADT/PointerEmbeddedInt.h
Log Message:
-----------
[ADT] Remove Mask in PointerEmbedded (#156201)
Mask, a private enum, isn't used anywhere in the class.
Commit: 2ff7a4ccc9e72e99a32683248709300498480082
https://github.com/llvm/llvm-project/commit/2ff7a4ccc9e72e99a32683248709300498480082
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
Log Message:
-----------
[RISCV][NFC] Simplify some rvv regbankselect cases (#155961)
Commit: a247da4f9363116c54b91a37755edd994c56dbf8
https://github.com/llvm/llvm-project/commit/a247da4f9363116c54b91a37755edd994c56dbf8
Author: Wenju He <wenju.he at intel.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M libclc/clc/include/clc/mem_fence/clc_mem_fence.h
A libclc/clc/include/clc/mem_fence/clc_mem_semantic.h
M libclc/clc/include/clc/synchronization/clc_work_group_barrier.h
M libclc/clc/lib/amdgcn/mem_fence/clc_mem_fence.cl
M libclc/clc/lib/amdgcn/synchronization/clc_work_group_barrier.cl
M libclc/clc/lib/ptx-nvidiacl/mem_fence/clc_mem_fence.cl
M libclc/clc/lib/ptx-nvidiacl/synchronization/clc_work_group_barrier.cl
M libclc/opencl/include/clc/opencl/synchronization/utils.h
M libclc/opencl/lib/amdgcn/mem_fence/fence.cl
M libclc/opencl/lib/amdgcn/synchronization/barrier.cl
M libclc/opencl/lib/ptx-nvidiacl/mem_fence/fence.cl
M libclc/opencl/lib/ptx-nvidiacl/synchronization/barrier.cl
Log Message:
-----------
[libclc] update __clc_mem_fence: add MemorySemantic arg and use __builtin_amdgcn_fence for AMDGPU (#152275)
It is necessary to add MemorySemantic argument for AMDGPU which means
the memory or address space to which the memory ordering is applied.
The MemorySemantic is also necessary for implementing the SPIR-V
MemoryBarrier instruction. Additionally, the implementation of
__clc_mem_fence on Intel GPUs requires the MemorySemantic argument.
Using __builtin_amdgcn_fence for AMDGPU is follow-up of
https://github.com/llvm/llvm-project/pull/151446#discussion_r2254006508
llvm-diff shows no change to nvptx64--nvidiacl.bc.
Commit: 0b42e117c829c6e127ef4b1bd82807ba01853128
https://github.com/llvm/llvm-project/commit/0b42e117c829c6e127ef4b1bd82807ba01853128
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Exclude some more tests
These tests are currently showing up as red on the buildbot. We have not
gotten to any of these passes yet, so add them to the exclude list for now.
Commit: 2e7ea9c94504ddb45f8215e2e2bad4a875617648
https://github.com/llvm/llvm-project/commit/2e7ea9c94504ddb45f8215e2e2bad4a875617648
Author: Tony Varghese <tonypalampalliyil at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
Log Message:
-----------
[PowerPC] Exploit xxeval instruction for operations of the form ternary(A,X,B) and ternary(A,X,C). (#152956)
Adds support for ternary equivalent operations of the form `ternary(A,
X, B)` and `ternary(A, X, C)` where `X=[and(B,C)| nor(B,C)| eqv(B,C)|
nand(B,C)]`.
The following are the patterns involved and the imm values:
| **Operation** | **Immediate Value** |
|----------------------------|---------------------|
| ternary(A, and(B,C), B) | 49 |
| ternary(A, nor(B,C), B) | 56 |
| ternary(A, eqv(B,C), B) | 57 |
| ternary(A, nand(B,C), B) | 62 |
| | |
| ternary(A, and(B,C), C) | 81 |
| ternary(A, nor(B,C), C) | 88 |
| ternary(A, eqv(B,C), C) | 89 |
| ternary(A, nand(B,C), C) | 94 |
eg. `xxeval XT, XA, XB, XC, 49`
- performs `XA ? and(XB, XC) : B`and places the result in `XT`.
This is the continuation of [[PowerPC] Exploit xxeval instruction for
ternary patterns - ternary(A, X,
and(B,C))](https://github.com/llvm/llvm-project/pull/141733#top).
---------
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
Commit: 3fc1aad65bc38d964b81091e57b1bcb3d56b8a3c
https://github.com/llvm/llvm-project/commit/3fc1aad65bc38d964b81091e57b1bcb3d56b8a3c
Author: Tony Varghese <tonypalampalliyil at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
A llvm/test/CodeGen/PowerPC/vsro-vsr-vsrq-dag-combine.ll
Log Message:
-----------
[PowerPC] Merge vsr(vsro(input, byte_shift), bit_shift) to vsrq(input, res_bit_shift) (#154388)
This change implements a patfrag based pattern matching ~dag combiner~
that combines consecutive `VSRO (Vector Shift Right Octet)` and `VSR
(Vector Shift Right)` instructions into a single `VSRQ (Vector Shift
Right Quadword)` instruction on Power10+ processors.
Vector right shift operations like `vec_srl(vec_sro(input, byte_shift),
bit_shift)` generate two separate instructions `(VSRO + VSR)` when they
could be optimised into a single `VSRQ `instruction that performs the
equivalent operation.
```
vsr(vsro (input, vsro_byte_shift), vsr_bit_shift) to vsrq(input, vsrq_bit_shift)
where vsrq_bit_shift = (vsro_byte_shift * 8) + vsr_bit_shift
```
Note:
```
vsro : Vector Shift Right by Octet VX-form
- vsro VRT, VRA, VRB
- The contents of VSR[VRA+32] are shifted right by the number of bytes specified in bits 121:124 of VSR[VRB+32].
- Bytes shifted out of byte 15 are lost.
- Zeros are supplied to the vacated bytes on the left.
- The result is placed into VSR[VRT+32].
vsr : Vector Shift Right VX-form
- vsr VRT, VRA, VRB
- The contents of VSR[VRA+32] are shifted right by the number of bits specified in bits 125:127 of VSR[VRB+32]. 3 bits.
- Bits shifted out of bit 127 are lost.
- Zeros are supplied to the vacated bits on the left.
- The result is place into VSR[VRT+32], except if, for any byte element in VSR[VRB+32], the low-order 3 bits are not equal to the shift amount, then VSR[VRT+32] is undefined.
vsrq : Vector Shift Right Quadword VX-form
- vsrq VRT,VRA,VRB
- Let src1 be the contents of VSR[VRA+32]. Let src2 be the contents of VSR[VRB+32].
- src1 is shifted right by the number of bits specified in the low-order 7 bits of src2.
- Bits shifted out the least-significant bit are lost.
- Zeros are supplied to the vacated bits on the left.
- The result is placed into VSR[VRT+32].
```
---------
Co-authored-by: Tony Varghese <tony.varghese at ibm.com>
Commit: 09350bd1c5ebba6cae96afcb70ef8ac097f7e1de
https://github.com/llvm/llvm-project/commit/09350bd1c5ebba6cae96afcb70ef8ac097f7e1de
Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/CodeGen/PowerPC/check-zero-vector.ll
Log Message:
-----------
[NFC][PowerPC] adding the arguments for register names and VSR to VR (#155991)
NFC patch to add the flags `-ppc-asm-full-reg-names
--ppc-vsr-nums-as-vr` to the test file
`llvm/test/CodeGen/PowerPC/check-zero-vector.ll`.
Created this PR based on this discussion:
https://github.com/llvm/llvm-project/pull/151971#issuecomment-3234090675
Co-authored-by: himadhith <himadhith.v at ibm.com>
Co-authored-by: Lei Huang <lei at ca.ibm.com>
Commit: 0fb1b56b2c2092d14317a7a886c316d987c1088f
https://github.com/llvm/llvm-project/commit/0fb1b56b2c2092d14317a7a886c316d987c1088f
Author: Jim Lin <jim at andestech.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/attributes-thead.ll
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Split the attribute test for THead to attributes-thead.ll. NFC.
Commit: 64b98967542d0128457154080f91c1ec4283eecb
https://github.com/llvm/llvm-project/commit/64b98967542d0128457154080f91c1ec4283eecb
Author: Amara Emerson <amara at apple.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/test/CodeGen/ARM/stack-guard-nomovt.ll
Log Message:
-----------
[ARM] Use t2LDRLIT_ga_pcrel for loading stack guards with no-movt in PIC mode. (#156208)
When using no-movt we don't use the pcrel version of the literal load.
This change also unifies logic with the ARM version of this function as
well,
which has:
```
if (!Subtarget.useMovt() || ForceELFGOTPIC) {
// For ELF non-PIC, use GOT PIC code sequence as well because R_ARM_GOT_ABS
// does not have assembler support.
if (TM.isPositionIndependent() || ForceELFGOTPIC)
expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
else
expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
return;
}
```
rdar://138334512
Commit: a50b096798ca0e186439b427390424c26add5713
https://github.com/llvm/llvm-project/commit/a50b096798ca0e186439b427390424c26add5713
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/test/Dialect/EmitC/form-expressions.mlir
Log Message:
-----------
[mlir][emitc] Only mark operator with fundamental type have no side effect (#144990)
Commit: 0ea54be66bd7333a80ec49d2b95e09c15391c7b0
https://github.com/llvm/llvm-project/commit/0ea54be66bd7333a80ec49d2b95e09c15391c7b0
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/include/llvm/ADT/BitVector.h
Log Message:
-----------
[ADT] Mark BitVector::find_prev_unset const (NFC) (#156272)
find_prev_unset calls find_last_unset_in, a const method, but
find_prev_unset itself isn't marked const.
Commit: bed3c7e74251d463ce724fae329ae106967e4728
https://github.com/llvm/llvm-project/commit/bed3c7e74251d463ce724fae329ae106967e4728
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/include/llvm/ADT/BitVector.h
Log Message:
-----------
[ADT] Remove BitVector::next_unset_in_word (#156273)
This patch removes BitVector::next_unset_in_word as the private method
doesn't seem to be used anywhere.
Commit: 100180fb536121aa012ed16778630bdc45b5f30c
https://github.com/llvm/llvm-project/commit/100180fb536121aa012ed16778630bdc45b5f30c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M llvm/docs/CMake.rst
Log Message:
-----------
[llvm] Proofread CMake.rst (#156276)
Commit: c9faedd760c5ec3e76241cc488d4db729bb75f86
https://github.com/llvm/llvm-project/commit/c9faedd760c5ec3e76241cc488d4db729bb75f86
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call-scalarize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr154103.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Log Message:
-----------
[VPlan] Fold common edges away in convertPhisToBlends (#150368)
If a phi is widened with tail folding, all of its predecessors will have
a mask of the form
%x = logical-and %active-lane-mask, %foo
%y = logical-and %active-lane-mask, %bar
%z = logical-and %active-lane-mask, %baz
...
We can remove the common %active-lane-mask from all of these edge masks,
which in turn allows us to simplify a lot of VPBlendRecipes.
In particular, it allows the header mask to be removed in selects with
EVL tail folding, improving RISC-V codegen on SPEC CPU 2017 for
525.x264_r, and supersedes #147243.
This also allows us to remove VPBlendRecipe and directly emit
VPInstruction::Select in another patch.
Commit: 46dc8ef2d3eebb6f588354d442ce4c07d46e9ea3
https://github.com/llvm/llvm-project/commit/46dc8ef2d3eebb6f588354d442ce4c07d46e9ea3
Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/xqciac.ll
M llvm/test/MC/RISCV/xqciac-valid.s
Log Message:
-----------
[RISCV] Compress shxadd to qc.c.muliadd when rd = rs2 (#155843)
Do this when Zba and Xqciac are both enabled.
Commit: 17d9ca8aa4e5487ccfdc7a18fed7217b366a42ae
https://github.com/llvm/llvm-project/commit/17d9ca8aa4e5487ccfdc7a18fed7217b366a42ae
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in mlir-linalg-ods-yaml-gen.cpp (NFC)
Commit: 80f418303fbf1f37909d6c5ab0f330f63b013a85
https://github.com/llvm/llvm-project/commit/80f418303fbf1f37909d6c5ab0f330f63b013a85
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-identifier-naming in LowerContractToSVEPatterns.cpp (NFC)
Commit: 31f0ab06e3ae95802db78056b7395497b8c876da
https://github.com/llvm/llvm-project/commit/31f0ab06e3ae95802db78056b7395497b8c876da
Author: hev <wangrui at loongson.cn>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
M llvm/test/CodeGen/LoongArch/lasx/bswap.ll
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
M llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll
M llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
M llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
M llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll
M llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
M llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
M llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
M llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
M llvm/test/CodeGen/LoongArch/lasx/mulh.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll
M llvm/test/CodeGen/LoongArch/lasx/vselect.ll
M llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
M llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
M llvm/test/CodeGen/LoongArch/lsx/bswap.ll
M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll
M llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
M llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
M llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll
M llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
M llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
M llvm/test/CodeGen/LoongArch/lsx/mulh.ll
M llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
M llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
M llvm/test/CodeGen/LoongArch/lsx/vselect.ll
Log Message:
-----------
[LoongArch] Enable vector tests for 32-bit target (#152094)
Commit: af41d0d7057d8365c7b48ce9f88d80b669057993
https://github.com/llvm/llvm-project/commit/af41d0d7057d8365c7b48ce9f88d80b669057993
Author: hev <wangrui at loongson.cn>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/bittest.ll
M llvm/test/CodeGen/LoongArch/select-const.ll
Log Message:
-----------
[LoongArch] Perform SELECT_CC combine (#155994)
Fold `((srl (and X, 1<<C), C), 0, eq/ne)` -> `((shl X, GRLen-1-C), 0, ge/lt)`
Commit: a987022f33a27610732544b0c5f4475ce818c982
https://github.com/llvm/llvm-project/commit/a987022f33a27610732544b0c5f4475ce818c982
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/MemoryBuiltins.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
Log Message:
-----------
[MemoryBuiltins] Add getBaseObjectSize() (NFCI) (#155911)
getObjectSize() is based on ObjectSizeOffsetVisitor, which has become
very expensive over time. The implementation is geared towards computing
as-good-as-possible results for the objectsize intrinsics and similar.
However, we also use it in BasicAA, which is very hot, and really only
cares about the base cases like alloca/malloc/global, not any of the
analysis for GEPs, phis, or loads.
Add a new getBaseObjectSize() API for this use case, which only handles
the non-recursive cases. As a bonus, this API can easily return a
TypeSize and thus support scalable vectors. For now, I'm explicitly
discarding the scalable sizes in BasicAA just to avoid unnecessary
behavior changes during this refactor.
Commit: 4d9578b8ed20f293641a5917447885ab97aeefbe
https://github.com/llvm/llvm-project/commit/4d9578b8ed20f293641a5917447885ab97aeefbe
Author: Vladimir Vuksanovic <109677816+vvuksanovic at users.noreply.github.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang-tools-extra/clang-reorder-fields/CMakeLists.txt
A clang-tools-extra/clang-reorder-fields/Designator.cpp
A clang-tools-extra/clang-reorder-fields/Designator.h
M clang-tools-extra/clang-reorder-fields/ReorderFieldsAction.cpp
A clang-tools-extra/test/clang-reorder-fields/AggregatePartialInitialization.c
M clang-tools-extra/test/clang-reorder-fields/AggregatePartialInitialization.cpp
A clang-tools-extra/test/clang-reorder-fields/DesignatedInitializerList.c
A clang-tools-extra/test/clang-reorder-fields/DesignatedInitializerList.cpp
A clang-tools-extra/test/clang-reorder-fields/IdiomaticZeroInitializer.c
A clang-tools-extra/test/clang-reorder-fields/InitializerListExcessElements.c
Log Message:
-----------
[clang-reorder-fields] Support designated initializers (#142150)
Initializer lists with designators, missing elements or omitted braces
can now be rewritten. Any missing designators are added and they get
sorted according to the new order.
```
struct Foo {
int a;
int b;
int c;
};
struct Foo foo = { .a = 1, 2, 3 }
```
when reordering elements to "b,a,c" becomes:
```
struct Foo {
int b;
int a;
int c;
};
struct Foo foo = { .b = 2, .a = 1, .c = 3 }
```
Commit: 01a135106bd49214d7f0a172566222d74d5543a7
https://github.com/llvm/llvm-project/commit/01a135106bd49214d7f0a172566222d74d5543a7
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
M llvm/test/Transforms/RelLookupTableConverter/X86/relative_lookup_table.ll
Log Message:
-----------
[RelLookupTableConverter] Make GEP type independent (#155404)
This makes the RelLookupTableConverter independent of the type used in
the GEP. In particular, it removes the requirement to have a leading
zero index.
Commit: e82abde49454d0bd2c2d37b6209e1d21fbcbaa56
https://github.com/llvm/llvm-project/commit/e82abde49454d0bd2c2d37b6209e1d21fbcbaa56
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Refactor `if`s into `&&` (#156278)
Commit: 055bfc027141bbfafd51fb43f5ab81ba3b480649
https://github.com/llvm/llvm-project/commit/055bfc027141bbfafd51fb43f5ab81ba3b480649
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/union-tbaa1.c
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll
M llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
M llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll
M llvm/test/Transforms/InstCombine/canonicalize-gep-constglob.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/cast_phi.ll
M llvm/test/Transforms/InstCombine/gep-addrspace.ll
M llvm/test/Transforms/InstCombine/gep-alias.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/load-bitcast-select.ll
M llvm/test/Transforms/InstCombine/load-cmp.ll
M llvm/test/Transforms/InstCombine/loadstore-alignment.ll
M llvm/test/Transforms/InstCombine/mem-gep-zidx.ll
M llvm/test/Transforms/InstCombine/memchr-11.ll
M llvm/test/Transforms/InstCombine/memcmp-8.ll
M llvm/test/Transforms/InstCombine/memcpy-addrspace.ll
M llvm/test/Transforms/InstCombine/memcpy-from-global.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/pr58901.ll
M llvm/test/Transforms/InstCombine/ptrtoint-nullgep.ll
M llvm/test/Transforms/InstCombine/remove-loop-phi-multiply-by-zero.ll
M llvm/test/Transforms/InstCombine/strcmp-3.ll
M llvm/test/Transforms/InstCombine/strlen-1.ll
M llvm/test/Transforms/InstCombine/strlen-4.ll
M llvm/test/Transforms/InstCombine/strlen-7.ll
M llvm/test/Transforms/InstCombine/strlen-8.ll
M llvm/test/Transforms/InstCombine/strlen-9.ll
M llvm/test/Transforms/InstCombine/strnlen-3.ll
M llvm/test/Transforms/InstCombine/strnlen-4.ll
M llvm/test/Transforms/InstCombine/strnlen-5.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
M llvm/test/Transforms/InstCombine/wcslen-1.ll
M llvm/test/Transforms/InstCombine/wcslen-3.ll
M llvm/test/Transforms/InstCombine/wcslen-5.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
M llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll
M llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
M llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
M llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll
M llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
M llvm/test/Transforms/PhaseOrdering/single-iteration-loop-sroa.ll
M llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
Log Message:
-----------
[InstCombine] Strip leading zero indices from GEP (#155415)
GEPs are often in the form `gep [N x %T], ptr %p, i64 0, i64 %idx`.
Canonicalize these to `gep %T, ptr %p, i64 %idx`.
This enables transforms that only support one GEP index to work and
improves CSE.
Various transforms were recently hardened to make sure they still work
without the leading index.
Commit: c128b8c46f2a3b750c9abcba1e303f92d6531e5f
https://github.com/llvm/llvm-project/commit/c128b8c46f2a3b750c9abcba1e303f92d6531e5f
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang-tools-extra/clang-reorder-fields/Designator.cpp
M clang-tools-extra/clang-reorder-fields/Designator.h
Log Message:
-----------
[clang-reorder-fields] Fix unused private field warning (NFC)
Fixes:
```
In file included from /home/gha/actions-runner/_work/llvm-project/llvm-project/clang-tools-extra/clang-reorder-fields/Designator.cpp:15:
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang-tools-extra/clang-reorder-fields/Designator.h:157:23: error: private field 'ILE' is not used [-Werror,-Wunused-private-field]
157 | const InitListExpr *ILE;
```
Commit: 0a193cb6876314ae906902261032c3fbe2b84328
https://github.com/llvm/llvm-project/commit/0a193cb6876314ae906902261032c3fbe2b84328
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Use IsaPred to improve code (NFC) (#156037)
Commit: 9ad8e12c573f248b3f0ca4cca01fee1e5ed22c7b
https://github.com/llvm/llvm-project/commit/9ad8e12c573f248b3f0ca4cca01fee1e5ed22c7b
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/test/CodeGen/AMDGPU/gfx1250-no-scope-cu-stores.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
A llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll
Log Message:
-----------
[AMDGPU] Expand scratch atomics to flat atomics if GAS is enabled (#154710)
Commit: c8d7a73cf1a62f99c2a5a41487ad39c074154bb7
https://github.com/llvm/llvm-project/commit/c8d7a73cf1a62f99c2a5a41487ad39c074154bb7
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Improve code around operands-iterator (NFC) (#156016)
Commit: 24bc5665bcb3ebfaf3b0ff0d1e1d7dd654a9d98d
https://github.com/llvm/llvm-project/commit/24bc5665bcb3ebfaf3b0ff0d1e1d7dd654a9d98d
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/test/Transforms/Coroutines/coro-split-dbg.ll
Log Message:
-----------
[Coroutines] Remove assert about a promise being present (#156007)
This commit removes an assert in the generation of debug info for a
coroutine frame. This assert checked if a promise alloca is present,
even though it's not used. While this might always be the case when the
coroutine was produced by clang++, this doesn't hold in the general
case.
Note: We generate coroutine intrinsics from downstream passes. In our
case, there is no guarantee that a coroutine has any promise, but they
can originate from some non-coro C++ code.
Commit: 3cac3329e16e0642f13a689a2db5c3fbf28dfc89
https://github.com/llvm/llvm-project/commit/3cac3329e16e0642f13a689a2db5c3fbf28dfc89
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
A llvm/test/Transforms/Coroutines/coro-split-dbg-labels-inlined.ll
Log Message:
-----------
[Coroutines] Enhance DILabel generation with support for inlined locs (#155989)
This commit fixes an issue in the generation of DILabels. The previous
code did not cover cases where the suspend intrinsic had an inlined
location. Because of this, it took an incorrect DIScope, that broke an
internal pre-condition of `DIBuilder::insertLabel`.
This has been addressed by taking the DIScope of the "inlined at"
location, which should be the DISubprogram of the function holding the
label.
Commit: 38268ecab94b90a2eea6c62c5911679d93954651
https://github.com/llvm/llvm-project/commit/38268ecab94b90a2eea6c62c5911679d93954651
Author: Liu Ke <liuke.gehry at bytedance.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/MakeSmartPtrCheck.cpp
M clang-tools-extra/clang-tidy/modernize/MakeSmartPtrCheck.h
M clang-tools-extra/test/clang-tidy/checkers/modernize/make-shared.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/make-unique.cpp
Log Message:
-----------
[clang-tidy] Support direct initialization in modernize smart pointer (#154732)
Support for direct initialization detection in modernize smart pointer checks.
Commit: 1debf23d7a3393234f59b4884ad680995b304c49
https://github.com/llvm/llvm-project/commit/1debf23d7a3393234f59b4884ad680995b304c49
Author: UmeshKalappa <103930015+ukalappa-mips at users.noreply.github.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/MC/RISCV/xmips-invalid.s
M llvm/test/MC/RISCV/xmips-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747)
Please refer the
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
for more information .
and files like RISCVInstrInfoXMips.td clang formatted .
No Regression found.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: a53a5ed65d60a7b942b0073db4b6bab6c0c5edb1
https://github.com/llvm/llvm-project/commit/a53a5ed65d60a7b942b0073db4b6bab6c0c5edb1
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
Log Message:
-----------
[VPlan] Add VPBlockBase::hasPredecessors (NFC).
Split off from https://github.com/llvm/llvm-project/pull/154510/, add
helper to check if a block has any predecessors.
Commit: d7d870326202a3dce9cec7a12aa097eb48c559d2
https://github.com/llvm/llvm-project/commit/d7d870326202a3dce9cec7a12aa097eb48c559d2
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter/dex/command/ParseCommand.py
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DAP.py
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/ConditionalController.py
M cross-project-tests/debuginfo-tests/dexter/dex/tools/test/Tool.py
A cross-project-tests/debuginfo-tests/dexter/feature_tests/commands/control/dex-continue.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/commands/control/dex_step_function.cpp
Log Message:
-----------
[Dexter] Implement DexStepFunction and DexContinue (#152721)
Adding together in a single commit as their implementations are linked.
Only supported for DAP debuggers. These two commands make it a bit easier to
drive dexter: DexStepFunction tells dexter to step-next though a function and
DexContinue tells dexter to continue (run free) from one breakpoint to another
within the current DexStepFunction function.
When the DexStepFunction function breakpoint is triggered, dexter sets an
instruction breakpoint at the return-address. This is so that stepping can
resume in any other DexStepFunctions deeps in the call stack.
Commit: 4cf770275fb54270fe7d4e22fbe9c08f70933d5c
https://github.com/llvm/llvm-project/commit/4cf770275fb54270fe7d4e22fbe9c08f70933d5c
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
Log Message:
-----------
[VPlan] Introduce replaceSymbolicStrides (NFC) (#155842)
Introduce VPlanTransforms::replaceSymbolicStrides factoring some code
from LoopVectorize.
Commit: e41a1bd30b777cac9a2aea5f7adfc6bd045fdda5
https://github.com/llvm/llvm-project/commit/e41a1bd30b777cac9a2aea5f7adfc6bd045fdda5
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M .ci/monolithic-linux.sh
Log Message:
-----------
[CI] Enable -Werror in pre-merge CI (#155627)
We have many buildbots that run with -Werror, but it's currently not
enabled in pre-merge CI, so adding a warning causes a slew of
post-commit failures.
Note that we only guarantee warning freedom when compiling with a recent
version of clang, but not when using gcc or msvc. The monolithic-linux
build uses recent clang (currently 21.1.0), so it should be safe to
enable the option there.
Commit: 392d03f3385d46613600c4e3c1ec4f3c71ea725b
https://github.com/llvm/llvm-project/commit/392d03f3385d46613600c4e3c1ec4f3c71ea725b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in TranslateToCpp.cpp (NFC)
Commit: 8a7fa1e03512228642f23e8b97067945f237220b
https://github.com/llvm/llvm-project/commit/8a7fa1e03512228642f23e8b97067945f237220b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/lib/IR/Location.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for performance-move-const-arg in Location.cpp (NFC)
Commit: a97f2069e58bbf2fdd727ca9497b9348930c0898
https://github.com/llvm/llvm-project/commit/a97f2069e58bbf2fdd727ca9497b9348930c0898
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/unittests/ExecutionEngine/Invoke.cpp
Log Message:
-----------
[MLIR] Fix unit-test missing guard `SKIP_WITHOUT_JIT` to exclude it on sparc
Commit: 020dff4be832e035a24fcdb13e26d7c2e69887eb
https://github.com/llvm/llvm-project/commit/020dff4be832e035a24fcdb13e26d7c2e69887eb
Author: William Huynh <William.Huynh at arm.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/File/CMakeLists.txt
A libc/src/__support/File/baremetal/CMakeLists.txt
A libc/src/__support/File/baremetal/stderr.cpp
A libc/src/__support/File/baremetal/stdin.cpp
A libc/src/__support/File/baremetal/stdout.cpp
A libc/src/__support/File/cookie_file.h
M libc/src/__support/OSUtil/baremetal/io.cpp
M libc/src/__support/OSUtil/baremetal/io.h
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/baremetal/CMakeLists.txt
R libc/src/stdio/baremetal/printf.cpp
R libc/src/stdio/baremetal/putchar.cpp
R libc/src/stdio/baremetal/puts.cpp
R libc/src/stdio/baremetal/vprintf.cpp
M libc/src/stdio/fopencookie.cpp
Log Message:
-----------
[libc] Migrate from baremetal stdio.h to generic stdio.h (#152748)
This is a follow up to the RFC here:
https://discourse.llvm.org/t/rfc-implementation-of-stdio-on-baremetal/86944
This provides the stdout/stderr/stdin symbols (which now don't have to
provided by the user). This allows the user to have access to all
functions, currently I've only tested `fprintf` but in theory everything
that works in the generic folder should work in the baremetal
configuration.
All streams are _non-buffered_, which does NOT require flushing. It is
based on the CookieFile that already existed
Commit: 2e8ecf7d5fbb4e0d029b0baf94f57f8161b396be
https://github.com/llvm/llvm-project/commit/2e8ecf7d5fbb4e0d029b0baf94f57f8161b396be
Author: Lakshay Kumar <lakshayk at nvidia.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
A llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
M llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
Log Message:
-----------
[llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (#142529)
Exegesis for AArch64 arch, before this patch only handles/initialise
Immediate and Register Operands.
For opcodes requiring rest operand types exegesis exits with Error:
`"not all operands are initialised by snippet generator"`.
To resolve a given error we have to initialise required operand types.
i.e., For `"not all operands are initialised by snippet generator"` init
`OPERAND_SHIFT_MSL`, `OPERAND_PCREL`,
And For `"targets with target-specific operands should implement this"`
init `OPERAND_FIRST_TARGET`.
This PR adds support to the following opcodes:-
- OPERAND_SHIFT_MSL: `[MOVI|MVNI]_[2s|4s]_msl`.
- OPERAND_PCREL: `LDR[R|X|W|SW|D|S|Q]l`
- OPERAND_IMPLICIT_IMM_0:
`[UMOV|SMOV]v[i8|i16|i32|i64|i8to32|i8to64|i16to32|i32to64|i16to64]_idx0`
---
### [Experiment/Learnings]
Moreover, We found out we can similarly omit `OPERAND_UNKNOWN` with
immediate value of 0. This brute force fix helps us get major part of
(`~1000`) opcodes which throw un-init operands error. But, The correct
way to resolve is to introduce `OperandType` in AArch64 tablegen files
for opcode which have `OPERND_UNKNOWN` in `AArch64GenInstrInfo.inc`. And
add switch case for those `OperandType` in the
`randomizeTargetMCOperand()`.
As, side-effect to this temporary fix that we explored is listed below
system-level instructions throws `illegal instruction` i.e. for`MRS,
MSR, MSRpstatesvcrImm1, SYSLxt, SYSxt, UDF`.
This patch in `--mode=inverse_throughput` for opcodes `MRS, MSR,
MSRpstatesvcrImm1, SYSLxt, SYSxt, UDF` exits with handled error of
`snippet crashed while running: Illegal instruction`, they previously
used to exits with error `not all operands initialized by snippet
generator`.
[For completeness] Additionally, exegesis beforehand and with this patch
too, throws illegal instruction in throughput mode, for these opcodes
too (`APAS, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, STGM, STZGM`). Will look
into them later.
---
### [Summary]
Thus, Only introduced changes in implementation of
`randomizeTargetMCOperand()` for AArch64 that omitting
`OPERAND_SHIFT_MSL`, `OPERAND_PCREL` to an immediate value of 264 and 8
respectively.
PS: Omitting
`MCOI::OPERAND_FIRST_TARGET`/`llvm:AArch64:OPERAND_IMPLICIT_IMM_0`
similarly, to value 0. It was low hanging change thus added in this PR
only.
For any future operand type of AArch64 if not initialised will exit with
error `"Unimplemented operand type: MCOI::OperandType:<#Number>"`.
Commit: 27c80fba53cd44ff3d575c6049bf88ecf6c15bc2
https://github.com/llvm/llvm-project/commit/27c80fba53cd44ff3d575c6049bf88ecf6c15bc2
Author: Brad Smith <brad at comstyle.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Log Message:
-----------
[sanitizer_common] Older Haiku needs _GNU_SOURCE (#156291)
Co-authored-by: Jérôme Duval <jerome.duval at gmail.com>
Commit: 10e5ec84573f83c172fc77da92252b60164b52b5
https://github.com/llvm/llvm-project/commit/10e5ec84573f83c172fc77da92252b60164b52b5
Author: Brad Smith <brad at comstyle.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Support/Unix/Threading.inc
Log Message:
-----------
[Support] Also check the value for HAVE_PTHREAD_(SETNAME/SET_NAME)_NP (#156294)
As was already done for HAVE_PTHREAD_(GETNAME/GET_NAME)_NP
Commit: f1032f06e8bd6571a929e45ca8d0afc9f17957cc
https://github.com/llvm/llvm-project/commit/f1032f06e8bd6571a929e45ca8d0afc9f17957cc
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Target/LLVMIR/nvvm/prefetch.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
Log Message:
-----------
[MLIR][NVVM][NVGPU] Combine prefetch and prefetch.tensormap (#153134)
This PR combines the `prefetch` and `prefetch.tensormap` NVVM Ops
to one `prefetch` Op. The `tensormap` variant is lowered through the
newly added intrinsics.
The lowering of the NVGPU `tma.prefetch.descriptor` Op is changed
from lowering to the `prefetch.tensormap` Op to `prefetch`.
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-prefetch-prefetchu
Commit: 32beea0605f37ea7a6429375d41b19ee78ddfe7d
https://github.com/llvm/llvm-project/commit/32beea0605f37ea7a6429375d41b19ee78ddfe7d
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M offload/plugins-nextgen/common/include/PluginInterface.h
Log Message:
-----------
[OpenMP][Offload] Mark `SPMD_NO_LOOP` as a valid exec mode (#155990)
This was added in #154105 , but was not added to the plugin interface's
list of valid modes.
Commit: 2320529ff77338cd0cb9786b8f195d611edcae77
https://github.com/llvm/llvm-project/commit/2320529ff77338cd0cb9786b8f195d611edcae77
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
M llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
Log Message:
-----------
[LoongArch] Fix broadcast load with extension. (#155960)
PR #135896 introduces [x]vldrepl instructions without handling
extension.
This patch will fix that.
Commit: 4b226318cca1ed8c29168defbba4599b0caf8edd
https://github.com/llvm/llvm-project/commit/4b226318cca1ed8c29168defbba4599b0caf8edd
Author: Vadim Curcă <80581374+VadimCurca at users.noreply.github.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/GlobalVariable.h
M llvm/lib/IR/Attributes.cpp
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[MLIR] Add target_specific_attrs attribute to mlir.global (#154706)
Adds a `target_specific_attrs` optional array attribute to
`mlir.global`, as well as conversions to and from LLVM attributes on
`llvm::GlobalVariable` objects. This is necessary to preserve unknown
attributes on global variables when converting to and from the LLVM
Dialect. Previously, any attributes on an `llvm::GlobalVariable` not
explicitly modeled by `mlir.global` were dropped during conversion.
Commit: b980ff795096ce95236b3e6f0f63cc9d1510fcec
https://github.com/llvm/llvm-project/commit/b980ff795096ce95236b3e6f0f63cc9d1510fcec
Author: WANG Rui <wangrui at loongson.cn>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
Log Message:
-----------
[LoongArch][NFC] Fix missing check prefixes in LSX build-vector.ll
Commit: a3dfedf09e017b00cb3cf5235c24cc57b96eb5b6
https://github.com/llvm/llvm-project/commit/a3dfedf09e017b00cb3cf5235c24cc57b96eb5b6
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/hints-trans.ll
Log Message:
-----------
[LV] Check both cases in hints-trans.ll: live and dead scalar loop.
Update hints-trans.ll to check both cases: 1) live scalar loop after
vectorization, 2) dead scalar loop after vectorization.
Commit: 77f256070f985029a53da5e76ecd85ca7686a7ea
https://github.com/llvm/llvm-project/commit/77f256070f985029a53da5e76ecd85ca7686a7ea
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.h
M mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/IR/Properties.td
M mlir/lib/Dialect/Ptr/IR/PtrAttrs.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
Log Message:
-----------
[mlir][ptr] Add load and store ops. (#156093)
This patch adds the load and store operations to the ptr dialect. It's
future work to implement SROA and Mem2Reg interfaces, as well as
conversion to LLVM, and add alias information.
This patch also fixes a bug in `OptionalProp` that was causing the
bytecode writer to exit early of writing the Op props if an optional
prop had the default value.
Example:
```mlir
func.func @load_ops(%arg0: !ptr.ptr<#ptr.generic_space>) -> (f32, f32, f32, f32, f32, i64, i32) {
%0 = ptr.load %arg0 : !ptr.ptr<#ptr.generic_space> -> f32
%1 = ptr.load volatile %arg0 : !ptr.ptr<#ptr.generic_space> -> f32
%2 = ptr.load %arg0 nontemporal : !ptr.ptr<#ptr.generic_space> -> f32
%3 = ptr.load %arg0 invariant : !ptr.ptr<#ptr.generic_space> -> f32
%4 = ptr.load %arg0 invariant_group : !ptr.ptr<#ptr.generic_space> -> f32
%5 = ptr.load %arg0 atomic monotonic alignment = 8 : !ptr.ptr<#ptr.generic_space> -> i64
%6 = ptr.load volatile %arg0 atomic syncscope("workgroup") acquire nontemporal alignment = 4 : !ptr.ptr<#ptr.generic_space> -> i32
return %0, %1, %2, %3, %4, %5, %6 : f32, f32, f32, f32, f32, i64, i32
}
func.func @store_ops(%arg0: !ptr.ptr<#ptr.generic_space>, %arg1: f32, %arg2: i64, %arg3: i32) {
ptr.store %arg1, %arg0 : f32, !ptr.ptr<#ptr.generic_space>
ptr.store volatile %arg1, %arg0 : f32, !ptr.ptr<#ptr.generic_space>
ptr.store %arg1, %arg0 nontemporal : f32, !ptr.ptr<#ptr.generic_space>
ptr.store %arg1, %arg0 invariant_group : f32, !ptr.ptr<#ptr.generic_space>
ptr.store %arg2, %arg0 atomic monotonic alignment = 8 : i64, !ptr.ptr<#ptr.generic_space>
ptr.store volatile %arg3, %arg0 atomic syncscope("workgroup") release nontemporal alignment = 4 : i32, !ptr.ptr<#ptr.generic_space>
return
}
```
Finally, this patch allows testing more advanced features of ptr memory
spaces, for example:
```mlir
// mlir-opt -verify-diagnostics
func.func @store_const(%arg0: !ptr.ptr<#test.const_memory_space>, %arg1: i64) {
// expected-error at +1 {{memory space is read-only}}
ptr.store %arg1, %arg0 atomic monotonic alignment = 8 : i64, !ptr.ptr<#test.const_memory_space>
return
}
```
Commit: 82245fc11d47f8c3d4fd00fe74c104c6321eca4d
https://github.com/llvm/llvm-project/commit/82245fc11d47f8c3d4fd00fe74c104c6321eca4d
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
Log Message:
-----------
[LV] Update make-follow-up-loop-id.ll to actually check metadata.
Update make-follow-up-loop-id.ll to make it independent of loop-unroll
by just checking if the correct metadata gets emitted for the scalar and
vector loops.
Also added a test to check for the case when the scalar loop is not
known to be dead.
Commit: 1477a67dceb99e3bac01e793ecaf18e36a01f33d
https://github.com/llvm/llvm-project/commit/1477a67dceb99e3bac01e793ecaf18e36a01f33d
Author: Gil Rapaport <gil.rapaport at mobileye.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Conversion/ArithToEmitC/arith-to-emitc.mlir
M mlir/test/Dialect/EmitC/form-expressions.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Target/Cpp/control_flow.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/Cpp/for.mlir
M mlir/test/Target/Cpp/switch.mlir
Log Message:
-----------
[mlir][emitc] Isolate expressions from above (#155641)
The expression op is currently not isolated from above. This served its
original usage as an optional, translation-oriented op, but is becoming
less convenient now that expressions appear earlier in the emitc
compilation flow and are gaining use as components of other emitc ops.
This patch therefore adds the isolated-from-above trait to expressions.
Syntactically, the only change is in the expression's signature which
now includes the values being used in the expression as arguments and
their types. The region's argument's names shadow the used values to
keep the def-use relations clear.
Commit: 74b7e7352b47dd1a5fd8c02bce392027b4c035dc
https://github.com/llvm/llvm-project/commit/74b7e7352b47dd1a5fd8c02bce392027b4c035dc
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test
Log Message:
-----------
[llldb][test] Mark a DWO test unsupported on Darwin and Windows (#156306)
This uses split DWARF and from looking at other tests, it should not be
running on Darwin or Windows.
It does pass using the DIA PDB plugin but I think this is misleading
because it's not actually testing the intended feature.
When the native PDB plugin is used it fails because it cannot set a
breakpoint. I don't see a point to running this test on Windows at all.
Native PDB plugin test failures are being tracked in #114906.
Commit: af80969b8125f242b37a96b6c7f63cb2910e2f59
https://github.com/llvm/llvm-project/commit/af80969b8125f242b37a96b6c7f63cb2910e2f59
Author: Jessica Del <50999226+OutOfCache at users.noreply.github.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Log Message:
-----------
[NFC] SimplifyCFG: Detect switch replacement earlier in `switchToLookup` (#155602)
This PR is the first part to solve the issue in #149937.
The end goal is enabling more switch optimizations on targets that do
not support lookup tables.
SimplifyCFG has the ability to replace switches with either a few simple
calculations, a single value, or a lookup table.
However, it only considers these options if the target supports lookup
tables, even if the final result is not a LUT, but a few simple
instructions like muls, adds and shifts.
To enable more targets to use these other kinds of optimization, this PR
restructures the code in `switchToLookup`.
Previously, code was generated even before choosing what kind of
replacement to do. However, we need to know if we actually want to
create a true LUT or not before generating anything. Then we can check
for target support only if any LUT would be created.
This PR moves the code so it first determines the replacement kind and
then generates the instructions.
A later PR will insert the target support check after determining the
kind of replacement. If the result is not a LUT, then even targets
without LUT support can replace the switch with something else.
Commit: 5f412415645edb0d735dbc58306e9deb6ab0bcd4
https://github.com/llvm/llvm-project/commit/5f412415645edb0d735dbc58306e9deb6ab0bcd4
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/docs/ProgrammersManual.rst
Log Message:
-----------
[docs] Update logging section of the programmer manual to include LDBG() (NFC) (#156235)
Commit: f0e9bba024d44b55d54b02025623ce4a3ba5a37c
https://github.com/llvm/llvm-project/commit/f0e9bba024d44b55d54b02025623ce4a3ba5a37c
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll
A llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
Log Message:
-----------
[LoopVectorize] Generate wide active lane masks (#147535)
This patch adds a new flag (-enable-wide-lane-mask) which allows
LoopVectorize to generate wider-than-VF active lane masks when it
is safe to do so (i.e. the mask is used for data and control flow).
The transform in extractFromWideActiveLaneMask creates vector
extracts from the first active lane mask in the header & loop body,
modifying the active lane mask phi operands to use the extracts.
An additional operand is passed to the ActiveLaneMask instruction,
the value of which is used as a multiplier of VF when generating the
mask.
By default this is 1, and is updated to UF by
extractFromWideActiveLaneMask.
The motivation for this change is to improve interleaved loops when
SVE2.1 is available, where we can make use of the whilelo instruction
which returns a predicate pair.
This is based on a PR that was created by @momchil-velikov (#81140)
and contains tests which were added there.
Commit: 2b5e105b58de773011260d36b5fe51ab66b331d5
https://github.com/llvm/llvm-project/commit/2b5e105b58de773011260d36b5fe51ab66b331d5
Author: scuzqy <80660355+scuzqy at users.noreply.github.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/docs/GitHub.rst
Log Message:
-----------
[docs] Correct MD links to proper reST syntax in GitHub.rst (#143277)
No content changes were made beyond syntax correction.
Commit: e34d2e1de2badc23276b2fd1e75cc65814c0e96f
https://github.com/llvm/llvm-project/commit/e34d2e1de2badc23276b2fd1e75cc65814c0e96f
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Add MMRA documentation (#156310)
MMRAs were missing from LangRef.
Commit: fb7c0d70a7aa284e1ef509e415849b4eea992ec9
https://github.com/llvm/llvm-project/commit/fb7c0d70a7aa284e1ef509e415849b4eea992ec9
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info-apply-to-adds.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-apply-to-adds.ll
M llvm/test/Transforms/LoopVectorize/miniters.ll
Log Message:
-----------
[SCEV] Rewrite some SCEVAdd sub-expressions using loop guards. (#156013)
Trip count expressions sometimes consist of adding 3 operands, i.e.
(Const + A + B). There may be guard info for A + B, and if so, apply it.
We can probably more generally apply this, but need to be careful w.r.t
compile-time.
Alive2 Proof for changes in miniters.ll:
https://alive2.llvm.org/ce/z/HFfXOx
Fixes https://github.com/llvm/llvm-project/issues/155941.
PR: https://github.com/llvm/llvm-project/pull/156013
Commit: eb7f6a5f8a167162eddf03a741b44e79dcce378c
https://github.com/llvm/llvm-project/commit/eb7f6a5f8a167162eddf03a741b44e79dcce378c
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
Log Message:
-----------
[VPlan] Simplify (x && y) || (x && z) -> x && (y || z) (#156308)
Split off from #155383, since it turns out this has a diff on its own.
Commit: 13357e8a12c1a45364a0c4d3137b6d21ee6ac40c
https://github.com/llvm/llvm-project/commit/13357e8a12c1a45364a0c4d3137b6d21ee6ac40c
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
Log Message:
-----------
[LV][EVL] Support interleaved access with tail folding by EVL (#152070)
The InterleavedAccess pass already supports transforming
vector-predicated (vp) load/store intrinsics. With this patch, we start
enabling interleaved access under tail folding by EVL.
This patch introduces a new base class, VPInterleaveBase, and a concrete
class, VPInterleaveEVLRecipe. Both the existing VPInterleaveRecipe and
the new VPInterleaveEVLRecipe inherit from and implement
VPInterleaveBase.
Compared to VPInterleaveRecipe, VPInterleaveEVLRecipe adds an EVL
operand to emit vp.load/vp.store intrinsics.
Currently, tail folding by EVL is only supported for scalable
vectorization. Therefore, VPInterleaveEVLRecipe will only emit
interleave/deinterleave intrinsics. Reverse accesses are not yet
implemented, as masked reverse interleaved access under tail folding is
not yet supported.
Fixed #123201
Commit: 4c916273041ff5ed7b2af20bec787ffc42871c9f
https://github.com/llvm/llvm-project/commit/4c916273041ff5ed7b2af20bec787ffc42871c9f
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M lldb/test/Shell/Settings/TestFrameFormatFunctionReturnObjC.test
Log Message:
-----------
[lldb][test] Use lld on Windows in frame format test (#156320)
link.exe discards DWARF information. Other linkers on non-Windows do
not.
Uses the same solution as TestFrameFunctionInlined.test.
This test was failing with the native PDB plugin but shouldn't have been
using PDB anyway (see #114906). Passes with DWARF and lld.
Commit: 78e3a58d218c07bf54b466718bbc53547648040a
https://github.com/llvm/llvm-project/commit/78e3a58d218c07bf54b466718bbc53547648040a
Author: nfrmtk <nfrmtk.aka.fkfka at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
Log Message:
-----------
[Clang] correct error message when assigning to const reference captured in lambda (#105647)
Fixes #98772
Commit: f8faf23d92a6bf931bad6104bace62be7182724c
https://github.com/llvm/llvm-project/commit/f8faf23d92a6bf931bad6104bace62be7182724c
Author: Denzel-Brian Budii <73462654+chios202 at users.noreply.github.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/lib/Tools/mlir-query/MlirQueryMain.cpp
Log Message:
-----------
[mlir] Default `mlir-query` input to stdin (#156324)
This allows piping without an explicit `-` :
```shell
./mlir-opt input.mlir -canonicalize | ./mlir-query -c "<your_query_1>" -c "<your_query_2>" ... -c "<your_query_N>"
```
Commit: 3a1298b943fe3beea60e6a6f2dff154620774aff
https://github.com/llvm/llvm-project/commit/3a1298b943fe3beea60e6a6f2dff154620774aff
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M libcxx/include/__tree
Log Message:
-----------
[libc++][NFC] Replace typedefs with using declarations (#156009)
We've done quite a bit of refactoring recently in `<__tree>`. This patch
finishes up replacing typedefs with using declarations. As a
side-effect, this also adds some `_LIBCPP_NODEBUG` annotations, since
the clang-tidy check catches these now.
Commit: c6286b30bd6eaa55a53891bde77a5e82879d01f0
https://github.com/llvm/llvm-project/commit/c6286b30bd6eaa55a53891bde77a5e82879d01f0
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
A llvm/test/DebugInfo/Generic/structor-declaration-linkage-names.ll
Log Message:
-----------
[llvm][DebugInfo] Support DW_AT_linkage_names that are different between declaration and definition (#154137)
This patch is motivated by
https://github.com/llvm/llvm-project/pull/149827, where we plan on using
mangled names on structor declarations to find the exact structor
definition that LLDB's expression evaluator should call.
So far LLVM expects the declaration and definition linkage names to be
identical (or the declaration to just not have a linkage name). But we
plan on attaching the GCC-style "unified" mangled name to declarations,
which will be different to linkage name on the definition. This patch
relaxes this restriction.
Commit: 4dbfde6b69ccba47fc5fc573f65d69c3ec79d733
https://github.com/llvm/llvm-project/commit/4dbfde6b69ccba47fc5fc573f65d69c3ec79d733
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M libcxx/test/std/iterators/iterator.requirements/indirectcallable/indirectinvocable/indirect_result_t.compile.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/ranges_destroy_at.pass.cpp
M libcxx/test/std/utilities/meta/meta.rel/is_convertible.pass.cpp
Log Message:
-----------
[libc++] Remove a few GCC workarounds that aren't needed anymore (#156290)
Commit: 6aeea122c51c65189cff023b5bf5b5aa9e28ef5d
https://github.com/llvm/llvm-project/commit/6aeea122c51c65189cff023b5bf5b5aa9e28ef5d
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Simplify population of `ReducedVals` (#156292)
Commit: dc5cf01dc04288da8d6ee46797565037ed0f7687
https://github.com/llvm/llvm-project/commit/dc5cf01dc04288da8d6ee46797565037ed0f7687
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/test/CodeGen/X86/x86-builtins.c
Log Message:
-----------
[X86] Add -fexperimental-new-constant-interpreter test coverage to the u32/f32 u64/f64 cast constexpr test files (#156327)
Update tests to use builtin_test_helpers.h and the TEST_CONSTEXPR helper macro
Partial fix for #155814
Commit: df95dfcf5a1e900801fdaa50daa63df16ca86fc3
https://github.com/llvm/llvm-project/commit/df95dfcf5a1e900801fdaa50daa63df16ca86fc3
Author: Andrey Karlov <dein.negativ at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/bugprone/unchecked-optional-access.cpp
M clang/include/clang/AST/Decl.h
M clang/lib/AST/Decl.cpp
M clang/lib/Analysis/CFG.cpp
M clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
Log Message:
-----------
[clang]: Support `analyzer_noreturn` attribute in `CFG` (#150952)
## Problem
Currently, functions with `analyzer_noreturn` attribute aren't
recognized as `no-return` by `CFG`:
```cpp
void assertion_handler() __attribute__((analyzer_noreturn)) {
log(...);
}
void handle_error(const std::optional<int> opt) {
if (!opt) {
fatal_error(); // Static analyzer doesn't know this never returns
}
*opt = 1; // False-positive `unchecked-optional-access` warning as analyzer thinks this is reachable
}
```
## Solution
1. Extend the `FunctionDecl` class by adding an `isAnalyzerNoReturn()`
function
2. Update `CFGBuilder::VisitCallExpr` to check both `FD->isNoReturn()`
and `FD->isAnalyzerNoReturn()` properties
## Comments
This PR incorporates part of the work done in
https://github.com/llvm/llvm-project/pull/146355
Commit: f502bab70fdeb9f58590d82816accf1783a5285b
https://github.com/llvm/llvm-project/commit/f502bab70fdeb9f58590d82816accf1783a5285b
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/DenseMap.h
Log Message:
-----------
[ADT] Overhaul the DenseMapIterator creation logic (NFC) (#156221)
Without this patch, it's overly complicated to create iterators in
DenseMap.
- We must specify whether to advance a newly created iterator, which
is needed in begin().
- We call shouldReverseIterate outside and inside DenseMapIterator.
This patch cleans up all this by creating factory methods:
- DenseMapIterator::makeBegin
- DenseMapIterator::makeEnd
- DenseMapIterator::makeIterator
With these:
- makeBegin knows that we need to advance the iterator to the first
valid bucket.
- Callers outside DenseMapIterator do not reference
shouldReverseIterate at all.
Now, it's a lot simpler to call helper functions
DenseMapBase::{makeIterator,makeConstIterator}. We just have to pass
the Bucket pointer:
makeIterator(Bucket);
and they take care of the rest, including passing *this as Epoch.
Commit: 2d216a94f3c84037cdfb3fa5def9efb020a88537
https://github.com/llvm/llvm-project/commit/2d216a94f3c84037cdfb3fa5def9efb020a88537
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/PointerUnion.h
Log Message:
-----------
[ADT] Simplify CastInfo<To, PointerUnion<PTs...>> (NFC) (#156274)
This patch simplifies CastInfo<To, PointerUnion<PTs...>> by "inlining"
CastInfoPointerUnionImpl into the CastInfo specialization.
Here is a brief background:
https://reviews.llvm.org/D125609
added support for CastInfo<To, PointerUnion<PTs...>> along with helper
struct CastInfoPointerUnionImpl. During the review, we did discuss
the idea of implementing the CastInfo specialization without the
helper struct, but the suggested solution did not work.
This patch attempts to simplify the CastInfo specialization again by
making CastInfo a friend of PointerUnion:
template <typename To, typename From, typename Enable>
friend struct CastInfo;
This gives CastInfo more access to PointerUnion than strictly
necessary, but the ability to simplify the CastInfo specialization
outweighs the risk.
Commit: 507ff082c2a301d63615695083cf209ec89ef253
https://github.com/llvm/llvm-project/commit/507ff082c2a301d63615695083cf209ec89ef253
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] Move runtime check blocks to correct position during exec (NFC).
Move adjusting the position of completely disconnected IR blocks to
VPIRBasicBlock::execute.
Commit: e956090f7455750c7ce932801609c22a97b19a05
https://github.com/llvm/llvm-project/commit/e956090f7455750c7ce932801609c22a97b19a05
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/test/CodeGen/X86/rot-intrinsics.c
Log Message:
-----------
[X86] Add -fexperimental-new-constant-interpreter test coverage to the x86 scalar rotate constexpr test files (#156337)
Update tests to use builtin_test_helpers.h and the TEST_CONSTEXPR helper macro
Partial fix for #155814
Commit: 3fd682863968dbbae2ad84b82741f24689bab85b
https://github.com/llvm/llvm-project/commit/3fd682863968dbbae2ad84b82741f24689bab85b
Author: Piotr Fusik <p.fusik at samsung.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Refactor duplicate code into `getVectorizedValue` (#156277)
Commit: e932e413cfd00d42b2832c7d5fc4b3db576a1401
https://github.com/llvm/llvm-project/commit/e932e413cfd00d42b2832c7d5fc4b3db576a1401
Author: moorabbit <moorabbit at proton.me>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avxintrin.h
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
Log Message:
-----------
[Headers][X86] Add constexpr support for some AVX[512] intrinsics. (#156187)
The following AVX[512] intrinsics are now constexpr:
- `_mm256_cvtepi32_pd`
- `_mm256_cvtepi32_ps`
- `_mm256_cvtps_pd`
- `_mm512_cvtepi32_ps`
- `_mm512_mask_cvtepi32_ps`
- `_mm512_maskz_cvtepi32_ps`
- `_mm512_cvtepu32_ps`
- `_mm512_mask_cvtepu32_ps`
- `_mm512_maskz_cvtepu32_ps`
- `_mm512_cvtepi32_pd`
- `_mm512_mask_cvtepi32_pd`
- `_mm512_maskz_cvtepi32_pd`
- `_mm512_cvtepi32lo_pd`
- `_mm512_mask_cvtepi32lo_pd`
- `_mm512_cvtepu32_pd`
- `_mm512_mask_cvtepu32_pd`
- `_mm512_maskz_cvtepu32_pd`
- `_mm512_cvtepu32lo_pd`
- `_mm512_mask_cvtepu32lo_pd`
- `_mm512_cvtps_pd`
- `_mm512_mask_cvtps_pd`
- `_mm512_maskz_cvtps_pd`
- `_mm512_cvtpslo_pd`
- `_mm512_mask_cvtpslo_pd`
- `_mm512_castsi512_si256`
- `_mm512_castps512_ps256`
This PR is part 1 of a series of PRs fixing #155798
Commit: 1fae86d5d361328b0598dd51dfb32f620c7d4158
https://github.com/llvm/llvm-project/commit/1fae86d5d361328b0598dd51dfb32f620c7d4158
Author: beetrees <b at beetr.ee>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/CodeGen/ARM/fp16-promote.ll
Log Message:
-----------
[ARM] Improve fp16-promote.ll test (NFC) (#156341)
Update the test to use `utils/update_llc_test_checks.py`, and add a
check for `fneg`. Prerequisite to #156343.
Commit: de6a83257c788731e1c8fadf36b7de2a3a433908
https://github.com/llvm/llvm-project/commit/de6a83257c788731e1c8fadf36b7de2a3a433908
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
A llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size-needs-loop-guards.ll
Log Message:
-----------
[Loads] Add tests for proving deref with assumes and loop guards.
Extra test coverage for using loop guards when reasoning about
dereferenceability with assumes.
Commit: 37127f74f4ed7a5c5fef04ef99bea77de4846da4
https://github.com/llvm/llvm-project/commit/37127f74f4ed7a5c5fef04ef99bea77de4846da4
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vecreduceadd.ll
Log Message:
-----------
[LV] Bundle sub reductions into VPExpressionRecipe (#147255)
This PR bundles sub reductions into the VPExpressionRecipe class and
adjusts the cost functions to take the negation into account.
Stacked PRs:
1. https://github.com/llvm/llvm-project/pull/147026
2. -> https://github.com/llvm/llvm-project/pull/147255
3. https://github.com/llvm/llvm-project/pull/147302
4. https://github.com/llvm/llvm-project/pull/147513
Commit: c241eb30c5c315942b8c83e1125b508e9a626a7d
https://github.com/llvm/llvm-project/commit/c241eb30c5c315942b8c83e1125b508e9a626a7d
Author: XChy <xxs_chy at outlook.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-vpmadd52.ll
Log Message:
-----------
[X86] Fold X * Y + Z --> C + Z for vpmadd52l/vpmadd52h (#156293)
Address TODO and implement constant fold for intermediate multiplication
result of vpmadd52l/vpmadd52h.
Commit: 5e28192fbac7c11205d3cc9e3d18f3670d7cfc7f
https://github.com/llvm/llvm-project/commit/5e28192fbac7c11205d3cc9e3d18f3670d7cfc7f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/lib/Interfaces/ValueBoundsOpInterface.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-simplify-boolean-expr in ValueBoundsOpInterface.cpp (NFC)
Commit: c4e70c28a3c2481181f21eb67b3f357d73e71fc3
https://github.com/llvm/llvm-project/commit/c4e70c28a3c2481181f21eb67b3f357d73e71fc3
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in AttrOrTypeFormatGen.cpp (NFC)
Commit: 442e4ad92301882e8362edd64072f7cc6e36d141
https://github.com/llvm/llvm-project/commit/442e4ad92301882e8362edd64072f7cc6e36d141
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/lib/Tools/mlir-reduce/MlirReduceMain.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in MlirReduceMain.cpp (NFC)
Commit: 6980d3b307b41600b9dbcc0d2d8ba4ef4990a89d
https://github.com/llvm/llvm-project/commit/6980d3b307b41600b9dbcc0d2d8ba4ef4990a89d
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/CodeGen/X86/call-graph-section.ll
Log Message:
-----------
[NFC][llvm] Simplify test IR file (#155926)
Commit: bf4486eb29c3009ddf68968b021c6fd98e3c2d52
https://github.com/llvm/llvm-project/commit/bf4486eb29c3009ddf68968b021c6fd98e3c2d52
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Move fixing reduction resumes for epilogue out of executePlan.(NFC)
Move fixing up reduction resume values out of the general ::executePlan
and perform it together with updating induction resume values.
This also allows moving additional bypass block handling to
EpilogueVectorizerEpilogueLoop.
Commit: b1a8089f1cf67a6038a6b6d958eff1bd2feb4f8d
https://github.com/llvm/llvm-project/commit/b1a8089f1cf67a6038a6b6d958eff1bd2feb4f8d
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/Sema/SemaTypeTraits.cpp
A clang/test/SemaCXX/type-trait-synthesises-from-spaceship.cpp
Log Message:
-----------
[Clang] Introduce __builtin_meow_synthesises_from_spaceship (#155612)
This set of builtins makes it possible to detect whether a comparison
operation is synthesised from a spaceship operator. This makes it
possible to avoid calling the comparison multiple times if you care
about the three-way relation. This is especially interesting for the
associative containers from the STL, since a lot of functions call the
comparator twice to establish the relation. With this builtin these
functions can call the comparator just once and use the result of the
three way comparison directly.
Commit: 5176fb8b1369f9738731ea3452828b29227e1e06
https://github.com/llvm/llvm-project/commit/5176fb8b1369f9738731ea3452828b29227e1e06
Author: Marco Elver <elver at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Clang] Update ReleaseNotes with ThreadSafetyAnalysis changes (#155687)
Note that ACQUIRED_BEFORE(...) and ACQUIRED_AFTER(...) no longer require
-Wthread-safety-beta.
Follow-up from https://github.com/llvm/llvm-project/pull/152853.
Commit: a80a1988f7b73f1608f22a35f20261358aa09085
https://github.com/llvm/llvm-project/commit/a80a1988f7b73f1608f22a35f20261358aa09085
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
Log Message:
-----------
[SLP]Better support for copyable values in stores
Currently stores are sorted by the stored values instruction types,
which do not include analysis for copyables. The compiler may miss some
potential vectorization opportunities because of that. Patch adds
detection of the copyables in stored values.
Reviewers: hiraditya, HanKuanChen, RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/153213
Commit: 33d5a3b455d3bb0d0487dabb98728aeaa8cba03b
https://github.com/llvm/llvm-project/commit/33d5a3b455d3bb0d0487dabb98728aeaa8cba03b
Author: David Green <david.green at arm.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
Log Message:
-----------
[AArch64] Add some multiuse tests for fptosi+sitofp converts. NFC
Commit: dafffe262d6d1114fa83ec155241aad4e7793845
https://github.com/llvm/llvm-project/commit/dafffe262d6d1114fa83ec155241aad4e7793845
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/MC/MCDecoder.h
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
A llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td
M llvm/test/TableGen/DecoderEmitterFnTable.td
M llvm/test/TableGen/HwModeEncodeDecode3.td
M llvm/test/TableGen/VarLenDecoder.td
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Disassembler/BUILD.gn
Log Message:
-----------
[LLVM][MC][DecoderEmitter] Add support to specialize decoder per bitwidth (#154865)
This change adds an option to specialize decoders per bitwidth, which
can help reduce the (compiled) code size of the decoder code.
**Current state**:
Currently, the code generated by the decoder emitter consists of two key
functions: `decodeInstruction` which is the entry point into the
generated code and `decodeToMCInst` which is invoked when a decode op is
reached while traversing through the decoder table. Both functions are
templated on `InsnType` which is the raw instruction bits that are
supplied to `decodeInstruction`.
Several backends call `decodeInstruction` with different `InsnType`
types, leading to several template instantiations of these functions in
the final code. As an example, AMDGPU instantiates this function with
type `DecoderUInt128` type for decoding 96/128-bit instructions,
`uint64_t` for decoding 64-bit instructions, and `uint32_t` for decoding
32-bit instructions. Since there is just one `decodeToMCInst` in the
generated code, it has code that handles decoding for *all* instruction
sizes. However, the decoders emitted for different instructions sizes
rarely have any intersection with each other. That means, in the AMDGPU
case, the instantiation with InsnType == DecoderUInt128 has decoder code
for 32/64-bit instructions that is *never exercised*. Conversely, the
instantiation with InsnType == uint64_t has decoder code for
128/96/32-bit instructions that is never exercised. This leads to
unnecessary dead code in the generated disassembler binary (that the
compiler cannot eliminate by itself).
**New state**:
With this change, we introduce an option
`specialize-decoders-per-bitwidth`. Under this mode, the DecoderEmitter
will generate several versions of `decodeToMCInst` function, one for
each bitwidth. The code is still templated, but will require backends to
specify, for each `InsnType` used, the bitwidth of the instruction that
the type is used to represent using a type-trait `InsnBitWidth`. This
will enable the templated code to choose the right variant of
`decodeToMCInst`. Under this mode, a particular instantiation will only
end up instantiating a single variant of `decodeToMCInst` generated and
that will include only those decoders that are applicable to a single
bitwidth, resulting in elimination of the code duplication through
instantiation and a reduction in code size.
Additionally, under this mode, decoders are uniqued only within a given
bitwidth (as opposed to across all bitwidths without this option), so
the decoder index values assigned are smaller, and consume less bytes in
their ULEB128 encoding. As a result, the generated decoder tables can
also reduce in size.
Adopt this feature for the AMDGPU and RISCV backend. In a release build,
this results in a net 55% reduction in the .text size of
libLLVMAMDGPUDisassembler.so and a 5% reduction in the .rodata size. For
RISCV, which today uses a single `uint64_t` type, this results in a 3.7%
increase in code size (expected as we instantiate the code 3 times now).
Actual measured sizes are as follows:
```
Baseline commit: 72c04bb882ad70230bce309c3013d9cc2c99e9a7
Configuration: Ubuntu clang version 18.1.3, release build with asserts disabled.
AMDGPU Before After Change
======================================================
.text 612327 275607 55% reduction
.rodata 369728 351336 5% reduction
RISCV:
======================================================
.text 47407 49187 3.7% increase
.rodata 35768 35839 0.1% increase
```
Commit: 0b1a17c6ccf7e72e4a1044008a655c5e75479b0b
https://github.com/llvm/llvm-project/commit/0b1a17c6ccf7e72e4a1044008a655c5e75479b0b
Author: William Huynh <William.Huynh at arm.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/src/__support/File/CMakeLists.txt
R libc/src/__support/File/baremetal/CMakeLists.txt
R libc/src/__support/File/baremetal/stderr.cpp
R libc/src/__support/File/baremetal/stdin.cpp
R libc/src/__support/File/baremetal/stdout.cpp
R libc/src/__support/File/cookie_file.h
M libc/src/__support/OSUtil/baremetal/io.cpp
M libc/src/__support/OSUtil/baremetal/io.h
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/baremetal/CMakeLists.txt
A libc/src/stdio/baremetal/printf.cpp
A libc/src/stdio/baremetal/putchar.cpp
A libc/src/stdio/baremetal/puts.cpp
A libc/src/stdio/baremetal/vprintf.cpp
M libc/src/stdio/fopencookie.cpp
Log Message:
-----------
Revert "[libc] Migrate from baremetal stdio.h to generic stdio.h" (#156371)
Reverts llvm/llvm-project#152748
Commit: a7224dc188bb131a4c51b33104e8090ccaad3250
https://github.com/llvm/llvm-project/commit/a7224dc188bb131a4c51b33104e8090ccaad3250
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
Log Message:
-----------
[Support] clang-format YAMLTraits.h
I'm planning to modify this file.
Commit: fdfc751d39f81f5e0befc898d3fc1994ea655d07
https://github.com/llvm/llvm-project/commit/fdfc751d39f81f5e0befc898d3fc1994ea655d07
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
Log Message:
-----------
[MLIR][XeGPU] Distribute load_gather/store_scatter op from Wg To Sg (#154420)
This PR adds distribution patterns for scatter ops (LoadGather and
StoreScatter) with offsets.
Commit: 74230ff2791384fb3285c9e9ab202056959aa095
https://github.com/llvm/llvm-project/commit/74230ff2791384fb3285c9e9ab202056959aa095
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
[SLP]Improved/fixed FMAD support in reductions
In the initial patch for FMAD, potential FMAD nodes were completely
excluded from the reduction analysis for the smaller patch. But it may
cause regressions.
This patch adds better detection of scalar FMAD reduction operations and
tries to correctly calculate the costs of the FMAD reduction operations
(also, excluding the costs of the scalar fmuls) and split reduction
operations, combined with regular FMADs.
Reviewers: RKSimon, gregbedwell, hiraditya
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/152787
Commit: 15173344aa958f1e123d4f8626fc0ff4d67c8635
https://github.com/llvm/llvm-project/commit/15173344aa958f1e123d4f8626fc0ff4d67c8635
Author: Fangrui Song <i at maskray.me>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/include/mlir/IR/EnumAttr.td
M mlir/test/lib/Dialect/Test/TestEnumDefs.td
Log Message:
-----------
[mlir] EnumAttr.td: Fix the width of I64Enum (#156133)
Follow-up to #132148
Commit: a7d1a652c2e7872939caf22d5209a060f7dccd7e
https://github.com/llvm/llvm-project/commit/a7d1a652c2e7872939caf22d5209a060f7dccd7e
Author: Fangrui Song <i at maskray.me>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
Log Message:
-----------
[RISCV] Fix -Wexplicit-specialization-storage-class warnings
Commit: e8b5fbd5fa0d0fbe0cc788964cb7e34482301348
https://github.com/llvm/llvm-project/commit/e8b5fbd5fa0d0fbe0cc788964cb7e34482301348
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
Log Message:
-----------
[AMDGPU, RISCV] Fix warnings
This patch fixes:
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:451:13:
error: explicit specialization cannot have a storage class
[-Werror,-Wexplicit-specialization-storage-class]
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:452:13:
error: explicit specialization cannot have a storage class
[-Werror,-Wexplicit-specialization-storage-class]
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:454:1:
error: explicit specialization cannot have a storage class
[-Werror,-Wexplicit-specialization-storage-class]
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:456:1:
error: explicit specialization cannot have a storage class
[-Werror,-Wexplicit-specialization-storage-class]
While I am at it, this patch changes the storage types of InsnBitWidth
specilization to "inline constexpr" to avoid linker errors.
Commit: 32868480cd039735c2f58adcd775472bcfd22a8b
https://github.com/llvm/llvm-project/commit/32868480cd039735c2f58adcd775472bcfd22a8b
Author: Jim Lin <jim at andestech.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/attributes-andes.ll
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Split the attribute test for Andes to attributes-andes.ll. NFC.
Commit: 21554274504f357d524bfe72294254c51e2b2562
https://github.com/llvm/llvm-project/commit/21554274504f357d524bfe72294254c51e2b2562
Author: Jim Lin <jim at andestech.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A llvm/test/CodeGen/RISCV/attributes-qc.ll
M llvm/test/CodeGen/RISCV/attributes.ll
Log Message:
-----------
[RISCV] Split the attribute test for Qualcomm to attributes-qc.ll. NFC.
Commit: b26f424152c1e0fead489239d48d49370bb92680
https://github.com/llvm/llvm-project/commit/b26f424152c1e0fead489239d48d49370bb92680
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/test/DebugInfo/Generic/structor-declaration-linkage-names.ll
Log Message:
-----------
[llvm][DebugInfo] Fix test on builds without target aarch64
Commit: 7997a79be67e925648881935818f23e1601c5f1c
https://github.com/llvm/llvm-project/commit/7997a79be67e925648881935818f23e1601c5f1c
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
Log Message:
-----------
[LV] Align legacy cost model to vplan-based model for gather/scatter w/ uniform addr. (#155739)
This patch check if the addr is uniform in legacy cost model to align
vplan-based cost model after #150371.
This patch fixes llvm-test-suite assertion
(https://lab.llvm.org/buildbot/#/builders/210/builds/1935) due to cost
model misaligned after #149955 under RISCV.
I've tested this patch (on top of #149955) on the llvm-test-suite
locally with crashed options `rva23u64`, `rva23u64_zvl1024b` and build
successfully.
Since this fix will change LV, I think would be better to create a PR to
fix this.
Commit: 9f42ba358806eaaa8c133fb116d8cc9612cd29fa
https://github.com/llvm/llvm-project/commit/9f42ba358806eaaa8c133fb116d8cc9612cd29fa
Author: Nico Weber <thakis at chromium.org>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn
Log Message:
-----------
[gn] Fix accidental args override from dafffe262d6d11
dafffe262d6d11 added `"-specialize-decoders-per-bitwidth",` to args,
but also added a stray `args = []` line after it.
Commit: 57365952ef3a0b5cd79b5af095c46579b409f7a2
https://github.com/llvm/llvm-project/commit/57365952ef3a0b5cd79b5af095c46579b409f7a2
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M flang/include/flang/Runtime/freestanding-tools.h
Log Message:
-----------
[Flang][Runtime][OpenMP][AMDGPU] Revert part of #152631 causing regression for amdgpu
When modifying the PR during review I made a minor alteration that I thought made sense,
but after further testing doesn't seem to. So, in this commit I regress the offending bit
of code.
Commit: b582670f6b33cde4e786bd98c1e0e712fe6236df
https://github.com/llvm/llvm-project/commit/b582670f6b33cde4e786bd98c1e0e712fe6236df
Author: x12301450 <x12301450 at 163.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Arith/Transforms/CMakeLists.txt
M mlir/lib/Dialect/ControlFlow/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Quant/Transforms/CMakeLists.txt
Log Message:
-----------
[MLIR][BUG] fix {$VARIABLE} usage in CMakeLists.txt (#156183)
This pr fixed #156182
Commit: 3b2796cc43b6b9dda7e75aa050a7ca2bf14e8bf9
https://github.com/llvm/llvm-project/commit/3b2796cc43b6b9dda7e75aa050a7ca2bf14e8bf9
Author: Owen Anderson <resistor at mac.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[Triple] Add target triple support for CheriotRTOS. (#155374)
For context, CheriotRTOS is a custom RTOS co-designed for the CHERIoT
CHERI-enabled RISCV32E platform. It uses a custom ABI and linkage model,
necesitating representing it in the target triple.
Commit: 0849dc11d9844a4df5f18c46831da3859e3ae4c1
https://github.com/llvm/llvm-project/commit/0849dc11d9844a4df5f18c46831da3859e3ae4c1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
Log Message:
-----------
AMDGPU: Switch merge-load-store-agpr test to generated checks (#156387)
Also had to fix missing --- separators between functions
Commit: 8fdae0c7daf3831c48be4c69e799da627337bddd
https://github.com/llvm/llvm-project/commit/8fdae0c7daf3831c48be4c69e799da627337bddd
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr154103.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
Log Message:
-----------
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
This patch implements the `getAddressComputationCost()` in RISCV TTI
which
make the gather/scatter with address calculation more expansive that
stride cost.
Note that the only user of `getAddressComputationCost()` with vector
type is in `VPWidenMemoryRecipe::computeCost()`. So this patch make some
LV tests changes.
I've checked the tests changes in LV and seems those changes can be
divided into two groups.
* gather/scatter with uniform vector ptr, seems can be optimized to
masked.load.
* can optimize to stride load/store.
----
After #155739 landed, the assertion (cost mis-aligned) is fixed.
I've tested llvm-test-suite w/ rva23u64 and rva23u64_zvl1024b locally
and no assertion occurred.
Commit: 66ba9dc62ba647d5dcefdcab06f21d38f6b2dd5f
https://github.com/llvm/llvm-project/commit/66ba9dc62ba647d5dcefdcab06f21d38f6b2dd5f
Author: tangaac <tangyan01 at loongson.cn>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
Log Message:
-----------
[LoongArch] Custom lower vecreduce. (#155196)
Commit: b2a7369631d70df8bcd0c4ee304afa30a0657ba7
https://github.com/llvm/llvm-project/commit/b2a7369631d70df8bcd0c4ee304afa30a0657ba7
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M mlir/docs/Bindings/Python.md
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/Pass.cpp
M mlir/lib/Bindings/Python/TransformInterpreter.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/python/ir/module.py
M mlir/test/python/ir/operation.py
M mlir/test/python/ir/symbol_table.py
M mlir/test/python/pass_manager.py
Log Message:
-----------
[MLIR][Python] remove `liveOperations` (#155114)
Historical context: `PyMlirContext::liveOperations` was an optimization
meant to cut down on the number of Python object allocations and
(partially) a mechanism for updating validity of ops after
transformation. E.g. during walking/transforming the AST. See original
patch [here](https://reviews.llvm.org/D87958).
Inspired by a
[renewed](https://github.com/llvm/llvm-project/pull/139721#issuecomment-3217131918)
interest in https://github.com/llvm/llvm-project/pull/139721 (which has
become a little stale...)
<p align="center">
<img width="504" height="375" alt="image"
src="https://github.com/user-attachments/assets/0daad562-d3d1-4876-8d01-5dba382ab186"
/>
</p>
In the previous go-around
(https://github.com/llvm/llvm-project/pull/92631) there were two issues
which have been resolved
1. ops that were "fetched" under a root op which has been transformed
are no longer reported as invalid. We simply "[formally
forbid](https://github.com/llvm/llvm-project/pull/92631#issuecomment-2119397018)"
this;
2. `Module._CAPICreate(module_capsule)` must now be followed by a
`module._clear_mlir_module()` to prevent double-freeing of the actual
`ModuleOp` object (i.e. calling the dtor on the
`OwningOpRef<ModuleOp>`):
```python
module = ...
module_dup = Module._CAPICreate(module._CAPIPtr)
module._clear_mlir_module()
```
- **the alternative choice** here is to remove the `Module._CAPICreate`
API altogether and replace it with something like `Module._move(module)`
which will do both `Module._CAPICreate` and `module._clear_mlir_module`.
Note, the other approach I explored last year was a [weakref
system](https://github.com/llvm/llvm-project/pull/97340) for
`mlir::Operation` which would effectively hoist this `liveOperations`
thing into MLIR core. Possibly doable but I now believe it's a bad idea.
The other potentially breaking change is `is`, which checks object
equality rather than value equality, will now report `False` because we
are always allocating `new` Python objects (ie that's the whole point of
this change). Users wanting to check equality for `Operation` and
`Module` should use `==`.
Commit: 3219fb098995385d5e97449a898a8aadfc8d6be3
https://github.com/llvm/llvm-project/commit/3219fb098995385d5e97449a898a8aadfc8d6be3
Author: Mythreya Kuricheti <git at mythreya.dev>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Tooling/Tooling.h
M clang/lib/Tooling/Tooling.cpp
M clang/unittests/Sema/HeuristicResolverTest.cpp
Log Message:
-----------
[clang][HeuristicResolver] Test suite: fail if test code does't compile (#155561)
Fixes https://github.com/llvm/llvm-project/issues/155545
Commit: 5cd7d81973510ea86ec49c5ce96e9055737b6c89
https://github.com/llvm/llvm-project/commit/5cd7d81973510ea86ec49c5ce96e9055737b6c89
Author: XChy <xxs_chy at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A llvm/test/tools/llvm-reduce/reduce-bb-callbr.ll
M llvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
Log Message:
-----------
[llvm-reduce] Treat CallBrInst as Branch (#156366)
Fixes the bug of the missing terminator for CallBrInst.
Commit: f91e8d562b3041f0137cbce1d72fe4b5f0d1ce03
https://github.com/llvm/llvm-project/commit/f91e8d562b3041f0137cbce1d72fe4b5f0d1ce03
Author: Muhammad Omair Javaid <omair.javaid at linaro.org>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
R llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
M llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
Log Message:
-----------
Revert "[llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (#142529)"
This reverts commit 2e8ecf7d5fbb4e0d029b0baf94f57f8161b396be.
It is causing clang-aarch64-quick buildbot to fail.
(see:https://lab.llvm.org/buildbot/#/builders/65/builds/22035)
Commit: 6f35a6a088e1c36c6780b3757a8117d23b5f1b92
https://github.com/llvm/llvm-project/commit/6f35a6a088e1c36c6780b3757a8117d23b5f1b92
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/PointerUnion.h
Log Message:
-----------
[ADT] Remove an obsolete forward declaration (NFC) (#156391)
We just removed CastInfoPointerUnionImpl in:
commit 2d216a94f3c84037cdfb3fa5def9efb020a88537
Author: Kazu Hirata <kazu at google.com>
Date: Mon Sep 1 08:04:49 2025 -0700
This patch removes the obsolete forward declaration.
Commit: a36a4019d371c00237c92e6d53f38b897b0fe66c
https://github.com/llvm/llvm-project/commit/a36a4019d371c00237c92e6d53f38b897b0fe66c
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Log Message:
-----------
[InstCombine] Remove unnecessary casts (NFC) (#156394)
These variables are already non const.
Commit: eb89af208828fc62b4a7623a7ac25f6da0bf3bfd
https://github.com/llvm/llvm-project/commit/eb89af208828fc62b4a7623a7ac25f6da0bf3bfd
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-01 (Mon, 01 Sep 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[llvm] Proofread LangRef.rst (#156395)
This patch replaces "i.e. " with "i.e., " to get mechanical changes
out of the way.
Commit: 74b9484fd62d6be9bc49e154800ceef0d74ef24f
https://github.com/llvm/llvm-project/commit/74b9484fd62d6be9bc49e154800ceef0d74ef24f
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__fwd/tuple.h
R libcxx/include/__tuple/make_tuple_types.h
M libcxx/include/__tuple/tuple_element.h
M libcxx/include/__tuple/tuple_like_ext.h
M libcxx/include/__tuple/tuple_size.h
M libcxx/include/module.modulemap.in
M libcxx/include/tuple
Log Message:
-----------
[libc++] Simplify <tuple> further (#156351)
This essentially inlines `__make_tuple_types` and simplifies the support
code. This significantly simplifies the implementation, since
`__make_tuple_types` has multiple features, but the different places
that use it only make use of a subset of the features. Inlining it
separates concerns better and leads to less code in total.
Commit: 8f59a946740bf8dbe2574b33eaa431fde3ce9204
https://github.com/llvm/llvm-project/commit/8f59a946740bf8dbe2574b33eaa431fde3ce9204
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DebugOptions.h
M llvm/lib/Support/TypeSize.cpp
M llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Log Message:
-----------
[IR] Remove options to make scalable TypeSize access a warning (#156336)
This removes the `LLVM_ENABLE_STRICT_FIXED_SIZE_VECTORS` cmake option
and the `-treat-scalable-fixed-error-as-warning` opt flag.
We stopped treating these as warnings by default a long time ago
(62f09d788f9fc540db12f3cfa2f98760071fca96), so I don't think it makes
sense to retain these options at this point. Accessing a scalable
TypeSize as fixed should always result in an error.
Commit: d6edc1a96f6ba06c745bbc733f9e7ce0b44ab71c
https://github.com/llvm/llvm-project/commit/d6edc1a96f6ba06c745bbc733f9e7ce0b44ab71c
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
A llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
Log Message:
-----------
[AMDGPU] Reenable BackOffBarrier on GFX11/12 (#155370)
Re-enable it by adding a wait on vm_vsrc before every barrier "start"
instruction in GFX10/11/12 CU mode.
This is a less strong wait than what we do without BackOffBarrier, thus
this shouldn't introduce
any new guarantees that can be abused, instead it relaxes the guarantees
we have now to the bare
minimum needed to support the behavior users want (fence release +
barrier works).
There is an exact memory model in the works which will be documented
separately.
Commit: a7ff60788df8d86f930c4588c9f2c4130da55630
https://github.com/llvm/llvm-project/commit/a7ff60788df8d86f930c4588c9f2c4130da55630
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/IR/DataLayout.cpp
Log Message:
-----------
[DataLayout] Explicitly call getFixedValue() (NFC)
Instead of relying on the implicit cast. The scalable case has
been explicitly checked beforehand.
Commit: 95e76c14daff1adf5d9a4087d043da4d2a429573
https://github.com/llvm/llvm-project/commit/95e76c14daff1adf5d9a4087d043da4d2a429573
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DebugOptions.h
M llvm/lib/Support/TypeSize.cpp
M llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Log Message:
-----------
Revert "[IR] Remove options to make scalable TypeSize access a warning (#156336)"
This reverts commit 8f59a946740bf8dbe2574b33eaa431fde3ce9204.
Failed on clang-aarch64-sve-vls-2stage, which still uses the option.
Commit: 1cdb8810ce66b79ff1f6efcf72a01ee9ae0d1c5f
https://github.com/llvm/llvm-project/commit/1cdb8810ce66b79ff1f6efcf72a01ee9ae0d1c5f
Author: Mahesh-Attarde <mahesh.attarde at intel.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A llvm/test/CodeGen/X86/isel-ceil.ll
A llvm/test/CodeGen/X86/isel-floor.ll
A llvm/test/CodeGen/X86/isel-ftrunc.ll
Log Message:
-----------
[X86][GlobalIsel] Add ceil/trunc/floor cpp intrinsic test (#156281)
I am working towards supporting G_INTRINSIC_TRUNC, G_FCEIL and G_FFLOOR.
This patch adds isel test for usecase.
Ref
https://llvm.org/docs/GlobalISel/GenericOpcode.html#g-fceil-g-fsqrt-g-ffloor-g-frint-g-fnearbyint
---------
Co-authored-by: mattarde <mattarde at intel.com>
Commit: e09fe9b5aae753c34827c71eea04284c20ed38d3
https://github.com/llvm/llvm-project/commit/e09fe9b5aae753c34827c71eea04284c20ed38d3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Fix adding m0 uses to gfx12 ds atomics (#156399)
Commit: ec40830b3866136d85a6315470e97889e11dc546
https://github.com/llvm/llvm-project/commit/ec40830b3866136d85a6315470e97889e11dc546
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
Log Message:
-----------
[LV] Add test for wrapping in isDereferenceableAndAlignedInLoop.
Commit: f8a53b0b01591ff3e29c390957bff42ab56a55e0
https://github.com/llvm/llvm-project/commit/f8a53b0b01591ff3e29c390957bff42ab56a55e0
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A llvm/test/CodeGen/X86/isel-llvm.acos.ll
A llvm/test/CodeGen/X86/isel-llvm.asin.ll
A llvm/test/CodeGen/X86/isel-llvm.atan.ll
A llvm/test/CodeGen/X86/isel-llvm.atan2.ll
A llvm/test/CodeGen/X86/isel-llvm.cos.ll
A llvm/test/CodeGen/X86/isel-llvm.cosh.ll
A llvm/test/CodeGen/X86/isel-llvm.sin.ll
A llvm/test/CodeGen/X86/isel-llvm.sincos.ll
A llvm/test/CodeGen/X86/isel-llvm.sinh.ll
A llvm/test/CodeGen/X86/isel-llvm.tan.ll
A llvm/test/CodeGen/X86/isel-llvm.tanh.ll
R llvm/test/CodeGen/X86/llvm.acos.ll
R llvm/test/CodeGen/X86/llvm.asin.ll
R llvm/test/CodeGen/X86/llvm.atan.ll
R llvm/test/CodeGen/X86/llvm.atan2.ll
R llvm/test/CodeGen/X86/llvm.cos.ll
R llvm/test/CodeGen/X86/llvm.cosh.ll
R llvm/test/CodeGen/X86/llvm.sin.ll
R llvm/test/CodeGen/X86/llvm.sincos.ll
R llvm/test/CodeGen/X86/llvm.sinh.ll
R llvm/test/CodeGen/X86/llvm.tan.ll
R llvm/test/CodeGen/X86/llvm.tanh.ll
Log Message:
-----------
[X86][NFC] Renamed Trigonometric functions testcases (#156162)
Reference PR -
https://github.com/llvm/llvm-project/pull/155434#discussion_r2310501931
Commit: c4885849adf0addf8c154bfcaf143d959ffda961
https://github.com/llvm/llvm-project/commit/c4885849adf0addf8c154bfcaf143d959ffda961
Author: Ana Mihajlovic <Ana.Mihajlovic at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h
A llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
Log Message:
-----------
[AMDGPU] Fix hw stage metadata setting for unsigned values (#154502)
Commit: ba707db840516b2246c6a31ef8a96e41939deeb5
https://github.com/llvm/llvm-project/commit/ba707db840516b2246c6a31ef8a96e41939deeb5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
M llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
Log Message:
-----------
[X86] getScalarMaskingNode - if the mask is zero just return the blended passthrough and preserved source value (#153575)
We already handle the case if the mask is one, so I added the other case where the op is replaced with a MOVSH/S/D blend.
This assumes the scalar passthrough is op0.
I had to adjust the test case for #98306 as AFAICT it'd been over
reduced
Fixes #153570
Commit: a4739708ebb99a7333658b96a0b328b6bfa0b193
https://github.com/llvm/llvm-project/commit/a4739708ebb99a7333658b96a0b328b6bfa0b193
Author: Gergely Bálint <gergely.balint at arm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M bolt/test/link_fdata.py
M bolt/test/timers.c
Log Message:
-----------
[BOLT] Improve regexp in link_fdata.py (#152694)
FileCheck accepts both '#' and '//' as leading chars for commands, but
link_fdata.py only searched for lines starting with '#'. This changes
the regexps in link_fdata.py to mirror FileCheck's behaviour.
The comment syntax in test/timers.c is modified to present this
capability.
Commit: e867b8511814e75abbbe7048d505f84d4e686961
https://github.com/llvm/llvm-project/commit/e867b8511814e75abbbe7048d505f84d4e686961
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/check-prof-info.ll
Log Message:
-----------
[LV] Always emit branch weights for vector epilogue (#155437)
We currently only emit the branch weights for the epilogue
iteration count check if there was already branch weight
data for the scalar loop. However, the code makes no use
of the existing branch weight when estimating the
likelihood of taking a particular branch and so we can
just always add the branch weights regardless. These
hints should hopefully improve code generation.
Commit: 372a86b4843481aef1da1308ee754d4cfcc75ce1
https://github.com/llvm/llvm-project/commit/372a86b4843481aef1da1308ee754d4cfcc75ce1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Mark DS instructions as fixed size (#156388)
Commit: b7f7d9601010ae3034f1e1d79f446565e2ecbed2
https://github.com/llvm/llvm-project/commit/b7f7d9601010ae3034f1e1d79f446565e2ecbed2
Author: Koustav Chowdhury <kc99.kol at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512dqintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vlbwintrin.h
M clang/lib/Headers/avx512vldqintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Headers/smmintrin.h
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vlbw-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
M clang/test/CodeGen/X86/sse41-builtins.c
Log Message:
-----------
[Headers][X86] Allow SSE2/AVX2/AVX512F/AVX512BW/AVX512DQ integer multiply intrinsics to be used in constexpr (#156369)
Fixes #155411
Commit: a6bd36eb71cf8ad281311f6ea1428a04e8783382
https://github.com/llvm/llvm-project/commit/a6bd36eb71cf8ad281311f6ea1428a04e8783382
Author: Hans Wennborg <hans at chromium.org>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/zero_alloc.cpp
Log Message:
-----------
Mark asan/TestCases/zero_alloc.cpp unsupported on Mac for now
It's failing due to the malloc.h include, see comment on
https://github.com/llvm/llvm-project/pull/155943
Commit: cf444ac2adc45c1079856087b8ba9a04466f78db
https://github.com/llvm/llvm-project/commit/cf444ac2adc45c1079856087b8ba9a04466f78db
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Analysis/Loads.cpp
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
Log Message:
-----------
[Loads] Check for overflow when adding MaxPtrDiff + Offset.
MaxPtrDiff + Offset may wrap, leading to incorrect results. Use uadd_ov
to check for overflow.
Commit: 0fa7733925b66f1fb22ae2734f0a661aac28ef28
https://github.com/llvm/llvm-project/commit/0fa7733925b66f1fb22ae2734f0a661aac28ef28
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopInterchange/profitability-vectorization-heuristic.ll
M llvm/test/Transforms/LoopInterchange/profitability-vectorization.ll
Log Message:
-----------
[LoopInterchange] Improve some tests (NFC) (#156426)
This patch addresses issues in existing test cases that I discovered
while working on DependenceAnalysis.
Details:
- Add `inbounds` to certain `getelementptr` instructions
- Add `nuw`/`nsw` to the instructions that update induction variables
- Fix incorrect type argument in `getelementptr`.
Commit: b96fa9f3ac57df001b38c1f6a21ca92c4615e58a
https://github.com/llvm/llvm-project/commit/b96fa9f3ac57df001b38c1f6a21ca92c4615e58a
Author: Kajetan Puchalski <kajetan.puchalski at arm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
Log Message:
-----------
[clang][AArch64] Use .i16.f16 intrinsic formats for vcvth*_[s|u]16_f16 (#156029)
Use .i16.f16 intrinsic formats for intrinsics like vcvth_s16_f16.
Avoids issues with incorrect saturation that arise when using .i32.f16
formats for the same conversions.
Fixes https://github.com/llvm/llvm-project/issues/154343.
Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>
Commit: abda8bed95dc3e8d3928288ac9b1e669b406cfe5
https://github.com/llvm/llvm-project/commit/abda8bed95dc3e8d3928288ac9b1e669b406cfe5
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/InferAlignment.cpp
A llvm/test/Transforms/InferAlignment/masked.ll
Log Message:
-----------
[InferAlignment] Increase alignment in masked load / store instrinsics if known (#156057)
Summary:
The masked load / store LLVM intrinsics take an argument for the
alignment. If the user is pessimistic about alignment they can provide a
value of `1` for an unaligned load. This patch updates infer-alignment
to
increase the alignment value of the alignment argument if it is known
greater than the provided one.
Ignoring the gather / scatter versions for now since they contain many
pointers.
Commit: eb7b162ea06091a1bc8b976ae43ee62783dc9fef
https://github.com/llvm/llvm-project/commit/eb7b162ea06091a1bc8b976ae43ee62783dc9fef
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/algorithm.h
A libc/src/__support/CPP/simd.h
M libc/src/__support/macros/attributes.h
M libc/src/__support/macros/properties/cpu_features.h
M libc/src/string/CMakeLists.txt
A libc/src/string/memory_utils/generic/inline_strlen.h
M libc/src/string/string_utils.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc] Implement generic SIMD helper 'simd.h' and implement strlen (#152605)
Summary:
This PR introduces a new 'simd.h' header that implements an interface
similar to the proposed `stdx::simd` in C++. However, we instead wrap
around the LLVM internal type. This makes heavy use of the clang vector
extensions and boolean vectors, instead using primitive vector types
instead of a class (many benefits to this).
I use this interface to implement a generic strlen implementation, but
propse we use this for math. Right now this requires a feature only
introduced in clang-22.
Commit: d8fd51148069bdea95974b3877abc31bcf5bf5ab
https://github.com/llvm/llvm-project/commit/d8fd51148069bdea95974b3877abc31bcf5bf5ab
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call-scalarize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-uniform-call.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
M llvm/test/Transforms/LoopVectorize/pr36983-multiple-lcssa.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
Log Message:
-----------
[VPlan] Introduce CSE pass (#151872)
Introduce a simple common-subexpression-elimination pass at the
VPlan-level, running late during the execution of the VPlan. The
long-term vision is to get rid of the legacy non-VPlan-based cse routine
in LV, but this patch doesn't yet fully subsume it.
Commit: 1af19772e62419809326b67994dc727e237994c2
https://github.com/llvm/llvm-project/commit/1af19772e62419809326b67994dc727e237994c2
Author: Wu Yingcong <yingcong.wu at intel.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libunwind/test/eh_frame_fde_pc_range.pass.cpp
Log Message:
-----------
[libunwind][test] set fed test to require x86 as others arch may have cross toolchain build (#156383)
In https://github.com/llvm/llvm-project/pull/154902, the test failed
with llvm-clang-win-x-aarch64(it is a cross-build, which builds on
Windows and run on Linux, "Win to Aarch64 Linux Ubuntu Cross
Toolchain"), and objdump is not available on Windows(the build env).
Set to require x86 Linux instead.
Commit: 8e4bda15b5779a6124f97f77481af4249270a961
https://github.com/llvm/llvm-project/commit/8e4bda15b5779a6124f97f77481af4249270a961
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/src/__support/macros/attributes.h
Log Message:
-----------
[libc] Fix missing has feature for older GCC
Commit: 8a820f133aa00557498d666a901003d1c4f64f00
https://github.com/llvm/llvm-project/commit/8a820f133aa00557498d666a901003d1c4f64f00
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/Dialect/Ptr/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.h
M mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrs.h
A mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.h
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
A mlir/include/mlir/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.h
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
A mlir/lib/Dialect/Ptr/IR/MemorySpaceInterfaces.cpp
M mlir/lib/Dialect/Ptr/IR/PtrAttrs.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
A mlir/lib/Target/LLVMIR/Dialect/Ptr/CMakeLists.txt
A mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/TypeToLLVM.cpp
A mlir/test/Dialect/LLVMIR/ptr.mlir
M mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
A mlir/test/Target/LLVMIR/ptr.mlir
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
Log Message:
-----------
[mlir][LLVM|ptr] Add the `#llvm.address_space` attribute, and allow `ptr` translation (#156333)
This commit introduces the `#llvm.address_space` attribute. This
attribute implements the `ptr::MemorySpaceAttrInterface`, establishing
the semantics of the LLVM address space.
This allows making `!ptr.ptr` translatable to LLVM IR as long it uses
the `#llvm.address_space` attribute.
Concretely, `!ptr.ptr<#llvm.address_space<N>>` now translates to `ptr
addrspace(N)`.
Additionally, this patch makes `PtrLikeTypes` with no metadata, no
element type, and with `#llvm.address_space` memory space, compatible
with the LLVM dialect.
**Infrastructure Updates:**
- Refactor `ptr::MemorySpaceAttrInterface` to include DataLayout
parameter for better validation
- Add new utility functions `LLVM::isLoadableType()` and
`LLVM::isTypeCompatibleWithAtomicOp()`
- Update type compatibility checks to support ptr-like types with LLVM
address spaces
- Splice the `MemorySpaceAttrInterface` to its own library, so the
LLVMDialect won't depend on the PtrDialect yet
**Translation Support:**
- New `PtrToLLVMIRTranslation` module for converting ptr dialect to LLVM
IR
- Type translation support for ptr types with LLVM address spaces
- Proper address space preservation during IR lowering
Example:
```mlir
llvm.func @llvm_ops_with_ptr_values(%arg0: !llvm.ptr) {
%1 = llvm.load %arg0 : !llvm.ptr -> !ptr.ptr<#llvm.address_space<1>>
llvm.store %1, %arg0 : !ptr.ptr<#llvm.address_space<1>>, !llvm.ptr
llvm.return
}
```
Translates to:
```llvmir
; ModuleID = 'LLVMDialectModule'
source_filename = "LLVMDialectModule"
define void @llvm_ops_with_ptr_values(ptr %0) {
%2 = load ptr addrspace(1), ptr %0, align 8
store ptr addrspace(1) %2, ptr %0, align 8
ret void
}
!llvm.module.flags = !{!0}
!0 = !{i32 2, !"Debug Info Version", i32 3}
```
Commit: 132173972a02d892d27935a23d3987277c84cbea
https://github.com/llvm/llvm-project/commit/132173972a02d892d27935a23d3987277c84cbea
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
Log Message:
-----------
AVR: Do not add target specific STI member to AVRAsmParser (#156442)
The base class has a pointer STI member already; the target subclass
had a reference with the same name. Just use the base class field.
Commit: 11f4be022a80466682e5392301137a50f7c34ce8
https://github.com/llvm/llvm-project/commit/11f4be022a80466682e5392301137a50f7c34ce8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
Log Message:
-----------
MSP430: Do not add target specific STI member to MSP430AsmParser (#156443)
The base class already has an STI pointer member, so use that.
Commit: c945022f2fd8321559d84e2272005487c5ced924
https://github.com/llvm/llvm-project/commit/c945022f2fd8321559d84e2272005487c5ced924
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.h
M mlir/lib/Conversion/NVVMToLLVM/NVVMToLLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[MLIR][NVVM] Support packed registers in `inline_ptx` (#154904)
Add support for packed registers with vectors.
Example:
```
%wo0 = nvvm.inline_ptx
"dp4a.s32.s32 {$w0}, {$r0}, {$r1}, {$r2};"
ro(%src, %mask, %zero : vector<4xi8>, i32, i32)
-> i32
```
Here, `vector<4xi8>` is lowered to an `i32` register (i.e., an `r` in
PTX).
Commit: 6042e090fac8b06d64666348fe4ca6ca6e4f77db
https://github.com/llvm/llvm-project/commit/6042e090fac8b06d64666348fe4ca6ca6e4f77db
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in Deserializer.cpp (NFC)
Commit: 7abbb0e70099cb4ae3328859ee8c74627501a8d8
https://github.com/llvm/llvm-project/commit/7abbb0e70099cb4ae3328859ee8c74627501a8d8
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for 3219fb098995385d5e97449a898a8aadfc8d6be3
Commit: 6f5f264528f3b4d4fe7d7469e760e921655457d8
https://github.com/llvm/llvm-project/commit/6f5f264528f3b4d4fe7d7469e760e921655457d8
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
[bazel] Port 8a820f133aa00557498d666a901003d1c4f64f00
Commit: a65aa32a3bf153204ff51c23d432a2497533a656
https://github.com/llvm/llvm-project/commit/a65aa32a3bf153204ff51c23d432a2497533a656
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for 8e4bda15b5779a6124f97f77481af4249270a961
Commit: 9a1e47839a331be303cb5b8ec034bfa53cc30f8a
https://github.com/llvm/llvm-project/commit/9a1e47839a331be303cb5b8ec034bfa53cc30f8a
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Analysis/Loads.cpp
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size-needs-loop-guards.ll
Log Message:
-----------
[Loads] Apply loop guards to maximum pointer difference.
Applying loop guards to MaxPtrDiff can improve results in some cases.
Commit: 73704052b479cd584fe7ff9d84dd299da5d02be5
https://github.com/llvm/llvm-project/commit/73704052b479cd584fe7ff9d84dd299da5d02be5
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for bugprone-argument-comment in ConvertToDestinationStyle.cpp (NFC)
Commit: c3f8c340d7b6aef7d9bf7facccfe34dc8a353332
https://github.com/llvm/llvm-project/commit/c3f8c340d7b6aef7d9bf7facccfe34dc8a353332
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir][debug] Inherit DISubprogramAttr from DILocalScopeAttr. (#156081)
As mentioned in https://github.com/llvm/llvm-project/pull/154926,
`DISubprogramAttr` is inherited from `DIScopeAttr` while in llvm, the
`DISubprogram` inherits from `DILocalScope`. This change corrects the
hierarchy.
Also does the same change for `DILexicalBlockAttr` and `DILexicalBlockFileAttr`.
Commit: 3ee6170210796ae2837407cf46bf6cd02a6a3316
https://github.com/llvm/llvm-project/commit/3ee6170210796ae2837407cf46bf6cd02a6a3316
Author: Ellis Kesterton <ellis.kesterton at proton.me>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512fp16intrin.h
M clang/lib/Headers/avxintrin.h
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512fp16-builtins.c
Log Message:
-----------
Allow vector zero padding intrinsics to be used in constexpr (#156441)
Fix #156346 by marking intrinsics as constexpr. A test has been added
for each intrinsic.
The following instrinsics have been modified:
```
_mm256_zextpd128_pd256
_mm512_zextpd128_pd512
_mm512_zextpd256_pd512
_mm256_zextph128_ph256
_mm512_zextph128_ph512
_mm512_zextph256_ph512
_mm256_zextps128_ps256
_mm512_zextps128_ps512
_mm512_zextps256_ps512
_mm256_zextsi128_si256
_mm512_zextsi128_si512
_mm512_zextsi256_si512
```
Commit: 36cb33bbcae8a7f988e101f5c9b23e7c68f73808
https://github.com/llvm/llvm-project/commit/36cb33bbcae8a7f988e101f5c9b23e7c68f73808
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
M llvm/test/CodeGen/ARM/cmpxchg-idioms.ll
M llvm/test/CodeGen/ARM/cmpxchg-weak.ll
M llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll
M llvm/test/CodeGen/PowerPC/atomic-float.ll
M llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/PowerPC/atomics-regression.ll
M llvm/test/CodeGen/PowerPC/atomics.ll
M llvm/test/CodeGen/PowerPC/loop-comment.ll
M llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll
M llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll
M llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll
Log Message:
-----------
support branch hint for AtomicExpandImpl::expandAtomicCmpXchg (#152366)
The patch add branch hint for AtomicExpandImpl::expandAtomicCmpXchg, For
example: in PowerPC, it support branch hint as
```
loop:
lwarx r6,0,r3 # load and reserve
cmpw r4,r6 #1st 2 operands equal? bne- exit #skip if not
bne- exit #skip if not
stwcx. r5,0,r3 #store new value if still res’ved bne- loop #loop if lost reservation
bne- loop #loop if lost reservation
exit:
mr r4,r6 #return value from storage
```
`-` hints not taken,
`+` hints taken,
Commit: 417bdb6672b891000bfa1ec3613074acf03f2616
https://github.com/llvm/llvm-project/commit/417bdb6672b891000bfa1ec3613074acf03f2616
Author: Jamie Schmeiser <schmeise at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A llvm/test/ExecutionEngine/JITLink/lit.local.cfg
A llvm/test/ExecutionEngine/Orc/lit.local.cfg
Log Message:
-----------
Mark ExecutionEngine/JITLink and ExecutionEngine/Orc as unsupported on AIX (#156076)
Create ExecutionEngine/JitLink/lit.local.cfg and
ExecutionEngine/Orc/lit.local.cfg and use them to mark tests as
unsupported on AIX.
Commit: 89f53af3fffed3e41167fbb7bc10d4885cd97c7f
https://github.com/llvm/llvm-project/commit/89f53af3fffed3e41167fbb7bc10d4885cd97c7f
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/implied-by-bounded-memory-access.ll
Log Message:
-----------
[ConstraintElim] Use constraints from bounded memory accesses (#155253)
This patch removes bound checks that are dominated by bounded memory
accesses. For example, if we have an array `int A[5]` and `A[idx]` is
performed successfully, we know that `idx u< 5` after the load.
compile-time impact (+0.1%):
https://llvm-compile-time-tracker.com/compare.php?from=f0e9bba024d44b55d54b02025623ce4a3ba5a37c&to=5227b08a4a514159ec524d1b1ca18ed8ab5407df&stat=instructions%3Au
llvm-opt-benchmark:
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/2709
Proof: https://alive2.llvm.org/ce/z/JEyjA2
Commit: 45dec71725bd57831051c27e43da698c23de1a52
https://github.com/llvm/llvm-project/commit/45dec71725bd57831051c27e43da698c23de1a52
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/test/Transforms/LICM/hoist-speculatable-load.ll
A llvm/test/Verifier/nofree_metadata.ll
Log Message:
-----------
[IR] Allow nofree metadata to inttoptr (#153149)
Our GPU compiler usually construct pointers through inttoptr. The memory
was pre-allocated before the shader function execution and remains valid
through the execution of the shader function. This brings back the
expected behavior of instruction hoisting for the test
`hoist-speculatable-load.ll`, which was broken by #126117.
Commit: e591df63e583a39b2b8356dae7024df82d2f2204
https://github.com/llvm/llvm-project/commit/e591df63e583a39b2b8356dae7024df82d2f2204
Author: David Spickett <david.spickett at linaro.org>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/utils/release/github-upload-release.py
Log Message:
-----------
[release] Correct download links for Windows on Arm packages (#156459)
Mistakenly repeated the https://github.com... part twice.
Found while editing the links for 21.1.0.
Commit: 1ff6bfe7a5c672a7349a5a619d44b4892c8b7f74
https://github.com/llvm/llvm-project/commit/1ff6bfe7a5c672a7349a5a619d44b4892c8b7f74
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
Log Message:
-----------
AMDGPU: Add VS_64_Align2 class (#156132)
We need an aligned version of the VS class to properly
represent operand constraints.
This fixes regressions with #155559
Commit: 0196d7ec6988c39fa08ba296d28ffb00494f2834
https://github.com/llvm/llvm-project/commit/0196d7ec6988c39fa08ba296d28ffb00494f2834
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/MC/MCDecoder.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[MC][DecoderEmitter] Fix build warning: explicit specialization cannot have a storage class (#156375)
Move `InsnBitWidth` template into anonymous namespace in the generated
code and move template specialization of `InsnBitWidth` to anonymous
namespace as well, and drop `static` for them. This makes `InsnBitWidth`
completely private to each target and fixes the "explicit specialization
cannot have a storage class" warning as well as any potential linker
errors if `InsnBitWidth` is kept in the `llvm::MCD` namespace.
Commit: 569d738d4e58dea13bac9864b16eb6b6ac0afa30
https://github.com/llvm/llvm-project/commit/569d738d4e58dea13bac9864b16eb6b6ac0afa30
Author: Sam Tebbs <samuel.tebbs at arm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/docs/LangRef.rst
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/SVEInstrFormats.td
A llvm/test/CodeGen/AArch64/alias_mask.ll
A llvm/test/CodeGen/AArch64/alias_mask_nosve.ll
A llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
A llvm/test/CodeGen/AArch64/alias_mask_scalable_nosve2.ll
Log Message:
-----------
[Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (#117007)
It can be unsafe to load a vector from an address and write a vector to
an address if those two addresses have overlapping lanes within a
vectorised loop iteration.
This PR adds intrinsics designed to create a mask with lanes disabled if
they overlap between the two pointer arguments, so that only safe lanes
are loaded, operated on and stored. The `loop.dependence.war.mask`
intrinsic represents cases where the store occurs after the load, and
the opposite for `loop.dependence.raw.mask`. The distinction between
write-after-read and read-after-write is important, since the ordering
of the read and write operations affects if the chain of those
instructions can be done safely.
Along with the two pointer parameters, the intrinsics also take an
immediate that represents the size in bytes of the vector element types.
This will be used by #100579.
Commit: 314dc33e4dccda18661472956f1990389db111d3
https://github.com/llvm/llvm-project/commit/314dc33e4dccda18661472956f1990389db111d3
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/utils/UpdateTestChecks/asm.py
Log Message:
-----------
[Utils] Fix AArch64 ASM regex after #148287 (#156460)
PR #148287 removed the "\s*" before ".Lfunc_end" for AArch64, which
broke `update_llc_test_checks.py` for a number of tests including:
- `llvm/test/CodeGen/AArch64/sme-za-exceptions.ll`
- `llvm/test/CodeGen/AArch64/win-sve.ll`
This patch adds the "\s*" back.
Commit: 6d902b67cdae224c0a5f4e13097a82d3148c8198
https://github.com/llvm/llvm-project/commit/6d902b67cdae224c0a5f4e13097a82d3148c8198
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
Revert "[SLP]Improved/fixed FMAD support in reductions"
This reverts commit 74230ff2791384fb3285c9e9ab202056959aa095 to fix the
bugs found during local testing.
Commit: 5f38548c86c3e7bbfce3a739245d8f999e9946b5
https://github.com/llvm/llvm-project/commit/5f38548c86c3e7bbfce3a739245d8f999e9946b5
Author: Vladimir Vuksanovic <109677816+vvuksanovic at users.noreply.github.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/test/Analysis/Malloc+MismatchedDeallocator+NewDelete.cpp
M clang/test/Analysis/Malloc+MismatchedDeallocator_intersections.cpp
M clang/test/Analysis/MismatchedDeallocator-checker-test.mm
M clang/test/Analysis/NewDelete-checker-test.cpp
M clang/test/Analysis/NewDelete-intersections.mm
M clang/test/Analysis/unix-fns.c
M clang/test/Sema/warn-alloc-size.c
Log Message:
-----------
[Sema] Allow zero-size allocations for -Walloc-size (#155793)
Allocations of size zero are usually done intentionally and then
reallocated before use.
Fixes #155633
Commit: 66fdde3612f28d3460d4946c3d29a5e68e762e51
https://github.com/llvm/llvm-project/commit/66fdde3612f28d3460d4946c3d29a5e68e762e51
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/tools/mlir-tblgen/mlir-tblgen.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in mlir-tblgen.cpp (NFC)
Commit: 8dee9e465bac6f1f85d37820f8ee15b5bd2118a6
https://github.com/llvm/llvm-project/commit/8dee9e465bac6f1f85d37820f8ee15b5bd2118a6
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-identifier-naming in ParallelLoopFusion.cpp (NFC)
Commit: cb80fa756c4fcbc4f5deba16da857ed309e044cf
https://github.com/llvm/llvm-project/commit/cb80fa756c4fcbc4f5deba16da857ed309e044cf
Author: XChy <xxs_chy at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/bitop-of-castops.ll
Log Message:
-----------
[VectorCombine] Support pattern `bitop(bitcast(x), C) -> bitcast(bitop(x, InvC))` (#155216)
Resolves #154797.
This patch adds the fold `bitop(bitcast(x), C) -> bitop(bitcast(x),
cast(InvC)) -> bitcast(bitop(x, InvC))`.
The helper function `getLosslessInvCast` tries to calculate the constant
`InvC`, satisfying `castop(InvC) == C`, and will try its best to keep
the poison-generated flags of the cast operation.
Commit: 85136993b6aea653bf78b8f1eb86a49ada9c02c7
https://github.com/llvm/llvm-project/commit/85136993b6aea653bf78b8f1eb86a49ada9c02c7
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
Log Message:
-----------
[OpenACC] 'reduction' 'one-init' lowering, */&& operators. (#156122)
The * and && operators of a reduction require a starting value of '1'.
This patch implements that by looping through every type and creating an
init-list that puts a 1 in place of every initializer.
This patch will be followed up by a patch that generalizes this, as
`min`, `max`, and `&` all have different initial values.
Commit: bde2abd3a6299dc60fd6ec6726b77808d0c17dbd
https://github.com/llvm/llvm-project/commit/bde2abd3a6299dc60fd6ec6726b77808d0c17dbd
Author: Richard Howell <rmaz at users.noreply.github.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Frontend/FrontendAction.cpp
A clang/test/Modules/Inputs/umbrella_header_order/module.modulemap
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/A.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/B.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/C.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/D.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/E.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/F.h
A clang/test/Modules/umbrella_dir_order.m
Log Message:
-----------
[clang] load umbrella dir headers in sorted order (#156108)
Clang modules sort the umbrella dir headers by name before adding to the
module's includes to ensure deterministic output across different file
systems.
This is insufficient however, as the header search table is also
serialized.
This includes all the loaded headers by file reference, which are
allocated
incrementally. To ensure stable output we have to also create the file
references in sorted order.
Commit: e96ff4530fa0111fccf2687a4e2a55bbe0f73554
https://github.com/llvm/llvm-project/commit/e96ff4530fa0111fccf2687a4e2a55bbe0f73554
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
Log Message:
-----------
[clang][bytecode] Lazily create DynamicAllocator (#155831)
Due to all the tracking via map(s) and a BumpPtrAllocator, the creating
and destroying the DynamicAllocator is rather expensive. Try to do it
lazily and only create it when first calling
InterpState::getAllocator().
Commit: 8c958c2be9d8febc4524de190c94c7f66ece82cc
https://github.com/llvm/llvm-project/commit/8c958c2be9d8febc4524de190c94c7f66ece82cc
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/MC/AMDGPU/vop3-literal.s
Log Message:
-----------
[AMDGPU] Autogenerate VOP3 literal checks (#156038)
Commit: 96c277619ca452983b51fa7df99a3c8841030aec
https://github.com/llvm/llvm-project/commit/96c277619ca452983b51fa7df99a3c8841030aec
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A clang/test/Modules/implicit-opt-level.c
R llvm/clang/test/Modules/implicit-opt-level.c
Log Message:
-----------
[llvm][clang] Move a stray test into the Clang subdirectory
Commit: ad4594effd8fbe6aa1f796a57b1ef01b4ddd8230
https://github.com/llvm/llvm-project/commit/ad4594effd8fbe6aa1f796a57b1ef01b4ddd8230
Author: Teresa Johnson <tejohnson at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
Log Message:
-----------
[MemProf] Allow hint update on existing calls to nobuiltin hot/cold new (#156476)
Explicit calls to ::operator new are marked nobuiltin and cannot be
elided or updated as they may call user defined versions. However,
existing calls to the hot/cold versions of new only need their hint
parameter value updated, which does not mutate the call.
Commit: 96e4caadb49e4810a70b477279bf12f205ff1431
https://github.com/llvm/llvm-project/commit/96e4caadb49e4810a70b477279bf12f205ff1431
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
Log Message:
-----------
AMDGPU: Stop special casing aligned VGPR targets in operand folding (#155559)
Perform a register class constraint check when performing the fold
Commit: 62447efa733eab7f2ce6573a3731fd4cf8db1912
https://github.com/llvm/llvm-project/commit/62447efa733eab7f2ce6573a3731fd4cf8db1912
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
A clang/test/CodeGen/complex_Float16.c
M clang/test/Sema/Float16.c
M clang/test/Sema/fp16-sema.c
M clang/test/Sema/riscv-fp16.c
Log Message:
-----------
[Clang] Permit half precision in `__builtin_complex` (#156479)
Summary:
This was forbidden previously, which made us divergent with the GCC
implementation. Permit this by simply removing this Sema check.
Fixes: https://github.com/llvm/llvm-project/issues/156463
Commit: e3e1652d1875c23c794b17250d5fee6a7b076500
https://github.com/llvm/llvm-project/commit/e3e1652d1875c23c794b17250d5fee6a7b076500
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
Log Message:
-----------
AMDGPU: Add version of isImmOperandLegal for MCInstrDesc (#155560)
This avoids the need for a pre-constructed instruction, at least
for the first argument.
Commit: bb54be585370cc281e60fb6973062004f200c9d3
https://github.com/llvm/llvm-project/commit/bb54be585370cc281e60fb6973062004f200c9d3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
Log Message:
-----------
AMDGPU: Fix DPP combiner using isOperandLegal on incomplete inst (#155595)
It is not safe to use isOperandLegal on an instruction that does
not have a complete set of operands. Unforunately the APIs are
not set up in a convenient way to speculatively check if an instruction
will be legal in a hypothetical instruction. Build all the operands
and then verify they are legal after. This is clumsy, we should have
a more direct check for will these operands give a legal instruction.
This seems to fix a missed optimization in the gfx11 test. The
fold was firing for gfx1150, but not gfx1100. Both should support
vop3 literals so I'm not sure why it wasn't working before.
Commit: 02473587fb1d5192f5e3aa089445902f9e7ee30e
https://github.com/llvm/llvm-project/commit/02473587fb1d5192f5e3aa089445902f9e7ee30e
Author: Alex Guteniev <gutenev at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.cons/move_assign_noexcept.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.erasure/erase_if_exceptions.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.cons/move_assign_noexcept.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.erasure/erase_if_exceptions.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.set/flat.set.erasure/erase_if_exceptions.pass.cpp
Log Message:
-----------
[libcxx][test] Avoid warnings about unused variables and typedefs if `_LIBCPP_VERSION` is not defined (#155679)
Make these tests pass with MSVC STL
Commit: 8bc2eb869cf41acc6f08308bdd4da99f55feb9a8
https://github.com/llvm/llvm-project/commit/8bc2eb869cf41acc6f08308bdd4da99f55feb9a8
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/unittests/ProfileData/InstrProfTest.cpp
Log Message:
-----------
[memprof] Rename "v2" functions and tests (NFC) (#156247)
I'm planning to remove the V2 support. Now, some functions and tests
should not be removed just because they have "v2" in their names.
This patch renames them.
- makeRecordV2: Renamed to makeRecord. This has "V2" in the name
because the concept of call stack ID came out as part of V2. It is
still useful for use with V3 and V4.
- test_memprof_v4_{partial,full}_schema: Upgraded to use V4. These
tests perform serialization/deserialization roundtrip tests of a
MemProfRecord with {partial,full} schema.
Commit: 5e91314b9bfb79855314d53713a893be400f7d10
https://github.com/llvm/llvm-project/commit/5e91314b9bfb79855314d53713a893be400f7d10
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/APInt.h
Log Message:
-----------
[ADT] Improve a comment in APInt.h (#156390)
We don't have to remove this constructor if we are worried about
accidental binding. We can use "= delete" instead. Also, this patch
replaces "captured by" with "bound to" as that is more precise.
Commit: 2a49ebf0ebce2e8157c5ac35ec27c6195b61c68a
https://github.com/llvm/llvm-project/commit/2a49ebf0ebce2e8157c5ac35ec27c6195b61c68a
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/StringMap.h
Log Message:
-----------
[ADT] Simplify StringMapIterBase (NFC) (#156392)
In open-adressing hash tables, begin() needs to advance to the first
valid element. We don't need to do the same for any other operations
like end(), find(), and try_emplace().
The problem is that the constructor of StringMapIterBase says:
bool NoAdvance = false
This increases the burden on the callers because most places need to
pass true for NoAdvance, defeating the benefit of the default
parameter.
This patch fixes the problem by changing the name and default to:
bool Advance = false
and adjusting callers. Again, begin() is the only caller that
specifies this parameter.
This patch fixes a "latent bug" where try_emplace() was requesting
advancing even on a successful insertion. I say "latent" because the
request is a no-op on success.
Commit: 9f7bb1c42c3011dab48e8de86e4d151d75747aef
https://github.com/llvm/llvm-project/commit/9f7bb1c42c3011dab48e8de86e4d151d75747aef
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.h
M clang/lib/CIR/Dialect/IR/CIRDataLayout.cpp
M clang/test/CIR/CodeGen/vtt.cpp
Log Message:
-----------
[CIR] Add support for emitting VTTs and related ojects (#155721)
This adds support for emitting virtual table tables (VTTs) and
construction vtables.
Commit: 83f390859e186d22af8aa32135d7993079ed4666
https://github.com/llvm/llvm-project/commit/83f390859e186d22af8aa32135d7993079ed4666
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
Log Message:
-----------
[AMDGPU] Fix a warning
This patch fixes:
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:298:9: error: unused
variable 'Src0Idx' [-Werror,-Wunused-variable]
Commit: e4a1b5f36e71c8c382bdd531867c5f6eb3f7deac
https://github.com/llvm/llvm-project/commit/e4a1b5f36e71c8c382bdd531867c5f6eb3f7deac
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang-tools-extra/clangd/XRefs.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Scope.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Basic/LangOptions.cpp
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/Scope.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
A clang/test/AST/ast-dump-labeled-break-continue-json.c
A clang/test/AST/ast-dump-labeled-break-continue.c
A clang/test/AST/ast-print-labeled-break-continue.c
M clang/test/Analysis/cfg.c
A clang/test/CodeGen/labeled-break-continue.c
A clang/test/CodeGenCXX/labeled-break-continue.cpp
A clang/test/CodeGenObjC/labeled-break-continue.m
M clang/test/OpenMP/for_loop_messages.cpp
A clang/test/Parser/labeled-break-continue.c
M clang/test/Sema/__try.c
A clang/test/Sema/labeled-break-continue.c
A clang/test/SemaCXX/labeled-break-continue-constexpr.cpp
A clang/test/SemaCXX/labeled-break-continue.cpp
A clang/test/SemaObjC/labeled-break-continue.m
M clang/test/SemaOpenACC/no-branch-in-out.c
M clang/www/c_status.html
Log Message:
-----------
[Clang] [C2y] Implement N3355 ‘Named Loops’ (#152870)
This implements support for [named
loops](https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3355.htm) for
C2y.
When parsing a `LabelStmt`, we create the `LabeDecl` early before we parse
the substatement; this label is then passed down to `ParseWhileStatement()`
and friends, which then store it in the loop’s (or switch statement’s) `Scope`;
when we encounter a `break/continue` statement, we perform a lookup for
the label (and error if it doesn’t exist), and then walk the scope stack and
check if there is a scope whose preceding label is the target label, which
identifies the jump target.
The feature is only supported in C2y mode, though a cc1-only option
exists for testing (`-fnamed-loops`), which is mostly intended to try
and make sure that we don’t have to refactor this entire implementation
when/if we start supporting it in C++.
---------
Co-authored-by: Balazs Benics <benicsbalazs at gmail.com>
Commit: 3e5f49af266e3c277a794b724cd6d115a0d5766c
https://github.com/llvm/llvm-project/commit/3e5f49af266e3c277a794b724cd6d115a0d5766c
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
R clang/test/CIR/CodeGen/complex-arithmetic.cpp
A clang/test/CIR/CodeGen/complex-plus-minus.cpp
Log Message:
-----------
[CIR][NFC] Reorder GenExprComplex and add errors for unhandled visitors (#156241)
- Reorder the CIRGenExprComplex functions to be similar to OCG.
- Add errors for unhandled visitors.
- Rename the test file to be similar to `complex-mul-div`.
Issue: https://github.com/llvm/llvm-project/issues/141365
Commit: 6c3db644eda97cf8461b03728ccd361e920da52b
https://github.com/llvm/llvm-project/commit/6c3db644eda97cf8461b03728ccd361e920da52b
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
Log Message:
-----------
[RISCV] Use slideup to lower build_vector when all operand are (extract_element X, 0) (#154450)
The general lowering of build_vector starts with splatting the first
operand before sliding down other operands one-by-one. However, if the
every operands is an extract_element from the first vector element, we
could use the original _vector_ (source of extraction) from the last
build_vec operand as start value before sliding up other operands (in
reverse order) one-by-one. By doing so we can avoid the initial splat
and eliminate the vector to scalar movement later, which is something we
cannot do with vslidedown/vslide1down.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Co-authored-by: Luke Lau <luke at igalia.com>
Commit: 62fd3320850c7632109b1f282d2db1fb89d9b453
https://github.com/llvm/llvm-project/commit/62fd3320850c7632109b1f282d2db1fb89d9b453
Author: Nimit Sachdeva <31580737+nimit25 at users.noreply.github.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
A llvm/test/Transforms/InstCombine/usub_sat_to_msb_mask.ll
Log Message:
-----------
[InstCombine] Optimize usub.sat pattern (#151044)
Fixes #79690
Generalized proof: https://alive2.llvm.org/ce/z/22ybrr
---------
Co-authored-by: Nimit Sachdeva <nimsach at amazon.com>
Commit: c1ae38145399cbe49a03e0661e44cf574a044bbe
https://github.com/llvm/llvm-project/commit/c1ae38145399cbe49a03e0661e44cf574a044bbe
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
Log Message:
-----------
[RISCV][VLOPT][NFC] Remove outdated FIXME comments related to supported instructions (#156126)
Remove several FIXME comments in `isSupportedInstr` for opcodes that
were already implemented. Also moved switch cases for
add-carry/sub-borrow instructions together.
NFC.
Commit: 036b33d4d9ecf00bab7a803d26e4c9361136aa63
https://github.com/llvm/llvm-project/commit/036b33d4d9ecf00bab7a803d26e4c9361136aa63
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/X86/fpenv.ll
A llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
Log Message:
-----------
[X86][NFC] Moved/Updated llvm.set.rounding testcases (#155434)
- Moved llvm.set.rounding testcases from llvm/test/CodeGen/X86/fpenv.ll to
llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll.
- Added GlobalIsel RUNs as precommit test and will add llvm.set.rounding
GISEL implementation PR after this merge.
Commit: 51a1aab6438aa33b15ff7e85bc8609b5ff003764
https://github.com/llvm/llvm-project/commit/51a1aab6438aa33b15ff7e85bc8609b5ff003764
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/include/mlir/Dialect/Math/Transforms/Passes.h
M mlir/include/mlir/Dialect/Math/Transforms/Passes.td
M mlir/lib/Dialect/Math/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Math/Transforms/ExpandOps.cpp
R mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/Dialect/Math/ops.mlir
M mlir/test/lib/Dialect/Math/CMakeLists.txt
R mlir/test/lib/Dialect/Math/TestExpandMath.cpp
M mlir/test/mlir-runner/test-expand-math-approx.mlir
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir][math] Add `clampf` and clean math `ExpandOps` API (#151153)
This patch adds the `clampf` operation to the math dialect. The
semantics op are defined as:
```
clampf(x, min_v, max_v) = max(min(x, min_v), max_v)
```
The reasoning behind adding this operation is that some GPU vendors
offer specialized intrinsics for this operation, or subsets of this
operation. For example,
[__saturatef](https://docs.nvidia.com/cuda/cuda-math-api/cuda_math_api/group__CUDA__MATH__INTRINSIC__SINGLE.html#group__cuda__math__intrinsic__single_1ga2c84f08e0db7117a14509d21c3aec04e)
in NVIDIA GPUs, or `__builtin_amdgcn_fmed3f` in AMD GPUs.
This patch also removes `test-expand-math` in favor of
`math-expand-ops`.
Finally, it removes individual expansion population API calls like
`populateExpandCoshPattern` in favor of:
```C++
void populateExpansionPatterns(RewritePatternSet &patterns,
ArrayRef<StringRef> opMnemonics = {});
```
Commit: 7c96eacbc7cbf319d743b3eb1491e1a48e4ec984
https://github.com/llvm/llvm-project/commit/7c96eacbc7cbf319d743b3eb1491e1a48e4ec984
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
Log Message:
-----------
[OpenACC] Add NYI for pointer/VLA arguments to recipes (#156465)
As mentioned in a previous review, we aren't properly generating
init/destroy/copy (combiner will need to be done correctly too!) regions
for recipe generation. In the case where these have 'bounds', we can do
a much better job of figuring out the type and how much needs to be
done, but that is going to be its own engineering effort.
For now, add an NYI as a note to come back to this.
Commit: f99b0f3de4f627dac0092a9bea4faa8d3cf0b2e1
https://github.com/llvm/llvm-project/commit/f99b0f3de4f627dac0092a9bea4faa8d3cf0b2e1
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td
M llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td
M llvm/test/TableGen/RuntimeLibcallEmitter.td
M llvm/unittests/IR/RuntimeLibcallsTest.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
Log Message:
-----------
[NFC] RuntimeLibcalls: Prefix the impls with 'Impl_' (#153850)
As noted in #153256, TableGen is generating reserved names for
RuntimeLibcalls, which resulted in a build failure for Arm64EC since
`vcruntime.h` defines `__security_check_cookie` as a macro.
To avoid using reserved names, all impl names will now be prefixed with
`Impl_`.
`NumLibcallImpls` was lifted out as a `constexpr size_t` instead of
being an enum field.
While I was churning the dependent code, I also removed the TODO to move
the impl enum into its own namespace and use an `enum class`: I
experimented with using an `enum class` and adding a namespace, but we
decided it was too verbose so it was dropped.
Commit: f0c819868dddc844f7539c532acfc4b7ab956bbe
https://github.com/llvm/llvm-project/commit/f0c819868dddc844f7539c532acfc4b7ab956bbe
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/source/Host/windows/Host.cpp
Log Message:
-----------
[lldb][windows] use OutputDebugStringA instead of c to log events (#156474)
In https://github.com/llvm/llvm-project/pull/150213 we made use of the
Event Viewer on Windows (equivalent of system logging on Darwin) rather
than piping to the standard output. This turned out to be too verbose in
practice, as the Event Viewer is developer oriented and not user
oriented.
This patch swaps the use of `ReportEventW` for `OutputDebugStringA`,
allowing to use tools such as `DebugView` to record logs when we are
interested in receiving them, rather than continuously writing to the
buffer. Please see an example below:
<img width="1253" height="215" alt="Screenshot 2025-09-02 at 16 07 03"
src="https://github.com/user-attachments/assets/4a326e46-d8a4-4c99-8c96-1bee62da8d55"
/>
Commit: 772cb84b9f03e1f630d237183acf37ba4c7a3bcf
https://github.com/llvm/llvm-project/commit/772cb84b9f03e1f630d237183acf37ba4c7a3bcf
Author: lntue <lntue at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/cmake/modules/LLVMLibCLibraryRules.cmake
M libc/cmake/modules/LLVMLibCObjectRules.cmake
Log Message:
-----------
[libc][NFC] Remove unused add_redirector_object and add_redirector_library in cmake. (#156485)
Commit: abb62b6ede461ac384d169fa9d9122328dc11809
https://github.com/llvm/llvm-project/commit/abb62b6ede461ac384d169fa9d9122328dc11809
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
A clang/test/CodeGenHLSL/resources/res-array-global-subarray-many.hlsl
A clang/test/CodeGenHLSL/resources/res-array-global-subarray-one.hlsl
Log Message:
-----------
[HLSL] Codegen for indexing of sub-arrays of multi-dimensional resource arrays (#154248)
Adds support for accessing sub-arrays from fixed-size multi-dimensional global resource arrays.
Enables indexing into globally scoped, fixed-size resource arrays that have multiple dimensions when the result is a smaller resource array.
For example:
```
RWBuffer<float> GlobalArray[4][2];
void main() {
RWBuffer<float> SubArray[2] = GlobalArray[3];
...
}
```
The initialization logic is handled during codegen when the ArraySubscriptExpr AST node is processed. When a global resource array is indexed and the result type is a sub-array of the larger array, a local array of the resource type is created and all elements in the array are initialized with a constructor call for the corresponding resource record type and binding.
Closes #145426
Commit: 1cc84bcc08f723a6ba9d845c3fed1777547f45f9
https://github.com/llvm/llvm-project/commit/1cc84bcc08f723a6ba9d845c3fed1777547f45f9
Author: Thurston Dang <thurston at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2_512ni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2ni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl_vnni-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl_vnni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vnni-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vnni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx_vnni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avxvnniint8-intrinsics.ll
Log Message:
-----------
[msan] Fix multiply-add-accumulate (#153927) to use ReductionFactor (#155748)
https://github.com/llvm/llvm-project/pull/153927 incorrectly cast using
a hardcoded reduction factor of two, rather than using the parameter.
This caused false negatives but not false positives. (The only incorrect
case was a reduction factor of four; if four values {A,B,C,D} are being
reduced, the result is fully zero iff {A,B} and {C,D} are both zero
after pairwise reduction. If only one of those reduced pairs is zero,
then the quadwise reduction is non-zero.)
Commit: d6a72cb300f1d4131eee4fdb101741fb2be1f780
https://github.com/llvm/llvm-project/commit/d6a72cb300f1d4131eee4fdb101741fb2be1f780
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
Log Message:
-----------
AMDGPU: Fix fixme for out of bounds indexing in usesConstantBus check (#155603)
This loop over all the operands in the MachineInstr will eventually
go past the end of the MCInstrDesc's explicit operands. We don't
need the instr desc to compute the constant bus usage, just the
register and whether it's implicit or not. The check here is slightly
conservative. e.g. a random vcc implicit use appended to an instruction
will falsely report a constant bus use.
Commit: 9b2c6052a8668711fb18844f557e229adb0306a1
https://github.com/llvm/llvm-project/commit/9b2c6052a8668711fb18844f557e229adb0306a1
Author: Yatao Wang <ningxinr at live.cn>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
Reland "[AArch64] AArch64TargetLowering::computeKnownBitsForTargetNode - add support for AArch64ISD::MOV/MVN constants" (#155696)
Reland #154039
Per suggestion by @davemgreen, add mask on the shift amount to prevent
shifting more than the bitwidth. This change is confirmed to fix the
tests failures on x86 sanitizer bots and aarch64 sanitizer bots
failures.
Fixes: https://github.com/llvm/llvm-project/issues/153159
Commit: 3ed91d880996976303e31b1900fb1fba9cd3ab44
https://github.com/llvm/llvm-project/commit/3ed91d880996976303e31b1900fb1fba9cd3ab44
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
Log Message:
-----------
[CIR][NFC] Fix build issue after AST modification (#156493)
Fix the build issue after AST modification
Commit: 4d2e1e1c74c1e437b23fccd4ea545d2f7d43d1d2
https://github.com/llvm/llvm-project/commit/4d2e1e1c74c1e437b23fccd4ea545d2f7d43d1d2
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/access-non-generic.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/alias.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/applypriority.ll
M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
M llvm/test/CodeGen/NVPTX/arithmetic-int.ll
M llvm/test/CodeGen/NVPTX/async-copy.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm60.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
M llvm/test/CodeGen/NVPTX/b52037.ll
M llvm/test/CodeGen/NVPTX/barrier.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bmsk.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/byval-arg-vectorize.ll
M llvm/test/CodeGen/NVPTX/byval-const-global.ll
M llvm/test/CodeGen/NVPTX/calling-conv.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-mad.ll
M llvm/test/CodeGen/NVPTX/combine-min-max.ll
M llvm/test/CodeGen/NVPTX/common-linkage.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/convert-call-to-indirect.ll
M llvm/test/CodeGen/NVPTX/convert-fp.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm89.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
M llvm/test/CodeGen/NVPTX/discard.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16-ex2.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fence-cluster.ll
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
M llvm/test/CodeGen/NVPTX/fence-proxy-tensormap.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-disable.ll
M llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
M llvm/test/CodeGen/NVPTX/fns.ll
M llvm/test/CodeGen/NVPTX/fold-movs.ll
M llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
M llvm/test/CodeGen/NVPTX/global-addrspace.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/griddepcontrol.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/idioms.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/intrinsic-old.ll
M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/kernel-param-align.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ld-generic.ll
M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/match.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm53-ptx42.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/mbarrier.ll
M llvm/test/CodeGen/NVPTX/nanosleep.ll
M llvm/test/CodeGen/NVPTX/nofunc.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
M llvm/test/CodeGen/NVPTX/packed-aggr.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll
M llvm/test/CodeGen/NVPTX/prefetch-inferas-test.ll
M llvm/test/CodeGen/NVPTX/prefetch.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/redux-sync.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg-sm100a.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/simple-call.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/NVPTX/st-generic.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/st_bulk.ll
M llvm/test/CodeGen/NVPTX/stacksaverestore.ll
M llvm/test/CodeGen/NVPTX/surf-tex.py
M llvm/test/CodeGen/NVPTX/symbol-naming.ll
M llvm/test/CodeGen/NVPTX/szext.ll
M llvm/test/CodeGen/NVPTX/tanhf.ll
M llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
M llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
M llvm/test/CodeGen/NVPTX/tcgen05-fence.ll
M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
M llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
M llvm/test/CodeGen/NVPTX/trunc-setcc.ll
M llvm/test/CodeGen/NVPTX/trunc-tofp.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/NVPTX/vaargs.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vector-compare.ll
M llvm/test/CodeGen/NVPTX/vector-select.ll
M llvm/test/CodeGen/NVPTX/vote.ll
M llvm/test/CodeGen/NVPTX/weak-global.ll
M llvm/test/CodeGen/NVPTX/wgmma-sm90a-fence.ll
M llvm/test/CodeGen/NVPTX/wmma-ptx60-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx61-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm72.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx64-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx65-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx71-sm80.py
M llvm/test/CodeGen/NVPTX/wmma-ptx78-sm90.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm100a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm101a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm120a.py
M llvm/test/DebugInfo/NVPTX/dbg-value-const-byref.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
M llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
M llvm/test/lit.cfg.py
Log Message:
-----------
Reland "[lit] Refactor available `ptxas` features" (#155923)
Reland #154439. Reverted with #155914.
Account for:
- Windows `ptxas` outputting error messages to `stdout` instead of
`stderr`
- Tests in `llvm/test/DebugInfo/NVPTX`
Commit: 2e96cd6562f64e11b4b3359f867bab8d45a79672
https://github.com/llvm/llvm-project/commit/2e96cd6562f64e11b4b3359f867bab8d45a79672
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp
A clang/test/Analysis/model-file-missing.cpp
Log Message:
-----------
[clang][analyzer] Delay checking the model-path (#150133)
This PR is part of an effort to remove file system usage from the
command line parsing code. The reason for that is that it's impossible
to do file system access correctly without a configured VFS, and the VFS
can only be configured after the command line is parsed. I don't want to
intertwine command line parsing and VFS configuration, so I decided to
perform the file system access after the command line is parsed and the
VFS is configured - ideally right before the file system entity is used
for the first time.
This patch delays checking that `model-path` is an existing directory.
Commit: 3ab1e0f888d46708c0c2308b072d84d8ceb43f93
https://github.com/llvm/llvm-project/commit/3ab1e0f888d46708c0c2308b072d84d8ceb43f93
Author: Sirraide <aeternalmail at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
R clang/test/AST/ast-dump-labeled-break-continue-json.c
Log Message:
-----------
[Clang] Remove broken AST dump test for now (#156498)
The name mangling on Mac OS is causing one of the AST dump tests added
by #152870 to fail, and it seems that there are some other issues with it; remove
it entirely so it stops breaking CI; I’ll add it back in a separate pr after I’ve managed
to fix it.
Commit: 2364736d6b55a4c92a53e33ee2be2679d36d26b5
https://github.com/llvm/llvm-project/commit/2364736d6b55a4c92a53e33ee2be2679d36d26b5
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang/lib/Semantics/check-call.cpp
M flang/test/Semantics/reduce01.f90
Log Message:
-----------
[flang] Fixed a crash in CheckReduce() (#156382)
Added extra checks to fix the crash.
Fixes #156167
Commit: 08001cf340185877665ee381513bf22a0fca3533
https://github.com/llvm/llvm-project/commit/08001cf340185877665ee381513bf22a0fca3533
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
Log Message:
-----------
[LAA,Loads] Use loop guards and max BTC if needed when checking deref. (#155672)
Remove the fall-back to constant max BTC if the backedge-taken-count
cannot be computed.
The constant max backedge-taken count is computed considering loop
guards, so to avoid regressions we need to apply loop guards as needed.
Also remove the special handling for Mul in willNotOverflow, as this
should not longer be needed after 914374624f
(https://github.com/llvm/llvm-project/pull/155300).
PR: https://github.com/llvm/llvm-project/pull/155672
Commit: 95d3ecee828528d4b019aae71c4f5581224ddbe2
https://github.com/llvm/llvm-project/commit/95d3ecee828528d4b019aae71c4f5581224ddbe2
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGen/volatile.cpp
Log Message:
-----------
[CIR] Add handling for volatile loads and stores (#156124)
This fills in the missing pieces to handle volatile loads and stores in
CIR.
This addresses https://github.com/llvm/llvm-project/issues/153280
Commit: 1fc090f7f1dba97bf0c53d3b158ef4934804d3d9
https://github.com/llvm/llvm-project/commit/1fc090f7f1dba97bf0c53d3b158ef4934804d3d9
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[clang][analyzer] Delay checking the ctu-dir (#150139)
This PR is part of an effort to remove file system usage from the
command line parsing code. The reason for that is that it's impossible
to do file system access correctly without a configured VFS, and the VFS
can only be configured after the command line is parsed. I don't want to
intertwine command line parsing and VFS configuration, so I decided to
perform the file system access after the command line is parsed and the
VFS is configured - ideally right before the file system entity is used
for the first time.
This patch delays checking that `ctu-dir` is an existing directory.
Commit: 7e1e13398f6907bf66fcf26dbf1f4ab67ece0182
https://github.com/llvm/llvm-project/commit/7e1e13398f6907bf66fcf26dbf1f4ab67ece0182
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang/test/Driver/atomic-control-options.f90
Log Message:
-----------
Exclude some run options on AIX. (#156376)
Those excluded run options failed on AIX.
Commit: ef72c2325ba995da84f9de62606e9a607f0d3c9a
https://github.com/llvm/llvm-project/commit/ef72c2325ba995da84f9de62606e9a607f0d3c9a
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Log Message:
-----------
[PowerPC] Implement vector unpack instructions (#151004)
Implement the set of vector uncompress instructions:
* vupkhsntob
* vupklsntob
* vupkint4tobf16
* vupkint8tobf16
* vupkint4tofp32
* vupkint8tofp32
Commit: 0c0c55a6e794779917132e48322a7222c76d11b6
https://github.com/llvm/llvm-project/commit/0c0c55a6e794779917132e48322a7222c76d11b6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
A bolt/test/runtime/copy_file.py
M bolt/test/runtime/instrumentation-indirect-2.c
Log Message:
-----------
[BOLT] Port additional test to internal shell (#156487)
This test was broken by #156083 because it was never ported to the
internal shell. It requires fuser which is not installed by default on
premerge and none of the BOLT buildbots have been online in a while.
This was actually causing a timeout because of #156484, worked around
using a manual bash invocation with a wait call to ensure all of the
subprocesses have exited.
Commit: cf3a8876f4129f76884a67f6db9214adb7adedc6
https://github.com/llvm/llvm-project/commit/cf3a8876f4129f76884a67f6db9214adb7adedc6
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
A mlir/lib/Dialect/SPIRV/IR/ArmGraphOps.cpp
M mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.cpp
M mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/test/Dialect/SPIRV/IR/availability.mlir
A mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
Log Message:
-----------
[mlir][spirv] Add support for SPV_ARM_graph extension - part 1 (#151934)
This is the first patch to add support for the SPV_ARM_graph SPIR-V
extension to MLIR’s SPIR-V dialect. The extension introduces a new Graph
abstraction for expressing dataflow computations over full resources.
The part 1 implementation includes:
- A new `GraphType`, modeled similarly to `FunctionType`, for typed
graph signatures.
- New operations in the `spirv.arm` namespace:
- `spirv.arm.Graph`
- `spirv.arm.GraphEntryPoint`
- `spirv.arm.GraphConstant`
- `spirv.arm.GraphOutput`
- Verifier and VCE updates to properly gate usage under SPV_ARM_graph.
- Tests covering parsing and verification.
Graphs currently support only SPV_ARM_tensors, but are designed to
generalize to other resource types, such as images.
Spec: KhronosGroup/SPIRV-Registry#346
RFC:
https://discourse.llvm.org/t/rfc-add-support-for-spv-arm-graph-extension-in-mlir-spir-v-dialect/86947
---------
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: c62284c43d519317979e3028f7c37f42eed6ac8e
https://github.com/llvm/llvm-project/commit/c62284c43d519317979e3028f7c37f42eed6ac8e
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
Log Message:
-----------
[clang] Followup for constexpr-unknown potential constant expressions. (#151053)
6a60f18997d62b0e2842a921fcb6beb3e52ed823 fixed the primary issue of
dereferences, but there are some expressions that depend on the identity
of the pointed-to object without actually accessing it. Handle those
cases.
Also, while I'm here, fix a crash in interpreter mode comparing typeid
to nullptr.
Commit: e2a8b9862c09acb5ae065718bbd73485da21172b
https://github.com/llvm/llvm-project/commit/e2a8b9862c09acb5ae065718bbd73485da21172b
Author: Thurston Dang <thurston at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M compiler-rt/test/asan/TestCases/zero_alloc.cpp
Log Message:
-----------
[asan] Change zero_alloc.cpp testcase to use stdlib.h, re-enable on Mac (#156490)
Avoid build breakage on Mac (reported at
https://github.com/llvm/llvm-project/pull/155943#issuecomment-3244593484)
Commit: 51163c5dbdea72139ee4b93f5de7e652d30dea9f
https://github.com/llvm/llvm-project/commit/51163c5dbdea72139ee4b93f5de7e652d30dea9f
Author: Thurston Dang <thurston at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M compiler-rt/test/msan/zero_alloc.cpp
Log Message:
-----------
[msan] Change zero_alloc.cpp testcase to use stdlib.h (#156491)
Avoid build breakage on Mac
Commit: c1d1e0e32fcd8f457a1644a5859d23155ca666ac
https://github.com/llvm/llvm-project/commit/c1d1e0e32fcd8f457a1644a5859d23155ca666ac
Author: Mohamed Emad <hulxxv at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/math/index.rst
M libc/include/math.yaml
M libc/src/math/CMakeLists.txt
A libc/src/math/atanpif16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/atanpif16.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/atanpif16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/atanpif16_test.cpp
M libc/utils/MPFRWrapper/MPCommon.cpp
M libc/utils/MPFRWrapper/MPCommon.h
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
Log Message:
-----------
[libc][math][c23] Implement C23 math function atanpif16 (#150400)
This PR implements `atanpif16(x)` which computes
$\frac{\arctan(x)}{\pi}$ for half-precision floating-point numbers using
polynomial approximation with domain reduction.
## Mathematical Implementation
The implementation uses a 15th-degree Taylor polynomial expansion of
$\frac{\arctan(x)}{\pi}$ that's computed using
[`python-sympy`](https://www.sympy.org/en/index.html) and it's accurate
in $|x| \in [0, 0.5)$:
$$
g(x) = \frac{\arctan(x)}{\pi} \approx
\begin{aligned}[t]
& 0.318309886183791x \\
& - 0.106103295394597x^3 \\
& + 0.0636619772367581x^5 \\
& - 0.0454728408833987x^7 \\
& + 0.0353677651315323x^9 \\
& - 0.0289372623803446x^{11} \\
& + 0.0244853758602916x^{13} \\
& - 0.0212206590789194x^{15} + O(x^{17})
\end{aligned}
$$
---
To ensure accuracy across all real inputs, the domain is divided into
three cases with appropriate transformations:
**Case 1: $|x| \leq 0.5$**
Direct polynomial evaluation:
$$\text{atanpi}(x) = \text{sign}(x) \cdot g(|x|)$$
**Case 2: $0.5 < |x| \leq 1$**
Double-angle reduction using:
$$\arctan(x) = 2\arctan\left(\frac{x}{1 + \sqrt{1 + x^2}}\right)$$
$$\text{atanpi}(x) = \text{sign}(x) \cdot 2g\left(\frac{|x|}{1 + \sqrt{1
+ x^2}}\right)$$
**Case 3: $|x| > 1$**
Reciprocal transformation using
$$\arctan(x) = \frac{\pi}{2} - \arctan\left(\frac{1}{x}\right) \
\text{for} \ x \gt 0$$
$$\text{atanpi}(x) = \text{sign}(x) \cdot \left(\frac{1}{2} -
g\left(\frac{1}{|x|}\right)\right)$$
Closes #132212
Commit: 1a4d0c6dfe9d717215890650a42a53d4ec9bfd8f
https://github.com/llvm/llvm-project/commit/1a4d0c6dfe9d717215890650a42a53d4ec9bfd8f
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/MC/AMDGPU/vop3-literal.s
Log Message:
-----------
[AMDGPU] Add VOP3 literal testing for GFX1250. NFC. (#156496)
Tweak some tests to avoid uninteresting errors about VGPR alignment and
some unsupported instructions.
Commit: a24e11fd951d3396ccbb469b2c5dc707dc4196a6
https://github.com/llvm/llvm-project/commit/a24e11fd951d3396ccbb469b2c5dc707dc4196a6
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[clang] Delay checking of `-fopenmp-host-ir-file-path` (#150124)
This PR is part of an effort to remove file system usage from the
command line parsing code. The reason for that is that it's impossible
to do file system access correctly without a configured VFS, and the VFS
can only be configured after the command line is parsed. I don't want to
intertwine command line parsing and VFS configuration, so I decided to
perform the file system access after the command line is parsed and the
VFS is configured - ideally right before the file system entity is used
for the first time.
This patch delays opening the OpenMP host IR file until codegen.
Commit: cea2c8625e801bdabca5e73d050300dc4060df00
https://github.com/llvm/llvm-project/commit/cea2c8625e801bdabca5e73d050300dc4060df00
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder][Debug] Remove unnecessary code. (#156468)
In the code that fix ups the debug information, we handles both the
debug intrinsics and debug records. The debug intrinsics are being
phased out and I recently changed mlir translation to not generate them.
This means that we should not get debug intrinsics anymore and code can
be simplified by removing their handling.
Commit: 005f0fa40ed3fe4657322f95916577c2f855719b
https://github.com/llvm/llvm-project/commit/005f0fa40ed3fe4657322f95916577c2f855719b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/AArch64/many-uses-fma-candidate.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
[SLP]Improved/fixed FMAD support in reductions
In the initial patch for FMAD, potential FMAD nodes were completely
excluded from the reduction analysis for the smaller patch. But it may
cause regressions.
This patch adds better detection of scalar FMAD reduction operations and
tries to correctly calculate the costs of the FMAD reduction operations
(also, excluding the costs of the scalar fmuls) and split reduction
operations, combined with regular FMADs.
Fixed the handling for reduced values with many uses.
Reviewers: RKSimon, gregbedwell, hiraditya
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/152787
Commit: 70a291f3225628d3479452829dc8b72d5d04e034
https://github.com/llvm/llvm-project/commit/70a291f3225628d3479452829dc8b72d5d04e034
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/include/mlir-c/IR.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/test/python/ir/operation.py
Log Message:
-----------
[MLIR][Python] fix operation hashing (#156514)
https://github.com/llvm/llvm-project/pull/155114 broke op hashing
(because the python objects ceased to be reference equivalent). This PR
fixes by binding `OperationEquivalence::computeHash`.
Commit: 4efde3c8fddc30b853430fc154cac85cfecc5224
https://github.com/llvm/llvm-project/commit/4efde3c8fddc30b853430fc154cac85cfecc5224
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Analysis/Loads.cpp
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size-needs-loop-guards.ll
Log Message:
-----------
[Loads] Apply loop guards to IRArgValue from assumption.
Applying loop guards to IRArgValue can improve results in some cases.
Commit: b0f85beeefbfdf3eb3f66fed6c5aed13ac423bb4
https://github.com/llvm/llvm-project/commit/b0f85beeefbfdf3eb3f66fed6c5aed13ac423bb4
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang/lib/Frontend/CompilerInvocation.cpp
Log Message:
-----------
[flang] Fix build after #150124
Commit: 9f8988aaf4cc28ff534edd8c6bd7ec0300afd328
https://github.com/llvm/llvm-project/commit/9f8988aaf4cc28ff534edd8c6bd7ec0300afd328
Author: Sebastian Pop <spop at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DependenceAnalysis] Improve debug messages (#156367)
This patch prints the reason why delinearization of array subscripts failed in dependence analysis.
Commit: 2429a8f71ff2080116b8a0e46541d1fb80351219
https://github.com/llvm/llvm-project/commit/2429a8f71ff2080116b8a0e46541d1fb80351219
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/include/math.yaml
Log Message:
-----------
[libc] Add missing and correct some existing C23 functions to math.h (#156512)
This change fixes and closes some gaps in the YAML template for
producing the math.h header.
It adds some missing declarations (dadd/dsub function variants), correct
arguments and/or return type for other functions from this family (dsqrt
and ddiv), and add a missing fminimum_numl variant.
Commit: f0df1e3dd4ec064821f673ced7d83e5a2cf6afa1
https://github.com/llvm/llvm-project/commit/f0df1e3dd4ec064821f673ced7d83e5a2cf6afa1
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
Log Message:
-----------
Revert "[LAA,Loads] Use loop guards and max BTC if needed when checking deref. (#155672)"
This reverts commit 08001cf340185877665ee381513bf22a0fca3533.
This triggers an assertion in some build configs, e.g.
https://lab.llvm.org/buildbot/#/builders/24/builds/12211
Commit: 3c7bf3b3c3a4871d13f7b7d5d60bbf190eaf8f3a
https://github.com/llvm/llvm-project/commit/3c7bf3b3c3a4871d13f7b7d5d60bbf190eaf8f3a
Author: nerix <nerixdev at outlook.de>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
M lldb/test/Shell/SymbolFile/NativePDB/Inputs/incomplete-tag-type.cpp
R lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.cpp
A lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.test
Log Message:
-----------
[LLDB][NativePDB] Complete array member types in AST builder (#156370)
Commit: 665e875f1a86be650e044bb20744bb272d03e11d
https://github.com/llvm/llvm-project/commit/665e875f1a86be650e044bb20744bb272d03e11d
Author: David Blaikie <dblaikie at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCall.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/test/DebugInfo/CXX/structured-binding.cpp
Log Message:
-----------
[DebugInfo] When referencing structured bindings use the reference's location, not the binding's declaration's location (#153637)
For structured bindings that use custom `get` specializations, the
resulting LLVM IR ascribes the load of the result of `get` to the
binding's declaration, rather than the place where the binding is
referenced - this caused awkward sequencing in the debug info where,
when stepping through the code you'd step back to the binding
declaration every time there was a reference to the binding.
To fix that - when we cross into IRGening a binding - suppress the debug
info location of that subexpression.
I don't represent this as a great bit of API design - certainly open to
ideas, but putting it out here as a place to start.
It's /possible/ this is an incomplete fix, even - if the binding decl
had other subexpressions, those would still get their location applied &
it'd likely be wrong.
So maybe that's a direction to go with to productionize this - add a new
location scoped device that suppresses any overriding - this might be
more robust. How do people feel about that?
Commit: 3e0b91b77c0e4a056b4d8be61a8b82a077d36644
https://github.com/llvm/llvm-project/commit/3e0b91b77c0e4a056b4d8be61a8b82a077d36644
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/error_message.cpp
Log Message:
-----------
[OpenMP][clang] Fix CaptureRegion for message clause (#156525)
Fixes https://github.com/llvm/llvm-project/issues/156232
Commit: fbb0f2dba040bbdd5de5e59201c1a6fb9be3e06d
https://github.com/llvm/llvm-project/commit/fbb0f2dba040bbdd5de5e59201c1a6fb9be3e06d
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Log Message:
-----------
[PowerPC] Implement vector uncompress instructions (#150702)
Implement the set of vector uncompress instructions:
* vucmprhh
* vucmprlh
* vucmprhn
* vucmprln
* vucmprhb
* vucmprlb
Commit: 3ce0ea38c2328c373227f5f1237b8ed88f7ecf06
https://github.com/llvm/llvm-project/commit/3ce0ea38c2328c373227f5f1237b8ed88f7ecf06
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
Log Message:
-----------
[AMDGPU] Definitions of new gfx1250 HW_REG_MODE fields. NFC. (#156527)
Commit: 49fcfaa15aeeed147280e6e39d802ac712ed3d74
https://github.com/llvm/llvm-project/commit/49fcfaa15aeeed147280e6e39d802ac712ed3d74
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
A llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
Log Message:
-----------
[GVN] Turn off ScalarPRE for TokenLike Types (#156513)
fixes #154407
In HLSL the GVNPass was adding a phi node on
a target extention type.
https://hlsl.godbolt.org/z/sc14YenEe
This is something we cleaned up in a past PR
(https://github.com/llvm/llvm-project/pull/154620) by introducing
`isTokenLikeTy`. In the case of the GVN pass the target extention type
was still making its way through. This change makes it so if we see this
type we don't do PRE.
Commit: 81131f37455e9960ed22fa48d95e69f8a0149347
https://github.com/llvm/llvm-project/commit/81131f37455e9960ed22fa48d95e69f8a0149347
Author: Haowei <haowei at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/Debuginfod/Debuginfod.h
M llvm/include/llvm/Debuginfod/HTTPServer.h
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/Debuginfod/HTTPServer.cpp
M llvm/tools/llvm-debuginfod/llvm-debuginfod.cpp
Log Message:
-----------
Reverts recent debuginfod patches (#156532)
This patch reverts 44e791c6ff1a982de9651aad7d1c83d1ad96da8a,
3cc1031a827d319c6cb48df1c3aafc9ba7e96d72 and
adbd43250ade1d5357542d8bd7c3dfed212ddec0. Which breaks debuginfod build
and tests when httplib is used.
Commit: cc9acb9df7f7e598a6c93eaa1f2b1405a6b73bad
https://github.com/llvm/llvm-project/commit/cc9acb9df7f7e598a6c93eaa1f2b1405a6b73bad
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
Log Message:
-----------
[AMDGPU] Add s_set_vgpr_msb gfx1250 instruction (#156524)
Commit: 023a98c2ae8a260632f5fa71aaede95c4a981399
https://github.com/llvm/llvm-project/commit/023a98c2ae8a260632f5fa71aaede95c4a981399
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/bindings/interface/SBStructuredDataExtensions.i
M lldb/test/API/python_api/sbstructureddata/TestStructuredDataAPI.py
Log Message:
-----------
[lldb] Add Pythonic API to SBStructuredData extension (#155061)
* Adds `dynamic` property to automatically convert `SBStructuredData`
instances to the associated Python type (`str`, `int`, `float`, `bool`,
`NoneType`, etc)
* Implements `__getitem__` for Pythonic array and dictionary
subscripting
* Subscripting return the result of the `dynamic` property
* Updates `__iter__` to support dictionary instances (supporting `for`
loops)
* Adds conversion to `str`, `int`, and `float`
* Adds Pythonic `bool` conversion
With these changes, these two expressions are equal:
```py
data["name"] == data.GetValueForKey("name").GetStringValue(1024)
```
Additionally did some cleanup in TestStructuredDataAPI.py.
Commit: 2fc0e2c888521489f4a286b0902a6896506f8d8e
https://github.com/llvm/llvm-project/commit/2fc0e2c888521489f4a286b0902a6896506f8d8e
Author: Zequan Wu <zequanwu at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
Log Message:
-----------
[lldb][NativePDB] Sort function name and type basename maps deterministically. (#156530)
https://github.com/llvm/llvm-project/pull/153160 created those function
maps and uses default sort comparator which is not deterministic when
there are multiple entries with same name because llvm::sort is unstable
sort.
This fixes it by comparing the id value when tie happens and sort
`m_type_base_names` deterministically as well.
Commit: 5b4819e337c662fad7176a1d8e7b95a94f199290
https://github.com/llvm/llvm-project/commit/5b4819e337c662fad7176a1d8e7b95a94f199290
Author: David Blaikie <dblaikie at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/test/DebugInfo/CXX/structured-binding.cpp
Log Message:
-----------
Generalize test over 32 and 64bit targets
Commit: 2bc019d8d02afee096f1c0c19cb2828b526aef94
https://github.com/llvm/llvm-project/commit/2bc019d8d02afee096f1c0c19cb2828b526aef94
Author: Philip Reames <preames at rivosinc.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Log Message:
-----------
[RISCV] Simplify interface of RISCVAsmPrinter::lowerToMCInst [nfc] (#156482)
The only case which returns true is just pypassing this routine for
custom logic. Given the caller *already* has to special case this to
even fall into this routine, let's just put the logic in one place.
Note that the code had a guard for a malformed attribute which is
unreachable, and was converted into an assert. The verifier enforces
that the function attribute is well formed if present.
Commit: e57cb26d171bebe78df0a3d008e7f4c14b319067
https://github.com/llvm/llvm-project/commit/e57cb26d171bebe78df0a3d008e7f4c14b319067
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M flang-rt/lib/runtime/CMakeLists.txt
Log Message:
-----------
[flang][rt] Remove findloc.cpp from supported_sources fro CUDA build (#156542)
findloc.cpp is causing memory exhaustion with higher compute
capabilities. Also it is a very expensive file to build. Remove it from
the supported_sources for CUDA build until we can lower its memory
footprint.
Commit: 7fa3e6d17941cfdd982f5e159a52dde671e24685
https://github.com/llvm/llvm-project/commit/7fa3e6d17941cfdd982f5e159a52dde671e24685
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M lldb/source/Commands/Options.td
Log Message:
-----------
[lldb] Format source/Commands/Options.td (#156517)
Format the command options tablegen file, which was created before
clang-format added support for tablegen. Small changes lead to lots of
reformatting changes which makes the diffs hard to review.
Commit: 03f836eff85e115c4dc57b64eeb3d8643f9f53a3
https://github.com/llvm/llvm-project/commit/03f836eff85e115c4dc57b64eeb3d8643f9f53a3
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
Log Message:
-----------
[NVPTX] Fix `fence-nocluster.ll` `ptxas` invocation (NFC) (#156531)
Commit: 7a0dfb1fec20bcb8565b39507e282b12e436ba1f
https://github.com/llvm/llvm-project/commit/7a0dfb1fec20bcb8565b39507e282b12e436ba1f
Author: erichkeane <ekeane at nvidia.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/test/SemaOpenACC/combined-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/compute-construct-reduction-clause.c
M clang/test/SemaOpenACC/compute-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
Log Message:
-----------
[OpenACC] Make 'reduction' on a complex ill-formed
The standard provides for scalar variables, though is silent as to
whether complex is a scalar variable. However, during review, we found
that it is completely nonsensical to do any of the reduction operations on
complex (or to initialize some), so this patch makes it ill-formed.
Commit: 22ba2ac3ea4e57d9e501c6c82e6f2f9e2a71f970
https://github.com/llvm/llvm-project/commit/22ba2ac3ea4e57d9e501c6c82e6f2f9e2a71f970
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for modernize-use-emplace in TosaReduceTransposes.cpp (NFC)
Commit: 2b70ad24e8c4db8fa681ea8a1086cda81e89fde2
https://github.com/llvm/llvm-project/commit/2b70ad24e8c4db8fa681ea8a1086cda81e89fde2
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in ReshapeOpsUtils.cpp (NFC)
Commit: e2901f161087840c36890e61055aded5df90399b
https://github.com/llvm/llvm-project/commit/e2901f161087840c36890e61055aded5df90399b
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
Log Message:
-----------
[AMDGPU] Adjust VGPR allocation encoding on gfx1250 (#156546)
Commit: 1cee0e7b6281e5f82154a101eed09a7197a295a6
https://github.com/llvm/llvm-project/commit/1cee0e7b6281e5f82154a101eed09a7197a295a6
Author: Charles Zablit <c_zablit at apple.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/include/lldb/Host/File.h
M lldb/source/Host/common/File.cpp
Log Message:
-----------
[lldb][windows] use Windows APIs to print to the console (#156469)
This is a relanding of https://github.com/llvm/llvm-project/pull/149493.
The tests were failing because we were interpreting a proper file
descriptor as a console file descriptor.
This patch uses the Windows APIs to print to the Windows Console,
through `llvm::raw_fd_ostream`.
This fixes a rendering issue where the characters defined in
`DiagnosticsRendering.cpp` ("╰" for instance) are not rendered properly
on Windows out of the box, because the default codepage is not `utf-8`.
This solution is based on [this patch
downstream](https://github.com/swiftlang/swift/pull/40632/files#diff-e948e4bd7a601e3ca82d596058ccb39326459a4751470eec4d393adeaf516977R37-R38).
rdar://156064500
Commit: a3c41ddcafb93dcb226bdef12b91a192b647e8c4
https://github.com/llvm/llvm-project/commit/a3c41ddcafb93dcb226bdef12b91a192b647e8c4
Author: Derek Schuff <dschuff at chromium.org>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/test/CodeGen/WebAssembly/global-set.ll
Log Message:
-----------
[WebAssembly] Guard use of getSymbolName with isSymbol (#156105)
WebAssemblyRegStackfy checks for writes to the stack pointer to avoid
stackifying across them, but it wasn't prepared for other global_set
instructions (such as writes in addrspace 1).
Fixes #156055
Thanks to @QuantumSegfault for reporting and identifying the offending
code.
Commit: e95355c3f7e18829b587bc2d589b24a65f596543
https://github.com/llvm/llvm-project/commit/e95355c3f7e18829b587bc2d589b24a65f596543
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
Log Message:
-----------
[libc] Add CMake Target for Dl_info.h Header (#156195)
Otherwise when installing the dlfcn.h header, there is a missing
reference to Dl_info.h, which causes compilation failures in some cases,
notably libunwind.
Commit: 0dc1b168a660969f6f99f3238b908c1e3be5ed2d
https://github.com/llvm/llvm-project/commit/0dc1b168a660969f6f99f3238b908c1e3be5ed2d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/dl_info.h
M libc/src/dlfcn/CMakeLists.txt
M libc/src/dlfcn/dladdr.cpp
M libc/src/dlfcn/dladdr.h
Log Message:
-----------
[libc] Install dladdr on X86 (#156500)
This patch adds dladdr to the X86 entrypoints and also does the
necessary plumbing so that dladdr.cpp will actually compile.
This depends on #156195.
Commit: d3d1d8ff213868262194676dfd90172ddc447907
https://github.com/llvm/llvm-project/commit/d3d1d8ff213868262194676dfd90172ddc447907
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-cluster-load.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
Log Message:
-----------
[AMDGPU] Support cluster load instructions for gfx1250 (#156548)
Commit: c7b26bdf0b495fb1e835f7fe4136d3583628dd60
https://github.com/llvm/llvm-project/commit/c7b26bdf0b495fb1e835f7fe4136d3583628dd60
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
Log Message:
-----------
[AMDGPU] Update builtins-amdgcn-error-gfx1250-param.cl (#156551)
Should check both load_async_to_lds and store_async_from_lds instead
just check store_async_from_lds twice.
Commit: 442b14d1720824064ac2d194d151c6421f6d4570
https://github.com/llvm/llvm-project/commit/442b14d1720824064ac2d194d151c6421f6d4570
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Fix adding m0 uses to gfx94/gfx12 ds atomics (#156402)
This was using the legacy multiclass which assumes the base form
has an m0 use. Use the versions which assume no m0 as the base name.
Most of the diff is shuffling around the pattern classes to avoid trying
to match the nonexistent m0-having form.
Commit: 1e786fbe5bbec669c745ea1bb67c1e15092a0073
https://github.com/llvm/llvm-project/commit/1e786fbe5bbec669c745ea1bb67c1e15092a0073
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Reorder arguments of DS_Real_gfx12 (NFC) (#156405)
This helps shrink the diff in a future change.
Commit: 3a7d14accef790e38fa38bdc2ef7fec4cfb90c2d
https://github.com/llvm/llvm-project/commit/3a7d14accef790e38fa38bdc2ef7fec4cfb90c2d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
Log Message:
-----------
AMDGPU: Avoid using exact class check in reg_sequence AGPR fold (#156135)
This does better in cases which mix align2 and non-align2 classes.
Commit: d7484684e5c81e567e6d31942b7047ba579daae1
https://github.com/llvm/llvm-project/commit/d7484684e5c81e567e6d31942b7047ba579daae1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
AMDGPU: Refactor isImmOperandLegal (#155607)
The goal is to expose more variants that can operate without
preconstructed MachineInstrs or MachineOperands.
Commit: d50f2ef437aeb1784f7556fd63639487f245ffaa
https://github.com/llvm/llvm-project/commit/d50f2ef437aeb1784f7556fd63639487f245ffaa
Author: Wenju He <wenju.he at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libclc/clc/include/clc/clc_convert.h
R libclc/clc/include/clc/clcmacro.h
M libclc/clc/lib/amdgcn/math/clc_ldexp_override.cl
M libclc/clc/lib/amdgpu/math/clc_native_exp2.cl
M libclc/clc/lib/amdgpu/math/clc_sqrt_fp64.cl
M libclc/clc/lib/clspv/math/clc_sw_fma.cl
M libclc/clc/lib/generic/common/clc_degrees.cl
M libclc/clc/lib/generic/common/clc_radians.cl
M libclc/clc/lib/generic/common/clc_smoothstep.cl
M libclc/clc/lib/generic/common/clc_step.cl
M libclc/clc/lib/generic/integer/clc_clz.cl
M libclc/clc/lib/generic/integer/clc_ctz.cl
M libclc/clc/lib/generic/integer/clc_mad_sat.cl
M libclc/clc/lib/generic/math/clc_cbrt.cl
M libclc/clc/lib/generic/math/clc_cos.cl
M libclc/clc/lib/generic/math/clc_exp10.cl
M libclc/clc/lib/generic/math/clc_fmod.cl
M libclc/clc/lib/generic/math/clc_fract.cl
M libclc/clc/lib/generic/math/clc_frexp.inc
M libclc/clc/lib/generic/math/clc_hypot.cl
M libclc/clc/lib/generic/math/clc_ilogb.cl
M libclc/clc/lib/generic/math/clc_ldexp.cl
M libclc/clc/lib/generic/math/clc_lgamma_r.cl
M libclc/clc/lib/generic/math/clc_log.cl
M libclc/clc/lib/generic/math/clc_log10.cl
M libclc/clc/lib/generic/math/clc_log2.cl
M libclc/clc/lib/generic/math/clc_logb.cl
M libclc/clc/lib/generic/math/clc_nextafter.cl
M libclc/clc/lib/generic/math/clc_pow.cl
M libclc/clc/lib/generic/math/clc_pown.cl
M libclc/clc/lib/generic/math/clc_powr.cl
M libclc/clc/lib/generic/math/clc_remainder.cl
M libclc/clc/lib/generic/math/clc_remquo.cl
M libclc/clc/lib/generic/math/clc_sin.cl
M libclc/clc/lib/generic/math/clc_sw_fma.cl
M libclc/clc/lib/generic/relational/clc_bitselect.cl
M libclc/clc/lib/r600/math/clc_native_rsqrt.cl
M libclc/clc/lib/r600/math/clc_rsqrt_override.cl
M libclc/clc/lib/spirv/math/clc_fmax.cl
M libclc/clc/lib/spirv/math/clc_fmin.cl
M libclc/opencl/lib/generic/common/sign.cl
M libclc/opencl/lib/generic/common/smoothstep.cl
M libclc/opencl/lib/generic/math/atan2.cl
M libclc/opencl/lib/generic/math/atan2pi.cl
M libclc/opencl/lib/generic/math/log.cl
M libclc/opencl/lib/generic/math/log10.cl
M libclc/opencl/lib/generic/math/log2.cl
M libclc/opencl/lib/generic/math/nan.cl
Log Message:
-----------
[NFC][libclc] Move _CLC_V_V_VP_VECTORIZE macro into clc_lgamma_r.cl and delete clcmacro.h (#156280)
clcmacro.h only defines _CLC_V_V_VP_VECTORIZE which is only used in
clc/lib/generic/math/clc_lgamma_r.cl.
Commit: dd5eb46690be62cc2c7b925de1b2dfde514337f0
https://github.com/llvm/llvm-project/commit/dd5eb46690be62cc2c7b925de1b2dfde514337f0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
Log Message:
-----------
AMDGPU: Fold 64-bit immediate into copy to AV class (#155615)
This is in preparation for patches which will intoduce more
copies to av registers.
Commit: b159631bc63c9a591500a9dcde759b358229f179
https://github.com/llvm/llvm-project/commit/b159631bc63c9a591500a9dcde759b358229f179
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
AMDGPU: Replace constexpr with inline
One bot doesn't like this constexpr after d7484684
Commit: 9b5502292d8e4fa00ec1ab204df3999b7424dbb8
https://github.com/llvm/llvm-project/commit/9b5502292d8e4fa00ec1ab204df3999b7424dbb8
Author: Adam Nemet <anemet at apple.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Log Message:
-----------
[CG] Add VTs for v[567]i1 and v[567]f16 (#156523)
[recommit https://github.com/llvm/llvm-project/pull/151763 after fixing
https://github.com/llvm/llvm-project/issues/152150]
We already had corresponding f32 and i32 vector types for these sizes.
Also add VTs v[567]i8 and v[567]i16: these are needed by the Hexagon
backend which for each i1 vector types want to query information about
the corresponding i8 and i16 types in
HexagonTargetLowering::getPreferredHvxVectorAction.
Commit: 681046e3a5d9892711846ff1eb01b112357fdacc
https://github.com/llvm/llvm-project/commit/681046e3a5d9892711846ff1eb01b112357fdacc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
Log Message:
-----------
AMDGPU: Fix true16 d16 entry table for DS pseudos (#156419)
This should be trying to use the _gfx9 variants of DS pseudos,
not the base form with m0 uses.
Commit: 4ec890857da327adf547d3fece986e125ff2e2cb
https://github.com/llvm/llvm-project/commit/4ec890857da327adf547d3fece986e125ff2e2cb
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
A llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
Log Message:
-----------
AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)
In future changes we will have more AV_ virtual registers, which
currently
block the formation of write2. Most of the time these registers can
simply
be constrained to VGPR, so do that.
Also relaxes the constraint in flat merging case. We already have the
necessary
code to insert copies to the original result registers, so there's no
point
in avoiding it.
Addresses the easy half of #155769
Commit: 410764cff5d657e66a64a8250958db99fb721385
https://github.com/llvm/llvm-project/commit/410764cff5d657e66a64a8250958db99fb721385
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
Log Message:
-----------
[RISCV] Commute True in foldVMergeToMask (#156499)
In order to fold a vmerge into a pseudo, the pseudo's passthru needs to
be the same as vmerge's false operand.
If they don't match we can try and commute the instruction if possible,
e.g. here we can commute v9 and v8 to fold the vmerge:
vsetvli zero, a0, e32, m1, ta, ma
vfmadd.vv v9, v10, v8
vsetvli zero, zero, e32, m1, tu, ma
vmerge.vvm v8, v8, v9, v0
vsetvli zero, a0, e32, m1, tu, mu
vfmacc.vv v8, v9, v10, v0.t
Previously this wasn't possible because we did the peephole in
SelectionDAG, but now that it's been migrated to MachineInstr in #144076
we can reuse the commuting infrastructure in TargetInstrInfo.
This fixes the extra vmv.v.v in the "mul" example here:
https://github.com/llvm/llvm-project/issues/123069#issuecomment-3137997141
It should also allow us to remove the isel patterns described in #141885
later.
Commit: c33ccfa52b2db90bae72ac11ee50639231e93310
https://github.com/llvm/llvm-project/commit/c33ccfa52b2db90bae72ac11ee50639231e93310
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
Log Message:
-----------
[VPlan] Reassociate (x & y) & z -> x & (y & z) (#155383)
This PR reassociates logical ands in order to enable more
simplifications.
The driving motivation for this is that with tail folding all blocks
inside the loop body will end up using the header mask. However this can
end up nestled deep within a chain of logical ands from other edges.
Typically the header mask will be a leaf nested in the LHS, e.g.
(headermask & y) & z. So pulling it out allows it to be simplified
further, e.g. allows it to be optimised away to VP intrinsics with EVL
tail folding.
Commit: cb89ffdd34aa6b7e6d1417ef68e1d837c8e651a1
https://github.com/llvm/llvm-project/commit/cb89ffdd34aa6b7e6d1417ef68e1d837c8e651a1
Author: Mitch <mitchbriles at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
Log Message:
-----------
[RISCV] Fix incorrect folding of select on ctlz/cttz (#155231)
This patch tries to fix
[#155014](https://github.com/llvm/llvm-project/issues/155014). The
pattern of `ctlz`/`cttz` -> `icmp` -> `select` can occur when accounting
for targets which don't support `cttz(0)` or `ctlz(0)`. We can replace
this with a mask, but **only on power-of-2 bitwidths**.
Commit: bfe150cdfc58feb0499f129b4be653340f98e1fe
https://github.com/llvm/llvm-project/commit/bfe150cdfc58feb0499f129b4be653340f98e1fe
Author: Brox Chen <guochen2 at amd.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
Log Message:
-----------
[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence (#154952)
update zext pattern with reg_sequence. This is a follow up from
https://github.com/llvm/llvm-project/pull/154211#discussion_r2288538817
Commit: c5d766236d2b550c093fe9d963f8d036b0fcfb0b
https://github.com/llvm/llvm-project/commit/c5d766236d2b550c093fe9d963f8d036b0fcfb0b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
Log Message:
-----------
AMDGPU: Add tests for ds_write2 formation with agprs (#155765)
The current handling for write2 formation is overly conservative
and cannot form write2s with AGPR inputs.
Commit: 74275a11038c0c354a31b5da4657e5ddfad58d9a
https://github.com/llvm/llvm-project/commit/74275a11038c0c354a31b5da4657e5ddfad58d9a
Author: Kito Cheng <kito.cheng at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[RISCV] Simplify code gen for riscv_vector_builtin_cg.inc [NFC] (#156397)
For each intrinsic with ManualCodegen block will generate something like
below:
```cpp
SegInstSEW = 0;
...
if (SegInstSEW == (unsigned)-1) {
auto PointeeType = E->getArg(4294967295)->getType()->getPointeeType();
SegInstSEW = llvm::Log2_64(getContext().getTypeSize(PointeeType));
}
```
But actually SegInstSEW is table-gen-time constant, so can remove that
if-check and directly use the constant.
This change reduce riscv_vector_builtin_cg.inc around 6600 lines (30913
to 24305) which is around 20% reduction, however seems this isn't impact
the build time much since the redundant dead branch is almost will
optimized away by compiler in early stage.
Commit: 4aeb2900837ce750af821e1f0dba6d53ccd4870a
https://github.com/llvm/llvm-project/commit/4aeb2900837ce750af821e1f0dba6d53ccd4870a
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M libc/src/__support/CPP/simd.h
M libc/src/string/memory_utils/generic/inline_strlen.h
Log Message:
-----------
[libc] Add more elementwise wrapper functions (#156515)
Summary:
Fills out some of the missing fundamental floating point operations.
These just wrap the elementwise builtin of the same name.
Commit: 9c3961f4f60d7d6de189addfb81d43e05300600e
https://github.com/llvm/llvm-project/commit/9c3961f4f60d7d6de189addfb81d43e05300600e
Author: Chaitanya Koparkar <ckoparkar at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Headers/fmaintrin.h
Log Message:
-----------
[X86] Clear EVEX512 feature for 128-bit and 256-bit FMA intrinsics (#156472)
This matches the corresponding features defined in avx512vlintrin.h.
Commit: ba7d4792e1edabac593b8292420d355495081e08
https://github.com/llvm/llvm-project/commit/ba7d4792e1edabac593b8292420d355495081e08
Author: Durgadoss R <durgadossr at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-cp.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-shift.mlir
Log Message:
-----------
[MLIR][NVVM] [NFC] Rename Tcgen05GroupKind to CTAGroupKind (#156448)
...as the cta_group::1/2 are used in non-tcgen05 Ops like TMA Loads
also.
Signed-off-by: Durgadoss R <durgadossr at nvidia.com>
Commit: 8f50921cef04a11b97be0fb333c1df6921df649f
https://github.com/llvm/llvm-project/commit/8f50921cef04a11b97be0fb333c1df6921df649f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
Log Message:
-----------
[RISCV] Add Zfh RUN lines to calling-conv-half.ll. NFC (#156562)
We had these RUN lines in our downstream and I couldn't tell for sure
that we had another Zfh calling convention test upstream.
Note we should fix the stack test to also exhaust the GPRs to make it
test the stack for ilp32f/lp64f. This was an existing issue in the
testing when F was enabled.
Commit: a9532191b82b02e6690e13fb72f513ab16119652
https://github.com/llvm/llvm-project/commit/a9532191b82b02e6690e13fb72f513ab16119652
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-09-02 (Tue, 02 Sep 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLRuntime.cpp
Log Message:
-----------
[HLSL][NFC] Add assert to verify implicit binding resource attribute exists (#156094)
Adds assert as requested in
https://github.com/llvm/llvm-project/pull/152454#discussion_r2304509802.
Commit: 10dbb45e5c278dbbae4c0c3744482e0ebb557a9a
https://github.com/llvm/llvm-project/commit/10dbb45e5c278dbbae4c0c3744482e0ebb557a9a
Author: Jim Lin <jim at andestech.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
Log Message:
-----------
[RISCV] Remove unused `IntrinsicTypes` from help functions in RISCV.cpp. NFC.
Commit: 085471d777a2056903dca12b10139a9036b0125b
https://github.com/llvm/llvm-project/commit/085471d777a2056903dca12b10139a9036b0125b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
Log Message:
-----------
AMDGPU: Handle rewriting VGPR MFMA fed from AGPR copy (#153022)
Previously we handled the inverse situation only.
Commit: d373ec7f16872f838ce5ea9355b76b5924628393
https://github.com/llvm/llvm-project/commit/d373ec7f16872f838ce5ea9355b76b5924628393
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
Log Message:
-----------
AMDGPU: Add baseline test for unspilling VGPRs after MFMA rewrite (#154322)
Test for #154260
Commit: fdede21ddf05d72ce752bf03920d533e0800354b
https://github.com/llvm/llvm-project/commit/fdede21ddf05d72ce752bf03920d533e0800354b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
Log Message:
-----------
AMDGPU: Add statistic for number of MFMAs moved to AGPR form (#153024)
Commit: 3294cddb9878347cf273f427184190321e062028
https://github.com/llvm/llvm-project/commit/3294cddb9878347cf273f427184190321e062028
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
Log Message:
-----------
AMDGPU: Add test for mfma rewrite pass respecting optnone (#153025)
Commit: 7624c6141974f66f24ea90a18a55a111e98baa40
https://github.com/llvm/llvm-project/commit/7624c6141974f66f24ea90a18a55a111e98baa40
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/__tree
M libcxx/include/map
M libcxx/include/set
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/set/insert_iter_iter.pass.cpp
Log Message:
-----------
[libc++] Optimize {map,set}::insert(InputIterator, InputIterator) (#154703)
```
----------------------------------------------------------------------------------------------------------------------------
Benchmark old new
----------------------------------------------------------------------------------------------------------------------------
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/0 14.2 ns 14.8 ns
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/32 519 ns 404 ns
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/1024 52460 ns 36242 ns
std::map<int, int>::ctor(iterator, iterator) (unsorted sequence)/8192 724222 ns 706496 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/0 14.2 ns 14.7 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/32 429 ns 349 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/1024 23601 ns 14734 ns
std::map<int, int>::ctor(iterator, iterator) (sorted sequence)/8192 267753 ns 112155 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/0 434 ns 448 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/32 950 ns 963 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/1024 27205 ns 25344 ns
std::map<int, int>::insert(iterator, iterator) (all new keys)/8192 294248 ns 280713 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/0 435 ns 449 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/32 771 ns 706 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/1024 30841 ns 17495 ns
std::map<int, int>::insert(iterator, iterator) (half new keys)/8192 468807 ns 285847 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/0 449 ns 453 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/32 1021 ns 932 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/1024 29796 ns 19518 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from same type)/8192 345688 ns 153966 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/0 449 ns 450 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/32 1026 ns 807 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/1024 31632 ns 15573 ns
std::map<int, int>::insert(iterator, iterator) (product_iterator from zip_view)/8192 303024 ns 128946 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/0 447 ns 452 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/32 687 ns 710 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/1024 8604 ns 8581 ns
std::map<int, int>::erase(iterator, iterator) (erase half the container)/8192 65693 ns 67406 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/0 15.0 ns 15.0 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/32 2781 ns 1845 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/1024 187999 ns 182103 ns
std::map<std::string, int>::ctor(iterator, iterator) (unsorted sequence)/8192 2937242 ns 2934912 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/0 15.0 ns 15.2 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/32 1326 ns 2462 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/1024 81778 ns 72193 ns
std::map<std::string, int>::ctor(iterator, iterator) (sorted sequence)/8192 1177292 ns 669152 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/0 439 ns 454 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/32 2483 ns 2465 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/1024 187614 ns 188072 ns
std::map<std::string, int>::insert(iterator, iterator) (all new keys)/8192 1654675 ns 1706603 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/0 437 ns 452 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/32 1836 ns 1820 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/1024 114885 ns 121865 ns
std::map<std::string, int>::insert(iterator, iterator) (half new keys)/8192 1151960 ns 1197318 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/0 438 ns 455 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/32 1599 ns 1614 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/1024 95935 ns 82159 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from same type)/8192 776480 ns 941043 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/0 435 ns 462 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/32 1723 ns 1550 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/1024 107096 ns 92850 ns
std::map<std::string, int>::insert(iterator, iterator) (product_iterator from zip_view)/8192 893976 ns 775046 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/0 436 ns 453 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/32 775 ns 824 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/1024 20241 ns 20454 ns
std::map<std::string, int>::erase(iterator, iterator) (erase half the container)/8192 139038 ns 138032 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/0 14.8 ns 14.7 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/32 468 ns 426 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/1024 54289 ns 39028 ns
std::set<int>::ctor(iterator, iterator) (unsorted sequence)/8192 738438 ns 695720 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/0 14.7 ns 14.6 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/32 478 ns 391 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/1024 24017 ns 13905 ns
std::set<int>::ctor(iterator, iterator) (sorted sequence)/8192 267862 ns 111378 ns
std::set<int>::insert(iterator, iterator) (all new keys)/0 458 ns 450 ns
std::set<int>::insert(iterator, iterator) (all new keys)/32 1066 ns 956 ns
std::set<int>::insert(iterator, iterator) (all new keys)/1024 29190 ns 25212 ns
std::set<int>::insert(iterator, iterator) (all new keys)/8192 320441 ns 279602 ns
std::set<int>::insert(iterator, iterator) (half new keys)/0 454 ns 453 ns
std::set<int>::insert(iterator, iterator) (half new keys)/32 816 ns 709 ns
std::set<int>::insert(iterator, iterator) (half new keys)/1024 32072 ns 17074 ns
std::set<int>::insert(iterator, iterator) (half new keys)/8192 403386 ns 286202 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/0 451 ns 452 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/32 710 ns 703 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/1024 8261 ns 8499 ns
std::set<int>::erase(iterator, iterator) (erase half the container)/8192 64466 ns 67343 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/0 15.2 ns 15.0 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/32 3069 ns 3005 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/1024 189552 ns 180933 ns
std::set<std::string>::ctor(iterator, iterator) (unsorted sequence)/8192 2887579 ns 2691678 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/0 15.1 ns 14.9 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/32 2611 ns 2514 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/1024 91581 ns 78727 ns
std::set<std::string>::ctor(iterator, iterator) (sorted sequence)/8192 1192640 ns 1158959 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/0 452 ns 457 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/32 2530 ns 2544 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/1024 195352 ns 179614 ns
std::set<std::string>::insert(iterator, iterator) (all new keys)/8192 1737890 ns 1749615 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/0 451 ns 454 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/32 1949 ns 1766 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/1024 128853 ns 109467 ns
std::set<std::string>::insert(iterator, iterator) (half new keys)/8192 1233077 ns 1177289 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/0 450 ns 451 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/32 809 ns 812 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/1024 21736 ns 21922 ns
std::set<std::string>::erase(iterator, iterator) (erase half the container)/8192 135884 ns 133228 ns
```
Fixes #154650
Commit: 4a2dd31f16d60b65a46696a909efad5c11b18c19
https://github.com/llvm/llvm-project/commit/4a2dd31f16d60b65a46696a909efad5c11b18c19
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__tree
M libcxx/include/map
Log Message:
-----------
[libc++] Refactor __tree::__find_equal to not have an out parameter (#147345)
Commit: a5b5248b7f2a9c0a25fc41ea87c01510558e3ecf
https://github.com/llvm/llvm-project/commit/a5b5248b7f2a9c0a25fc41ea87c01510558e3ecf
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__functional/function.h
M libcxx/include/__type_traits/invoke.h
Log Message:
-----------
[libc++] Simplify std::function implementation further (#145153)
We can use `if constexpr` and `__is_invocable_r` to simplify the
`function` implementation a bit.
Commit: 0a2eb850d0dbd9caa1b22ee94f3b2b9903f679cb
https://github.com/llvm/llvm-project/commit/0a2eb850d0dbd9caa1b22ee94f3b2b9903f679cb
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__config
M libcxx/include/mutex
A libcxx/test/extensions/clang/thread/thread.mutex/lock.verify.cpp
Log Message:
-----------
[libc++] Add thread safety annotations for std::lock (#154078)
Fixes #151733
Commit: 7ac3e52e29b17e22e973c15c2715602ffd19e8a9
https://github.com/llvm/llvm-project/commit/7ac3e52e29b17e22e973c15c2715602ffd19e8a9
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__cxx03/bitset
M libcxx/include/__cxx03/forward_list
M libcxx/include/__cxx03/list
M libcxx/test/std/containers/sequences/forwardlist/types.pass.cpp
M libcxx/test/std/containers/sequences/list/types.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/index_const.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/nonstdmem.uglified.compile.pass.cpp
Log Message:
-----------
[libc++][C++03] Backport #111127, #112843 and #121620 (#155571)
Commit: 90865906dd2d42311901ce8a567bb992a169860d
https://github.com/llvm/llvm-project/commit/90865906dd2d42311901ce8a567bb992a169860d
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/docs/analyzer/checkers.rst
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
R clang/lib/StaticAnalyzer/Checkers/CastSizeChecker.cpp
R clang/test/Analysis/castsize.c
M clang/test/Analysis/malloc-annotations.c
M clang/test/Analysis/malloc-annotations.cpp
M clang/test/Analysis/malloc.c
M clang/test/Analysis/malloc.cpp
M clang/test/Analysis/misc-ps.m
M clang/test/Analysis/qt_malloc.cpp
Log Message:
-----------
[clang][analyzer] Remove checker 'alpha.core.CastSize' (#156350)
Commit: 655cdf2e45a108177f013a59f108d17a8a267783
https://github.com/llvm/llvm-project/commit/655cdf2e45a108177f013a59f108d17a8a267783
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
Log Message:
-----------
llvm-tli-checker: Remove TLINameList helper struct (#142535)
This avoids subclassing std::vector and a static constructor.
This started as a refactor to make TargetLibraryInfo available during
printing so a custom name could be reported. It turns out this struct
wasn't doing anything, other than providing a hacky way of printing the
standard name instead of the target's custom name. Just remove this and
stop hacking on the TargetLibraryInfo to falsely report the function
is available later.
Commit: d0363815dd4acde08168e930cb529ee10f86b838
https://github.com/llvm/llvm-project/commit/d0363815dd4acde08168e930cb529ee10f86b838
Author: quic_hchandel <hchandel at qti.qualcomm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/xqcibm-insbi.ll
Log Message:
-----------
[RISCV] Add changes to have better coverage for qc.insb and qc.insbi (#154135)
Before this patch, the selection for `QC_INSB` and `QC_INSBI` entirely
happens in C++, and does not support more than one non-constant input.
This patch seeks to rectify this shortcoming, by moving the C++ into a
target-specific DAGCombine, and adding `RISCV::QC_INSB`. One advantage
is this simplifies the code for handling `QC_INSBI`, as the C++ no
longer needs to choose between the two instructions based on the
inserted value (this is still done, but via ISel Patterns).
Another advantage of the DAGCombine is that this introduction can also
shift the inserted value to the `QC_INSB`, which our patterns need (and
were previously doing to the constant), and this shift can be
CSE'd/optimised with any prior shifts, if they exist. This allows the
inserted value to be variable, rather than a constant.
Commit: 22e7c36b7e3bc8755ae4b856eb0da1249beb0d6c
https://github.com/llvm/llvm-project/commit/22e7c36b7e3bc8755ae4b856eb0da1249beb0d6c
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Log Message:
-----------
[RISCV] Remove remaining vmerge_vl mask patterns. NFC (#156566)
Now that RISCVVectorPeephole can commute operands to fold vmerge into a
pseudo to make it masked in #156499, we can remove the remaining
VPatMultiplyAccVL_VV_VX/VPatFPMulAccVL_VV_VF_RM patterns.
It also looks like we can remove the vmerge_vl patterns for _TIED
psuedos too. I suspect they're handled by convertAllOnesVMergeToVMv and
foldVMV_V_V
Tested on SPEC CPU 2017 and llvm-test-suite to confirm there's no
codegen change.
Fixes #141885
Commit: f1dcdaac09b9271e00aeb095735ef984ae69752b
https://github.com/llvm/llvm-project/commit/f1dcdaac09b9271e00aeb095735ef984ae69752b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__tree
Log Message:
-----------
[libc++] Refactor remaining __find_equal calls (#156594)
#147345 refactored `__find_equal`. Unfortunately there was a merge
conflict with another patch. This fixes up the problematic places.
Commit: fba17cdee1830951867ecfc7d40f7b6caa78310a
https://github.com/llvm/llvm-project/commit/fba17cdee1830951867ecfc7d40f7b6caa78310a
Author: David Green <david.green at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
Log Message:
-----------
[AArch64] Guard fptosi+sitofp patterns with one use checks. (#156407)
Otherwise we can end up with more instructions, needing to emit both
`fcvtzu w0, s0` and `fcvtzu s0, s0`.
Commit: da8f692e3e6ecc7f91e4d0ff945613cabc103c28
https://github.com/llvm/llvm-project/commit/da8f692e3e6ecc7f91e4d0ff945613cabc103c28
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
Log Message:
-----------
AMDGPU: Handle V->A MFMA copy from case with immediate src2 (#153023)
Handle a special case for copies from AGPR VGPR on the MFMA inputs.
If the "input" is really a subregister def, we will not see the
usual copy to VGPR for src2, only the read of the subregister def.
Not sure if this pattern appears in practice.
Commit: 852f40f63bab4d85919cef1a28a3ee50239c303f
https://github.com/llvm/llvm-project/commit/852f40f63bab4d85919cef1a28a3ee50239c303f
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Follow up for #154865
Commit: 0909f04dcec436a7956a86300eaaaac6fbfd681c
https://github.com/llvm/llvm-project/commit/0909f04dcec436a7956a86300eaaaac6fbfd681c
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/unittests/Analysis/IR2VecTest.cpp
Log Message:
-----------
IR2VecTest.cpp: Suppress a warning. [-Wunused-const-variable]
Commit: 5256924acca8530c311abe64b525ba5dffa02074
https://github.com/llvm/llvm-project/commit/5256924acca8530c311abe64b525ba5dffa02074
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Clarify semantics of objectsize min parameter (#156309)
LangRef currently only says that this determines the return value if the
object size if unknown. What it actually does is determine whether the
minimum or maximum size is reported, which degenerates to 0 or -1 if
unknown.
Fixes https://github.com/llvm/llvm-project/issues/156192.
Commit: e915d9addeae5431f869d9a10021382871c11169
https://github.com/llvm/llvm-project/commit/e915d9addeae5431f869d9a10021382871c11169
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/tools/f18/CMakeLists.txt
Log Message:
-----------
[flang] Do not create omp_lib.f18.mod files (#156311)
The build system used to create `.f18.mod` variants for all `.mod`
files, but this was removed in #85249. However, there is a leftover that
still creates these when building `openmp` in the project configuration.
It does not happen in the runtimes configuration.
Commit: 0f3ede911a2c54ae6c4cac9801edc28d83e4c6a0
https://github.com/llvm/llvm-project/commit/0f3ede911a2c54ae6c4cac9801edc28d83e4c6a0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsX86.td
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Headers/avx512fintrin.h
M clang/test/CodeGen/X86/avx512f-builtins.c
Log Message:
-----------
[X86] Allow AVX512 512-bit variants of AVX2 per-element i32 shift intrinsics to be used in constexpr (#156480)
Followup to #154780
Commit: 653c40365b9adf43ef766aeb7b6ef341598cceb5
https://github.com/llvm/llvm-project/commit/653c40365b9adf43ef766aeb7b6ef341598cceb5
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/CodeGen/X86/bswap-inline-asm.ll
Log Message:
-----------
[X86] Generate test checks (NFC)
Commit: d0d79fd1ac70602b3286bedbb75e42d3766c8019
https://github.com/llvm/llvm-project/commit/d0d79fd1ac70602b3286bedbb75e42d3766c8019
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
Log Message:
-----------
[AMDGPU] si-peephole-sdwa: reuse getOne{NonDBGUse,Def} (NFC) (#156455)
This patch changes the findSingleRegDef function from si-peephole-sdwa
to reuse MachineRegisterInfo::getOneDef and findSingleRefUse to use a
new MachineRegisterInfo::getOneNonDBGUse function.
Commit: 349523e26b80155b200e52e628006855371b6a93
https://github.com/llvm/llvm-project/commit/349523e26b80155b200e52e628006855371b6a93
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/IR/GEPNoWrapFlags.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/gep-canonicalize-constant-indices.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
Log Message:
-----------
[InstCombine] Merge constant offset geps across variable geps (#156326)
Fold:
%gep1 = ptradd %p, C1
%gep2 = ptradd %gep1, %x
%res = ptradd %gep2, C2
To:
%gep = ptradd %gep, %x
%res = ptradd %gep, C1+C2
An alternative to this would be to generally canonicalize constant
offset GEPs to the right. I found the results of doing that somewhat
mixed, so I'm going for this more obviously beneficial change for now.
Proof for flag preservation on reassociation:
https://alive2.llvm.org/ce/z/gmpAMg
Commit: 73bed64433072338d11ebf770d6db99c2ce810aa
https://github.com/llvm/llvm-project/commit/73bed64433072338d11ebf770d6db99c2ce810aa
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
A llvm/test/CodeGen/AArch64/scalable_masked_deinterleaved_loads.ll
Log Message:
-----------
[AArch64] Improve lowering for scalable masked deinterleaving loads (#154338)
For IR like this:
%mask = ... @llvm.vector.interleave2(<vscale x 16 x i1> %a, <vscale x 16
x i1> %a)
%vec = ... @llvm.masked.load(..., <vscale x 32 x i1> %mask, ...)
%dvec = ... @llvm.vector.deinterleave2(<vscale x 32 x i8> %vec)
where we're deinterleaving a wide masked load of the supported type
and with an interleaved mask we can lower this directly to a ld2b
instruction. Similarly we can also support other variants of ld2
and ld4.
This PR adds a DAG combine to spot such patterns and lower to ld2X
or ld4X variants accordingly, whilst being careful to ensure the
masked load is only used by the deinterleave intrinsic.
Commit: cd7f7cf5cca6fa425523a5af9fd42f82c6566ebf
https://github.com/llvm/llvm-project/commit/cd7f7cf5cca6fa425523a5af9fd42f82c6566ebf
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DebugOptions.h
M llvm/lib/Support/TypeSize.cpp
M llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
Log Message:
-----------
Reapply [IR] Remove options to make scalable TypeSize access a warning (#156336)
Reapplying now that buildbot has picked up the new configuration
that does not use -treat-scalable-fixed-error-as-warning.
-----
This removes the `LLVM_ENABLE_STRICT_FIXED_SIZE_VECTORS` cmake option
and the `-treat-scalable-fixed-error-as-warning` opt flag.
We stopped treating these as warnings by default a long time ago
(62f09d788f9fc540db12f3cfa2f98760071fca96), so I don't think it makes
sense to retain these options at this point. Accessing a scalable
TypeSize as fixed should always result in an error.
Commit: 759a2ac5b0ee09be9dbb51ad50143d7db990a94a
https://github.com/llvm/llvm-project/commit/759a2ac5b0ee09be9dbb51ad50143d7db990a94a
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__ranges/as_rvalue_view.h
M libcxx/test/std/ranges/range.adaptors/range.as.rvalue/adaptor.pass.cpp
Log Message:
-----------
[libc++][ranges] LWG4083: `views::as_rvalue` should reject non-input ranges (#155156)
Fixes #105351
# References:
- https://wg21.link/LWG4083
- https://wg21.link/range.as.rvalue.overview
Commit: be1e50f56af8e270a0396eef8f62626fbbb84996
https://github.com/llvm/llvm-project/commit/be1e50f56af8e270a0396eef8f62626fbbb84996
Author: Miguel Saldivar <miguel.saldivar at hpe.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/lib/Lower/ConvertConstant.cpp
Log Message:
-----------
[flang] Avoid unnecessary looping for constants (#156403)
Going through and doing `convertToAttribute` for all elements, if they
are the same can be costly. If the elements are the same, we can just
call `convertToAttribute` once.
This does give us a significant speed-up:
```console
$ hyperfine --warmup 1 --runs 5 ./slow.sh ./fast.sh
Benchmark 1: ./slow.sh
Time (mean ± σ): 1.606 s ± 0.014 s [User: 1.393 s, System: 0.087 s]
Range (min … max): 1.591 s … 1.628 s 5 runs
Benchmark 2: ./fast.sh
Time (mean ± σ): 452.9 ms ± 7.6 ms [User: 249.9 ms, System: 83.3 ms]
Range (min … max): 443.9 ms … 461.7 ms 5 runs
Summary
./fast.sh ran
3.55 ± 0.07 times faster than ./slow.sh
```
Fixes #125444
Commit: b16930204b230240d834f667c8f32b12ca4ad198
https://github.com/llvm/llvm-project/commit/b16930204b230240d834f667c8f32b12ca4ad198
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
Log Message:
-----------
[LV] Add additional tests for reasoning about dereferenceable loads.
Includes a test for the crash exposed by 08001cf340185877.
Commit: 7da91fa801d8bd490c8dcd9a29faba209feb2954
https://github.com/llvm/llvm-project/commit/7da91fa801d8bd490c8dcd9a29faba209feb2954
Author: David Sherwood <david.sherwood at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
Log Message:
-----------
[CodeGen] Fix failing assert in interleaved access pass (#156457)
In the InterleavedAccessPass the function getMask assumes that
shufflevector operations are always fixed width, which isn't true
because we use them for splats of scalable vectors. This patch fixes the
code by bailing out for scalable vectors.
Commit: 49ffe31defafd0cd87b2c194e57a02ad428fdae4
https://github.com/llvm/llvm-project/commit/49ffe31defafd0cd87b2c194e57a02ad428fdae4
Author: Vikash Gupta <Vikash.Gupta at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
Log Message:
-----------
[AMDGPU][LIT][NFC] Adding -mtriple for AMDGPUAnnotateUniformValues Pass tests (#156437)
It specifies the target machine as AMDGPU for
AMDGPUAnnotateUniformValues pass-related test (that uses UA). Before in
its absense, the UA would consider everything Uniform resulting in
setting metadata incorrectly for AMDGPU. Now, after specifying the
AMDGPU, the UA would be rightful sets the right metadata as the test
gets commpiled for AMDGPU.
Commit: 47de90e285aeec1acc8595c4b327cd823c069c90
https://github.com/llvm/llvm-project/commit/47de90e285aeec1acc8595c4b327cd823c069c90
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
A clang/test/Analysis/ctu-import-type-decl-definition.c
Log Message:
-----------
[clang] Fix crash 'Cannot get layout of forward declarations' during CTU static analysis (#156056)
When a type is imported with `ASTImporter`, the "original declaration"
of the type is imported. In some cases this is not the definition
(of the class). Before the fix the definition was only imported if
there was an other reference to it in the AST to import. This is not
always the case (like in the added test case), if not the definition
was missing in the "To" AST which can cause the assertion later.
Commit: 2f5500e4cf603ae080363f4f24df78d543972667
https://github.com/llvm/llvm-project/commit/2f5500e4cf603ae080363f4f24df78d543972667
Author: Mel Chen <mel.chen at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
Log Message:
-----------
[LV] Improve the test coverage for strided access. nfc (#155981)
Add tests for strided access with UF > 1, and introduce a new test case
@constant_stride_reinterpret.
Commit: 3576f05db125006ffbe22bfc199a269bf2a4a06f
https://github.com/llvm/llvm-project/commit/3576f05db125006ffbe22bfc199a269bf2a4a06f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
Log Message:
-----------
llvm-tli-checker: Avoid a temporary string while printing (#156605)
Directly write to the output instead of building a string to
print.
Closes #142538
Commit: a1bfa2f6a69b9bff45529809af932f0484795b90
https://github.com/llvm/llvm-project/commit/a1bfa2f6a69b9bff45529809af932f0484795b90
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
Log Message:
-----------
AMDGPU: Avoid directly using MCOperandInfo RegClass field (#156641)
This value should not be directly interpreted. Also avoids
a function only used for an assert.
Commit: d4de7809697842e99e4935974d54d3a1f829e59d
https://github.com/llvm/llvm-project/commit/d4de7809697842e99e4935974d54d3a1f829e59d
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
Log Message:
-----------
[AMDGPU] Use "v_bfi_b32 x, 0, z" to implement (z & ~x) (#156636)
Commit: 3bb6e60c1681300c44098a772f0a277dd12a9648
https://github.com/llvm/llvm-project/commit/3bb6e60c1681300c44098a772f0a277dd12a9648
Author: Gaëtan Bossu <gaetan.bossu at arm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/shuffle-extract.ll
A llvm/test/Analysis/CostModel/AArch64/sve-vls-shuffle-extract.ll
Log Message:
-----------
[AArch64] Update cost model for extracting halves from 128+ bit vectors (#155601)
Previously, only 128-bit "NEON" vectors were given sensible costs.
Cores with vscale>1 can use SVE's EXT instruction to perform a
fixed-length subvector extract.
This is a follow-up from the codegen patches at #152554. They show that
with the help of MOVPRFX, we can do subvector extracts with roughly one
instruction. We now at least give sensible costs for extracting 128-bit
halves from a 256-bit vector.
Commit: 8989ec5439dc2df2aeb7e5ea3e6c255ce8e9634d
https://github.com/llvm/llvm-project/commit/8989ec5439dc2df2aeb7e5ea3e6c255ce8e9634d
Author: Ricardo Jesus <rjj at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
Log Message:
-----------
[AArch64] Combine SEXT_INREG(CSET) to CSETM. (#156429)
Add the following patterns to performSignExtendInRegCombine:
* SIGN_EXTEND_INREG (CSEL 0, 1, cc), i1 --> CSEL 0, -1, cc
* SIGN_EXTEND_INREG (CSEL 1, 0, cc), i1 --> CSEL -1, 0, cc
The combined forms can be matched to a CSETM.
Commit: a434a7a4f12faf3e0231fc145f7fb2e02c623a97
https://github.com/llvm/llvm-project/commit/a434a7a4f12faf3e0231fc145f7fb2e02c623a97
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
Log Message:
-----------
Reapply "[LAA,Loads] Use loop guards and max BTC if needed when checking deref. (#155672)"
This reverts commit f0df1e3dd4ec064821f673ced7d83e5a2cf6afa1.
Recommit with extra check for SCEVCouldNotCompute. Test has been added in
b16930204b.
Original message:
Remove the fall-back to constant max BTC if the backedge-taken-count
cannot be computed.
The constant max backedge-taken count is computed considering loop
guards, so to avoid regressions we need to apply loop guards as needed.
Also remove the special handling for Mul in willNotOverflow, as this
should not longer be needed after 914374624f
(https://github.com/llvm/llvm-project/pull/155300).
PR: https://github.com/llvm/llvm-project/pull/155672
Commit: 2ee567110c4cb9d562d03b690799c4f040b2a06c
https://github.com/llvm/llvm-project/commit/2ee567110c4cb9d562d03b690799c4f040b2a06c
Author: Mario Camillo <mario.camillo at imgtec.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/test/Dialect/Tosa/level_check.mlir
Log Message:
-----------
[mlir][tosa] handle unranked tensors in tosa::table::verify (#156321)
Seen when running TOSA PRO-INT conformance tests in our SUT. This leads
to verify being called with unranked tensors causing exception/error
when trying to call getShape on them.
Made some variables const for consistency with other verify functions in
same file.
Commit: 27e541645c2a99cba6ae8705f2969f523410ef4c
https://github.com/llvm/llvm-project/commit/27e541645c2a99cba6ae8705f2969f523410ef4c
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M offload/test/offloading/mandatory_but_no_devices.c
M offload/test/offloading/memory_manager.cpp
Log Message:
-----------
[Offload][OpenMP] Enable more tests on AMDGPU (#156626)
(Re)enables a couple of tests that were disabled on AMDGPU for some
reason. Pass for me locally.
Commit: 38b376f1927df5c1dea1065041779b28b13b9dd9
https://github.com/llvm/llvm-project/commit/38b376f1927df5c1dea1065041779b28b13b9dd9
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/IR/DataLayout.cpp
Log Message:
-----------
[DataLayout] Use linear scan to determine integer alignment (NFC)
The number of alignment entries is usually very small (5-7), so
it is more efficient to use a linear scan than a binary search.
Commit: 298764a250150752b556b3212af955e1e2a01877
https://github.com/llvm/llvm-project/commit/298764a250150752b556b3212af955e1e2a01877
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
A mlir/test/Conversion/FuncToLLVM/func-to-llvm-datalayout.mlir
Log Message:
-----------
[mlir][ToLLVM] Fix the index bitwidth handling for the dynamic case of `convert-to-llvm` (#156557)
This patch changes the behavior of `convert-to-llvm{dynamic=true}` so
that the nearest `DataLayout` is used to configure LowerToLLVMOptions
and LLVMTypeConverter.
Example:
```mlir
module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 16>>} {
func.func private @test_16bit_index(%arg0: index) -> index
}
// mlir-opt --convert-to-llvm="dynamic=true"
module attributes {dlti.dl_spec = #dlti.dl_spec<index = 16 : i64>} {
llvm.func @test_16bit_index(i16) -> i16 attributes {sym_visibility = "private"}
}
```
Commit: dc05c5dd12a952df82a7c843b1b3d05ea1ef21c0
https://github.com/llvm/llvm-project/commit/dc05c5dd12a952df82a7c843b1b3d05ea1ef21c0
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/lldb/LLDB.py
Log Message:
-----------
[Dexter] Use continue when resuming lldb execution to reach breakpoint (#156481)
Currently, Dexter's interface for lldb and lldb-dap has a post-step hook
that checks to see whether lldb reports that we stopped because we
completed a step, and if so checks to see whether the current $pc
address also matches a known breakpoint whose conditions (if any) are
met, and if so it requests to "step in", so that we "resume" execution,
stopping again at the current address, such that lldb now reports that
we have hit a breakpoint and provides the list of breakpoints that were
hit.
This logic has a flaw however: the call to "step in" sets an implicit
breakpoint on the next line. In Dexter's default stepping mode this is
not an issue, as we intend to step there eventually. When we use
DexContinue, however, we set a breakpoint from which we wish to continue
to the next user-specified breakpoint, rather than stepping. Currently,
there is a bug where Dexter sets a DexContinue breakpoint, arrives at
that bp from a step, requests "step in" so that LLDB gives us the hit
breakpoint ID, requests "continue" to hit the next user breakpoint, and
then arrives at the next line after the continue due to the earlier
"step in" request. This effectively negates the DexContinue command.
This patch fixes this behaviour by using "continue" instead of "step in"
in the post-step hook, ensuring that no implicit breakpoint is set so
that we do not incorrectly stop at the next line.
Commit: d29dc18992c85c5ef20f5958f55ed1713c1e215c
https://github.com/llvm/llvm-project/commit/d29dc18992c85c5ef20f5958f55ed1713c1e215c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Log Message:
-----------
AMDGPU: Remove dead code for printing DFP immediates (#156644)
Nothing in the backend uses these, so there's no reason
to support printing them.
Commit: 3f4d116978044e2acc5e9a36196cf2a7d790319e
https://github.com/llvm/llvm-project/commit/3f4d116978044e2acc5e9a36196cf2a7d790319e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M bolt/runtime/instr.cpp
Log Message:
-----------
[BOLT] close map_files FD (#156489)
The BOLT runtime currently does not close the FD pointing to
/proc/self/map_files. This does not actually hurt anything but was at
least a bit of a red herring for me when looking through strace on a
BOLT instrumented binary.
Commit: 71641049a91253f7547f792ec2fcb6609794ea4f
https://github.com/llvm/llvm-project/commit/71641049a91253f7547f792ec2fcb6609794ea4f
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libc/src/__support/threads/thread.cpp
M libc/src/__support/threads/thread.h
M libc/src/stdlib/exit.cpp
M libc/test/integration/src/__support/threads/CMakeLists.txt
A libc/test/integration/src/__support/threads/double_exit_test.cpp
A libc/test/integration/src/__support/threads/main_exit_test.cpp
Log Message:
-----------
[libc] ensure tls dtors are called in main thread (#133641)
This is a part of allocator patch since I want to make sure the TLS for
allocators are correctly handled.
TLS dtors are not invoked on exit previously. This departures from major
libc implementations.
This PR fixes the issue by aligning the behavior with bionic.
https://android.googlesource.com/platform/bionic/+/refs/heads/main/libc/bionic/exit.cpp
I believe the finalization order is also consistent with glibc now:
On main thread exiting:
- pthread_key dtors are not called (unless exiting with `pthread_exit`)
- `__cxa` based tls dtors are called
- `::__cxa_atexit` and `::atexit` dtors are called
- `.fini` dtors are called
Commit: ee71af4fc7e62981da3d73a917ef1919e6d4c2d8
https://github.com/llvm/llvm-project/commit/ee71af4fc7e62981da3d73a917ef1919e6d4c2d8
Author: Lakshay Kumar <lakshayk at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
A llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
M llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
Log Message:
-----------
[llvm-exegesis] [AArch64] Reland Resolving "not all operands are initialized by snippet generator" (#156423)
### Reland #142529 (Resolving "not all operands are initialized by
snippet generator")
Introduced changes in implementation of `randomizeTargetMCOperand()` for
AArch64 that omitting `OPERAND_SHIFT_MSL`, `OPERAND_PCREL` to an
immediate value of 264 and 8 respectively.
PS: Omitting
`MCOI::OPERAND_FIRST_TARGET/llvm:AArch64:OPERAND_IMPLICIT_IMM_0`
similarly, to value 0. It was low hanging change thus added in this PR
only.
For any future operand type of AArch64 if not initialised will exit with
error "`Unimplemented operand type: MCOI::OperandType:<#Number>`".
#### [Reland Updates]
Updated `tools/llvm-exegesis/AArch64/error-resolution.s` which caused
problem.
Test case was failing when there is uninitialised operands error coming
from secondary/consumer instruction used by exegesis in latency mode
required to chain up the assembly to ensure serial execution.
i.e. We get error message like `UMOVvi16_idx0: Not all operands were
initialized by the snippet generator for <<<any opcode other than
UMOVvi16_idx0>>> opcode.` but test case want to check like
`# UMOVvi16_idx0_latency: ---`. Thus the testcase fails.
```+ /llvm-project/build/bin/FileCheck /llvm-project/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s --check-prefix=UMOVvi16_idx0_latency
/llvm-project/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s:65:26: error: UMOVvi16_idx0_latency: expected string not found in input
# UMOVvi16_idx0_latency: ---
^
<stdin>:1:1: note: scanning from here
UMOVvi16_idx0: Not all operands were initialized by the snippet generator for LD1W_D_IMM opcode.
^
Input file: <stdin>
Check file: /llvm-project/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
-dump-input=help explains the following input dump.
Input was:
<<<<<<
1: UMOVvi16_idx0: Not all operands were initialized by the snippet generator for LD1W_D_IMM opcode.
check:65 X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
>>>>>>
--
********************
********************
Failed Tests (1):
LLVM :: tools/llvm-exegesis/AArch64/error-resolution.s
```
#### [Why it fails (only sometimes)]
Exegesis in latency mode require the generated assembly to be chained to
ensure serial execution,
For this exegesis add an additional consumer instruction for some
instruction, which is chosen via a random seed.
Thus, it randomly fails whenever there is secondary consumer instruction
(which is unsupported/throws error) added in generated assembly.
Commit: 9f9b480dea3bd26b133e30d56e37f8ab0007f26d
https://github.com/llvm/llvm-project/commit/9f9b480dea3bd26b133e30d56e37f8ab0007f26d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[AArch64] Add computeKnownBits unit test coverage for AArch64ISD::VASHR/VLSHR/VSHL (#156631)
Base tests so we can add additional FREEZE tests on top in #156445
Commit: 5e924fa7640041f7081deed9787dc10d8007e7f9
https://github.com/llvm/llvm-project/commit/5e924fa7640041f7081deed9787dc10d8007e7f9
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
A clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-unsigned-int.c
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
Log Message:
-----------
[OpenACC] Reduction 'init' lowering for all-ones/least/largest (#156535)
As a follow on to the last patches of this form, this patch does the
init section for all of the reduction operators that weren't previously
covered, which is '&' as all-ones, 'max' as 'least', and 'min' as
'largest'.
Commit: 913d44da833674be59b1713dfdb1cde8fea2a842
https://github.com/llvm/llvm-project/commit/913d44da833674be59b1713dfdb1cde8fea2a842
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/IR/EnumAttr.td
M mlir/test/IR/array-of-attr.mlir
M mlir/test/lib/Dialect/Test/TestEnumDefs.td
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/test/mlir-tblgen/attr-or-type-format.td
Log Message:
-----------
[mlir][IR] Fix enum attribute handling by using parseKeywordOrString instead of parseKeyword (#156662)
Change enum attribute parsing to handle special characters and
multi-word
identifiers. This allows enum attrs to use symbols like "+" and strings
with separators like "dash-separated-sentence" instead of being limited
to
valid identifiers.
This also aligns enum attribute parsing with how enums are already
handled
by the `FieldParser`:
https://github.com/llvm/llvm-project/blob/main/mlir/tools/mlir-tblgen/EnumsGen.cpp#L108
Signed-off-by: Fabian Mora <fabian.mora-cordero at amd.com>
Commit: 44b779526036a62aa2f7c5285a51f5c043805c33
https://github.com/llvm/llvm-project/commit/44b779526036a62aa2f7c5285a51f5c043805c33
Author: Shamshura Egor <164661612+egorshamshura at users.noreply.github.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags-std.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags.cpp
Log Message:
-----------
[Clang] Add detailed notes explaining why is_aggregate evaluates to false (#152488)
This PR is part of
[#141911](https://github.com/llvm/llvm-project/issues/141911)
---------
Co-authored-by: Erich Keane <ekeane at nvidia.com>
Commit: 48d445a9713577576f03c6ddb11a4fa782838a4f
https://github.com/llvm/llvm-project/commit/48d445a9713577576f03c6ddb11a4fa782838a4f
Author: Lucas <github.snugness349 at passinbox.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/www/features.html
Log Message:
-----------
[clang][www] Documentation revision and proof read for features.html (#156620)
This is mostly just a small proof read for the
https://clang.llvm.org/features.html documentation page.
The changes include some typo fixes and suggestions I've found would be
useful.
---------
Co-authored-by: Lucas Mellone <lucasmellone at MAC-MINI.station>
Co-authored-by: lknknm <sxswt at protonmail.com>
Commit: fdace1ca454316d35d7fcbf4e0a0aa747aac57f2
https://github.com/llvm/llvm-project/commit/fdace1ca454316d35d7fcbf4e0a0aa747aac57f2
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Extract SCEVExpander from `calculateRtStride`, NFC
Make `calculateRtStride` return the SCEV of rt stride value and let the
caller expand it where needed.
Commit: b5f6ce6a1f5a8f42f9506f3a1b17b80b30e3e717
https://github.com/llvm/llvm-project/commit/b5f6ce6a1f5a8f42f9506f3a1b17b80b30e3e717
Author: Erick Ochoa Lopez <erick.ochoalopez at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Conversion/Passes.td
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/test/Conversion/VectorToLLVM/use-vector-alignment.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
Log Message:
-----------
[mlir][vector] Propagate alignment from vector to llvm dialects. (#153482)
Allows alignment to be propagated correctly from vector to LLVM dialect
operations.
Commit: 6bbf0c30ca4449e325beb2d28db00d258d3a1a10
https://github.com/llvm/llvm-project/commit/6bbf0c30ca4449e325beb2d28db00d258d3a1a10
Author: Fei Peng <airpfei at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Log Message:
-----------
[sanitizer] Fix prctl interceptor causing PAC authentication failure (#153081)
The root cause of this crash is that prctl(PR_PAC_RESET_KEYS) generates
a new PAC key. As a result, paciasp and autiasp use different keys,
leading to the crash.
The solution is: if prctl's option is PR_PAC_RESET_KEYS, call real_prctl
directly. This is implemented in assembly, so there are no PAC
instructions involved.
Related issue: https://github.com/android/ndk/issues/1848
```
0000000000095468 <__interceptor_prctl>:
95468: d503233f paciasp
9546c: d10183ff sub sp, sp, #0x60
95470: a90267fe stp x30, x25, [sp, #0x20]
95474: a9035ff8 stp x24, x23, [sp, #0x30]
95478: a90457f6 stp x22, x21, [sp, #0x40]
9547c: a9054ff4 stp x20, x19, [sp, #0x50]
95480: aa1e03f4 mov x20, x30
95484: aa0403f3 mov x19, x4
95488: aa0303f6 mov x22, x3
9548c: aa0203f7 mov x23, x2
95490: aa0103f5 mov x21, x1
95494: 2a0003f8 mov w24, w0
95498: 940172ec bl 0xf2048 <_ZN6__tsan10cur_threadEv>
9549c: 4f05e540 movi v0.16b, #0xaa
954a0: 52801548 mov w8, #0xaa // =170
954a4: aa1403fe mov x30, x20
954a8: 39007fe8 strb w8, [sp, #0x1f]
954ac: aa0003f4 mov x20, x0
954b0: 910043e0 add x0, sp, #0x10
954b4: aa1403e1 mov x1, x20
954b8: bc01b3e0 stur s0, [sp, #0x1b]
954bc: d50320ff xpaclri
954c0: aa1e03e3 mov x3, x30
954c4: 97ffb461 bl 0x82648 <_ZN6__tsan17ScopedInterceptorC2EPNS_11ThreadStateEPKcm>
954c8: 97ff75ea bl 0x72c70 <_ZN11__sanitizer10StackTrace12GetCurrentPcEv>
954cc: 394c2688 ldrb w8, [x20, #0x309]
954d0: 7100051f cmp w8, #0x1
954d4: 540000c1 b.ne 0x954ec <__interceptor_prctl+0x84>
954d8: b9400a88 ldr w8, [x20, #0x8]
954dc: 35000088 cbnz w8, 0x954ec <__interceptor_prctl+0x84>
954e0: 394c2288 ldrb w8, [x20, #0x308]
954e4: 7100051f cmp w8, #0x1
954e8: 54000501 b.ne 0x95588 <__interceptor_prctl+0x120>
954ec: f0001128 adrp x8, 0x2bc000 <_ZN6__tsanL23interceptor_placeholderE+0xcac0>
954f0: 2a1803e0 mov w0, w24
954f4: aa1503e1 mov x1, x21
954f8: f9452508 ldr x8, [x8, #0xa48]
954fc: aa1703e2 mov x2, x23
95500: aa1603e3 mov x3, x22
95504: aa1303e4 mov x4, x19
95508: d63f0100 blr x8
9550c: f9400bf3 ldr x19, [sp, #0x10]
95510: 394c2668 ldrb w8, [x19, #0x309]
95514: 7100051f cmp w8, #0x1
95518: 540002a1 b.ne 0x9556c <__interceptor_prctl+0x104>
9551c: 39406be8 ldrb w8, [sp, #0x1a]
95520: 7100051f cmp w8, #0x1
95524: 54000d60 b.eq 0x956d0 <__interceptor_prctl+0x268>
95528: 394067e8 ldrb w8, [sp, #0x19]
9552c: 7100051f cmp w8, #0x1
95530: 54000de0 b.eq 0x956ec <__interceptor_prctl+0x284>
95534: b9400a68 ldr w8, [x19, #0x8]
95538: 350001a8 cbnz w8, 0x9556c <__interceptor_prctl+0x104>
9553c: b9403268 ldr w8, [x19, #0x30]
95540: 35000e48 cbnz w8, 0x95708 <__interceptor_prctl+0x2a0>
95544: f9400e68 ldr x8, [x19, #0x18]
95548: 91002109 add x9, x8, #0x8
9554c: f27c1d3f tst x9, #0xff0
95550: 54000ec0 b.eq 0x95728 <__interceptor_prctl+0x2c0>
95554: 5280004a mov w10, #0x2 // =2
95558: f900010a str x10, [x8]
9555c: f9000e69 str x9, [x19, #0x18]
95560: f9400a68 ldr x8, [x19, #0x10]
95564: d1002108 sub x8, x8, #0x8
95568: f9000a68 str x8, [x19, #0x10]
9556c: a9454ff4 ldp x20, x19, [sp, #0x50]
95570: a94457f6 ldp x22, x21, [sp, #0x40]
95574: a9435ff8 ldp x24, x23, [sp, #0x30]
95578: a94267fe ldp x30, x25, [sp, #0x20]
9557c: 910183ff add sp, sp, #0x60
95580: d50323bf autiasp
95584: d65f03c0 ret
...
```
Commit: 20b4f59ccad51e26e7cbd8b317c9f331d1ada6e5
https://github.com/llvm/llvm-project/commit/20b4f59ccad51e26e7cbd8b317c9f331d1ada6e5
Author: Shreeyash Pandey <shreeyash335 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/unittests/Target/RISCV/CMakeLists.txt
A llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp
Log Message:
-----------
[RISCV] add computeKnownBitsForTargetNode for RISCVISD::SRLW (#155995)
I've added support for computeKnownBitsForTargetNode for the SRLW
instruction. A test has been included which uses the snippet of IR as
suggested by topperc.
Fixed #154913
---------
Signed-off-by: Shreeyash Pandey <shreeyash335 at gmail.com>
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>
Commit: 86879d46f6476386dc07772ede83cd43b6ddd739
https://github.com/llvm/llvm-project/commit/86879d46f6476386dc07772ede83cd43b6ddd739
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/pr156256.ll
Log Message:
-----------
[X86] Only fold AND/ANDNP back to VSELECT if we know the predicated mask select is legal (#156663)
By only checking type legality we didn't account for 128/256-bit ops
being run on non-AVX512VL targets, or vXi8/i16 ops being run on
non-AVX512BW targets
This check is cropping up in several places now and I intend to hoist it
out into a common helper, but this initial fix needs to be as clean as
possible to be back ported to 21.X
Fixes #156256
Commit: d15998fe64619e1cc0d6285fbd24d5fe5429c9ef
https://github.com/llvm/llvm-project/commit/d15998fe64619e1cc0d6285fbd24d5fe5429c9ef
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/ptr.mlir
Log Message:
-----------
[mlir][ptr] Add translations to LLVMIR for ptr ops. (#156355)
Implements translation from ptr dialect to LLVM IR for core pointer
operations:
- `ptr.ptr_add` -> `getelementptr`
- `ptr.load` -> `load` with atomic ordering, volatility, and metadata
support
- `ptr.store` -> `store` with atomic ordering, volatility, and metadata
support
- `ptr.type_offset` -> GEP-based size computation
Example:
```mlir
llvm.func @test(%arg0: !ptr.ptr<#llvm.address_space<0>>) {
%0 = ptr.type_offset f64 : i32
%1 = ptr.ptr_add inbounds %arg0, %0 : !ptr.ptr<#llvm.address_space<0>>, i32
%2 = ptr.load volatile %1 : !ptr.ptr<#llvm.address_space<0>> -> f64
ptr.store %2, %arg0 : f64, !ptr.ptr<#llvm.address_space<0>>
llvm.return
}
```
Translates to:
```llvm
define void @test(ptr %0) {
%2 = getelementptr inbounds i8, ptr %0, i32 8
%3 = load volatile double, ptr %2, align 8
store double %3, ptr %0, align 8
ret void
}
```
Commit: 47793f9a73314a7669f436ee6e0528203c8633e7
https://github.com/llvm/llvm-project/commit/47793f9a73314a7669f436ee6e0528203c8633e7
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/ExpandFp.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/lib/CodeGen/ExpandFp.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem-inf.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/lit.local.cfg
Log Message:
-----------
[AMDGPU] Implement IR expansion for frem instruction (#130988)
This patch implements a correctly rounded expansion of the frem
instruction in LLVM IR. This is useful for target architectures for
which such an expansion is too involved to be implement in ISel
Lowering. The expansion is based on the code from the AMD device libs
and has been tested successfully against the OpenCL conformance tests on
amdgpu. The expansion is implemented in the preexisting "expand-fp"
pass. It replaces the expansion of "frem" in ISel for the amdgpu target;
it is enabled for targets which do not directly support "frem" and for
which no matching "fmod" LibCall is available.
---------
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: 0f032f1925389394802a86318ebc51b5e83f3b97
https://github.com/llvm/llvm-project/commit/0f032f1925389394802a86318ebc51b5e83f3b97
Author: Utkarsh Saxena <usx at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Analysis/LifetimeSafety.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
Log Message:
-----------
[LifetimeSafety] Fix duplicate loan generation for ImplicitCastExpr (#153661)
This PR fixes a bug in the lifetime safety analysis where `ImplicitCastExpr` nodes were causing duplicate loan generation. The changes:
1. Remove the recursive `Visit(ICE->getSubExpr())` call in `VisitImplicitCastExpr` to prevent duplicate processing of the same expression
2. Ensure the CFG build options are properly configured for lifetime safety analysis by moving the flag check earlier
3. Enhance the unit test infrastructure to properly handle multiple loans per variable
4. Add a test case that verifies implicit casts to const don't create duplicate loans
5. Add a test case for ternary operators with a FIXME note about origin propagation
These changes prevent the analysis from generating duplicate loans when expressions are wrapped in implicit casts, which improves the accuracy of the lifetime safety analysis.
Commit: e6c63d920dec3e8874ac1dc3c3f19fb822f0ab06
https://github.com/llvm/llvm-project/commit/e6c63d920dec3e8874ac1dc3c3f19fb822f0ab06
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A clang/test/OpenMP/spirv_locstr.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Use target global AS for SrcLocStr (#156520)
We should set the correct target-specific AS for the SrcLocStr global
created in OMPIRBuilder.
We also may have to insert a constexpr addrspacecast because the struct
field type may be different than the value used to initialize it.
I actually want the cast to be from AS 1 to AS 4, but getting the type
to be AS4 relies on a PR currently in-review, so leave the cast target
to AS 0 for now.
---------
Signed-off-by: Sarnie, Nick <nick.sarnie at intel.com>
Commit: 34e9f3d6e3757d4e6a13a3f3df32a134933b6e7b
https://github.com/llvm/llvm-project/commit/34e9f3d6e3757d4e6a13a3f3df32a134933b6e7b
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/IR/OpBase.td
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Target/LLVMIR/ptr.mlir
Log Message:
-----------
[mlir][ptr] Add `gather`, `masked_load`, `masked_store`, and `scatter` ops (#156368)
This patch adds the `gather`, `masked_load`, `masked_store`, and
`scatter` operations to the `ptr` dialect. It also implements
translation from these operations to LLVM intrinsics:
- ptr.gather -> llvm.masked.gather
- ptr.masked_load -> llvm.masked.load
- ptr.masked_store -> llvm.masked.store
- ptr.scatter -> llvm.masked.scatter
Example:
```mlir
llvm.func @mixed_masked_ops_address_spaces(%ptr: !ptr.ptr<#llvm.address_space<3>>, %ptrs: vector<4x!ptr.ptr<#llvm.address_space<3>>>,
%mask: vector<4xi1>, %value: vector<4xf64>, %passthrough: vector<4xf64>) {
%0 = ptr.gather %ptrs, %mask, %passthrough alignment = 8 : vector<4x!ptr.ptr<#llvm.address_space<3>>> -> vector<4xf64>
ptr.scatter %value, %ptrs, %mask alignment = 8 : vector<4xf64>, vector<4x!ptr.ptr<#llvm.address_space<3>>>
%1 = ptr.masked_load %ptr, %mask, %passthrough alignment = 8 : !ptr.ptr<#llvm.address_space<3>> -> vector<4xf64>
ptr.masked_store %value, %ptr, %mask alignment = 8 : vector<4xf64>, !ptr.ptr<#llvm.address_space<3>>
llvm.return
}
```
Translates to:
```llvm
define void @mixed_masked_ops_address_spaces(ptr addrspace(3) %0, <4 x ptr addrspace(3)> %1, <4 x i1> %2, <4 x double> %3, <4 x double> %4) {
%6 = call <4 x double> @llvm.masked.gather.v4f64.v4p3(<4 x ptr addrspace(3)> %1, i32 8, <4 x i1> %2, <4 x double> %4)
call void @llvm.masked.scatter.v4f64.v4p3(<4 x double> %3, <4 x ptr addrspace(3)> %1, i32 8, <4 x i1> %2)
%7 = call <4 x double> @llvm.masked.load.v4f64.p3(ptr addrspace(3) %0, i32 8, <4 x i1> %2, <4 x double> %4)
call void @llvm.masked.store.v4f64.p3(<4 x double> %3, ptr addrspace(3) %0, i32 8, <4 x i1> %2)
ret void
}
```
Commit: e8755e71c770bf65a26842ed68262336d2508dfc
https://github.com/llvm/llvm-project/commit/e8755e71c770bf65a26842ed68262336d2508dfc
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/ADT/PriorityWorklist.h
Log Message:
-----------
[ADT] "Inline" TestAndEraseFromMap into PriorityWorklist.h (NFC) (#156596)
TestAndEraseFromMap is used only from PriorityWorklist::erase_if.
This patch "inlines" the struct into its sole user in the form of a
lambda function, eliminating a lot of boilerplate code.
Commit: 07e30043117c87f30a4505f2858a27ed0e2ea012
https://github.com/llvm/llvm-project/commit/07e30043117c87f30a4505f2858a27ed0e2ea012
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/Support/YAMLTraits.h
Log Message:
-----------
[Support] Modernize YAML traits with is_detected (NFC) (#156598)
This patch modernizes has_* YAML traits with is_detected.
The resulting code should be a lot more readable because all the
SFINAE logic is hidden behind is_detected.
One note about has_FlowTraits. The original code uses a complex trick
to detect a member variable named "flow", intentionally triggering
ambiguity with "flow" in the two base classes. I've simplified the
check down to:
template <class U> using check = decltype(&U::flow);
without using SameType. The use of SameType here would make the trait
unnecessarily complicated.
While I am at it, this patch switches to "static constexpr bool".
Commit: d77aafbeee174449d590aaef656ea7f5ea001303
https://github.com/llvm/llvm-project/commit/d77aafbeee174449d590aaef656ea7f5ea001303
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Remove an unnecessary cast (NFC) (#156599)
getSExtValue already returns int64_t.
Commit: 94e0c46498e061d8d40774417ce121904c8c4524
https://github.com/llvm/llvm-project/commit/94e0c46498e061d8d40774417ce121904c8c4524
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
Log Message:
-----------
[RISCV] Remove an unnecessary cast (NFC) (#156600)
*MF is already non const.
Commit: fd2a21d41abf3a1b33824db740272d9d8ab25a6d
https://github.com/llvm/llvm-project/commit/fd2a21d41abf3a1b33824db740272d9d8ab25a6d
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/docs/AddingConstrainedIntrinsics.rst
Log Message:
-----------
[llvm] Proofread AddingConstrainedIntrinsics.rst (#156601)
Commit: d25d8309d173f81bc26babf9964d4d021b76a4af
https://github.com/llvm/llvm-project/commit/d25d8309d173f81bc26babf9964d4d021b76a4af
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
Log Message:
-----------
[NFC] Remove trailing whitespaces from two files
Commit: 25a304559a7aba8ea7035dd68af2d9078a1a2826
https://github.com/llvm/llvm-project/commit/25a304559a7aba8ea7035dd68af2d9078a1a2826
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
Log Message:
-----------
[lldb][ExpressionParser][NFC] Clean up expression language picking logic (#156642)
This patch moves the `frame_lang` logic to just the logging (because
that's what it was always used for anyway). The callsites decide whether
to fall back on to the frame language or not when running the
expression.
Commit: fd6a2b84e7a9c4d345eea2b07bce65311f02c75f
https://github.com/llvm/llvm-project/commit/fd6a2b84e7a9c4d345eea2b07bce65311f02c75f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Log Message:
-----------
[NFC][MC][ARM] Rearrange decoder functions 3/N (#156240)
Commit: 9d7449a82b83ee589b8af8d6f86525727788b3b9
https://github.com/llvm/llvm-project/commit/9d7449a82b83ee589b8af8d6f86525727788b3b9
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/ARM/MVETailPredication.cpp
Log Message:
-----------
[NFC][LLVM] Use `INITILIZE_PASS` instead of `INITIALIZE_PASS_BEGIN/END` (#156212)
Commit: 53fce759fb35f2a162bc7bcc1e56911643b0e7a8
https://github.com/llvm/llvm-project/commit/53fce759fb35f2a162bc7bcc1e56911643b0e7a8
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang-tools-extra/clang-tidy/readability/UppercaseLiteralSuffixCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp
Log Message:
-----------
[clang-tidy] Fix `readability-uppercase-literal-suffix` warning with hex literals (#156584)
This is a regression I introduced in #148275 and was [noticed
by](https://github.com/llvm/llvm-project/pull/148275#issuecomment-3246670841)
nettle. The check incorrectly fires on hex literals containing the
letter `b`.
(I felt a revert was unnecessary in this case. Maybe others disagree?)
Commit: a2693dc192366372da4170c82d1b0719066ded95
https://github.com/llvm/llvm-project/commit/a2693dc192366372da4170c82d1b0719066ded95
Author: David Pagan <dave.pagan at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/scan_messages.cpp
M clang/test/OpenMP/target_data_use_device_addr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_messages.cpp
M clang/test/OpenMP/task_in_reduction_message.cpp
M clang/test/OpenMP/taskgroup_task_reduction_messages.cpp
M clang/test/OpenMP/teams_reduction_messages.cpp
Log Message:
-----------
[clang][OpenMP] 6.0: detect privatization of array section/assumed-size array (#152786)
According to the OpenMP 6.0 specification, array sections with no length
and unknown size are considered assumed-size arrays. As of pull request
https://github.com/llvm/llvm-project/pull/148048
these types of array sections are allowed and can be specified in
clauses that allow array sections as list items. However, only two
clauses explicitly allow array sections that are assumed-size arrays:
- 'map' and 'use_device_addr'.
The other clauses that accept array sections do not explicitly accept
assumed-size arrays:
- inclusive, exclusive, has_device_addr, in_reduction, task_reduction,
reduction These cases should generate an error. See OpenMP 6.0
specification section 7.4 List Item Privatization, Restrictions, p. 222,
L15
Assumed-size arrays must not be privatized
For OpenMP 6.0, function getPrivateItem() now checks for array section
list items that are assumed-size arrays and generates an error if they
are not allowed for the clause.
Testing
- Updated LIT tests for assumed-size array sections to ensure these
clauses generate an error: inclusive, exclusive, has_device_addr,
in_reduction, task_reduction, reduction and that this clause is accepted
(codegen test): use_device_addr
- check-all
- OpenMP_VV (sollve_vv)
Commit: 5cf12458433a74859a5d90c8e5163ba1b2b717f5
https://github.com/llvm/llvm-project/commit/5cf12458433a74859a5d90c8e5163ba1b2b717f5
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/unittests/Target/RISCV/CMakeLists.txt
Log Message:
-----------
Fix build break in RISCV unit tests
/usr/bin/ld: unittests/Target/RISCV/CMakeFiles/RISCVTests.dir/RISCVSelectionDAGTest.cpp.o: undefined reference to symbol '_ZN4llvm19parseAssemblyStringENS_9Stri
ngRefERNS_12SMDiagnosticERNS_11LLVMContextEPNS_11SlotMappingE'
/usr/bin/ld: lib/libLLVMAsmParser.so.22.0git:
error adding symbols: DSO missing from command line
collect2: error: ld returned 1 exit status
Commit: 28646140110f11e83926b0e48ce052d1de1c4a04
https://github.com/llvm/llvm-project/commit/28646140110f11e83926b0e48ce052d1de1c4a04
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for d15998fe64619e1cc0d6285fbd24d5fe5429c9ef
Commit: 1efbd8e62cfb5aedd791396c7ca854066e027d33
https://github.com/llvm/llvm-project/commit/1efbd8e62cfb5aedd791396c7ca854066e027d33
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
Log Message:
-----------
[bazel][mlir] Port #156355: translations to LLVMIR for ptr ops (#156689)
Commit: 329b21505a5f26d85955664943b0e0ac3411e11b
https://github.com/llvm/llvm-project/commit/329b21505a5f26d85955664943b0e0ac3411e11b
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/test/Transforms/debug-allocatable-1.fir
M flang/test/Transforms/debug-assumed-rank-array.fir
M flang/test/Transforms/debug-assumed-shape-array-2.fir
M flang/test/Transforms/debug-assumed-shape-array.fir
M flang/test/Transforms/debug-ptr-type.fir
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/test/Dialect/LLVMIR/debuginfo.mlir
Log Message:
-----------
[MLIR][LLVM][Flang] Move the element param of DICompositeType to the end (#156624)
This commit moves the "element" param of `DICompositeType` to the end of
the parameter list. This is required as there seems to be a bug in the
attribute parser that breaks a print + parse roundtrip.
Related ticket: https://github.com/llvm/llvm-project/issues/156623
Commit: 99f61f34362b77c42c8261213256854516c7485d
https://github.com/llvm/llvm-project/commit/99f61f34362b77c42c8261213256854516c7485d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M offload/test/CMakeLists.txt
Log Message:
-----------
[Offload] Run unit tests as a part of check-offload (#156675)
Summary:
Add a dependnecy on the unit tests on the main check-offload test suite.
This matches what the other projects do, pass `llvm-lit` to the
directory to only run the lit tests, use the `check-offload-unit` for
only the unit tests.
Commit: 696590c07de868637e224502484d9847a691db20
https://github.com/llvm/llvm-project/commit/696590c07de868637e224502484d9847a691db20
Author: Benjamin Barenblat <bbaren at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/WORKSPACE
Log Message:
-----------
[bazel][libc] Update MPFR to v4.2.2 (#156691)
Use MPFR v4.2.2 rather than MPFR v4.1.1 for Bazel/Clang builds to avoid
conflicts with glibc’s `__float128` fallback typedef. See
https://gitlab.inria.fr/mpfr/mpfr/-/commit/c37c9d599b9aced92e182507bf223440bbc9a9f1
for further details.
Fixes https://github.com/llvm/llvm-project/issues/147879
Commit: 2a486148d754829a3ed16e1c4265f24d19cd3783
https://github.com/llvm/llvm-project/commit/2a486148d754829a3ed16e1c4265f24d19cd3783
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Port #153661: LifetimeSafetyTest dep (#156697)
Commit: fee17b3a96c29ddef59103bd7c02568f748e37ab
https://github.com/llvm/llvm-project/commit/fee17b3a96c29ddef59103bd7c02568f748e37ab
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/user-sgpr-count-diag.s
M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
M llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
M llvm/test/MachineVerifier/AMDGPU/verify-av-mov-imm-pseudo.mir
M llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
M llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/basic.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
M llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
M llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
M llvm/test/Verifier/AMDGPU/intrinsic-prefetch.ll
M llvm/test/Verifier/AMDGPU/mfma-scale.ll
M llvm/test/Verifier/AMDGPU/wmma-f8f6f4.ll
Log Message:
-----------
[AMDGPU] Remove most uses of /dev/null in tests (#156630)
Using options like -filetype=null instead should allow tools to save
some work by not generating any output.
Commit: 7d6e72f11033685af069e40697cd9fc0bad0a682
https://github.com/llvm/llvm-project/commit/7d6e72f11033685af069e40697cd9fc0bad0a682
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add-sub.ll
R llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add.ll
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir
Log Message:
-----------
[RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD (#155972)
RISCV does not provide a native atomic subtract instruction, so this
patch lowers `G_ATOMICRMW_SUB` by negating the RHS value and performing
an atomic add. The legalization rules in `RISCVLegalizerInfo` are
updated accordingly, with libcall fallbacks when `StdExtA` is not
available, and intrinsic legalization is extended to support
`riscv_masked_atomicrmw_sub`.
For example, lowering
`%1 = atomicrmw sub ptr %a, i32 1 seq_cst`
on riscv32a produces:
```
li a1, -1
amoadd.w.aqrl a0, a1, (a0)
```
On riscv64a, where the RHS type is narrower than XLEN, it currently
produces:
```
li a1, 1
neg a1, a1
amoadd.w.aqrl a0, a1, (a0)
```
There is still a constant-folding or InstConbiner gap. For instance,
lowering
```
%b = sub i32 %x, %y
%1 = atomicrmw sub ptr %a, i32 %b seq_cst
```
generates:
```
subw a1, a1, a2
neg a1, a1
amoadd.w.aqrl a0, a1, (a0)
```
This sequence could be optimized further to eliminate the redundant neg.
Addressing this may require improvements in the Combiner or Peephole
Optimizer in future work.
---------
Co-authored-by: Kane Wang <kanewang95 at foxmail.com>
Commit: d91a5c33df2e53c757c68b0a893d4654993fa3a5
https://github.com/llvm/llvm-project/commit/d91a5c33df2e53c757c68b0a893d4654993fa3a5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/implied-by-bounded-memory-access.ll
Log Message:
-----------
[ConstraintElim] Bail out on non-canonical GEPs (#156688)
In most cases, GEPs should be canonicalized by InstCombine. Bail out on
non-canonical forms for simplicity.
Fixes
https://github.com/llvm/llvm-project/pull/155253#issuecomment-3248457478.
Commit: bad2036c6ef13e4b44fdea527c3f6ea49033358d
https://github.com/llvm/llvm-project/commit/bad2036c6ef13e4b44fdea527c3f6ea49033358d
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/test/Conversion/PtrToLLVM/ptr-to-llvm.mlir
M mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Target/LLVMIR/ptr.mlir
Log Message:
-----------
[mlir][ptr] Extend `ptr_add` operation to support shaped operands (#156374)
This patch extends `ptr_add` to work with shaped types with value
semantics, both for the offsets and base.
Concretely this patch makes the following changes:
- Supports scalar-to-scalar, scalar-to-shaped, shaped-to-scalar, and
shaped-to-shaped combinations
- Adds InferTypeOpInterface for automatic result type deduction
- Adds tests for LLVM IR translation with vector operands
Example:
```mlir
func.func @ptr_add_tensor_2d(%ptrs: tensor<4x8x!ptr.ptr<#ptr.generic_space>>, %offsets: tensor<4x8xindex>) -> tensor<4x8x!ptr.ptr<#ptr.generic_space>> {
%res = ptr.ptr_add %ptrs, %offsets : tensor<4x8x!ptr.ptr<#ptr.generic_space>>, tensor<4x8xindex>
%res1 = ptr.ptr_add nuw %ptrs, %offsets : tensor<4x8x!ptr.ptr<#ptr.generic_space>>, tensor<4x8xindex>
return %res : tensor<4x8x!ptr.ptr<#ptr.generic_space>>
}
```
The motivation behind this patch is to lay the groundwork for enabling
`triton` styled loads and stores, and their variants.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: 527c8ff11e4b05e3502a46a5ad52bb7f0da5ed2a
https://github.com/llvm/llvm-project/commit/527c8ff11e4b05e3502a46a5ad52bb7f0da5ed2a
Author: cmtice <cmtice at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/utils/lit/lit/ShUtil.py
M llvm/utils/lit/tests/unit/ShUtil.py
Log Message:
-----------
[lit] Update internal shell lexer to handle LLDB persistent vars. (#156125)
LLDB allows creation of 'persistent' variables, with names that start
with '$'. The lit internal shell was escaping the '$', making it '\\$',
in some CHECK lines, which causes an LLDB test,
TestExprWithSideEffectOnConvenienceVar, to fail when using the lit
internal shell.
Further explanation of the failing LLDB test: LLDB convenience variables
start with '$'. The test passes several quoted commands that use and
update convenience variables to lldb as arguments to be run in batch
mode. The tool that packages up the complete string and passes it to the
lit internal shell lexer for lexing inserts a backslash in front of the
'$' before passing the string in for lexing. The lexer was passing this
change along, causing the tests to fail.
This PR fixes the issue by having the lexer remove the newly added
escape on the '$'.
Commit: e75f054d18c426b421d7d4cc58342fcb60047cfc
https://github.com/llvm/llvm-project/commit/e75f054d18c426b421d7d4cc58342fcb60047cfc
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/MachO/Driver.cpp
A lld/test/MachO/read-workers.s
Log Message:
-----------
[lld][MachO] Silence warnings about --read-workers parsing (#156608)
The parsing of the --read-workers argument v is implemented like this:
unsigned threads = 0
if (!llvm::to_integer(v, threads, 0) || threads < 0) {
...
As reported by a compiler warning, the value of the "threads < 0"
expession is never going to be true. It could only evaluate to true if v
represents a negative number, but in this case llvm::to_integer returns
false since threads is unsigned and hence the second operand of the ||
operator will not be evaluated.
This patch removes the useless || operand to silence compiler warnings.
Since I had to first find out if --read-workers=0 is valid or not (it is),
I also added a test to document the valid values for the option and I adjusted
the error message on invalid values to clearly state that 0 is valid.
Commit: df9965cb5a116c4f8c07bff8349d9bf342d9c96f
https://github.com/llvm/llvm-project/commit/df9965cb5a116c4f8c07bff8349d9bf342d9c96f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/test/COFF/color-diagnostics.test
M lld/test/COFF/linkrepro-res.test
M lld/test/COFF/linkrepro.test
M lld/test/ELF/arm-exidx-range.s
M lld/test/ELF/color-diagnostics.test
M lld/test/ELF/file-access.s
M lld/test/ELF/linkerscript/invalid.test
M lld/test/ELF/lto/resolution-err.ll
M lld/test/MachO/color-diagnostics.test
M lld/test/MachO/framework.s
M lld/test/MachO/implicit-and-allowable-clients.test
M lld/test/MachO/link-search-at-loader-path-symlink.s
M lld/test/MachO/reexport-with-symlink.s
M lld/test/MachO/reexport-without-rpath.s
M lld/test/MachO/reproduce.s
M lld/test/MachO/tapi-rpath.s
M lld/test/wasm/reproduce.s
Log Message:
-----------
[lld] Remove shell requirements from tests
These tests all pass inside the lit internal shell. A couple were marked
as requiring a shell to exclude them on Windows. Update those tests to
explicitly carve out Windows rather than any configuration that does not
provide the shell feature.
Towards #102700.
Reviewers: petrhosek, cmtice, mysterymath, MaskRay, ilovepi
Reviewed By: cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/156510
Commit: 1b130e3fc011443ac3700bd4d76f61aa5e4cd467
https://github.com/llvm/llvm-project/commit/1b130e3fc011443ac3700bd4d76f61aa5e4cd467
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
A clang/test/CIR/CodeGen/builtins-elementwise.c
Log Message:
-----------
[CIR] Upstream FPToFPBuiltin ACosOp (#156356)
Upstream support for FPToFPBuiltin ACosOp
Commit: c9ca354d383dc4a2843c9f89d9317c8a21fd0bf8
https://github.com/llvm/llvm-project/commit/c9ca354d383dc4a2843c9f89d9317c8a21fd0bf8
Author: Amr Hesham <amr96 at programmer.net>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Upstream Atomic init for ComplexType (#156518)
This change adds support for Atomic init for ComplexType
Issue: https://github.com/llvm/llvm-project/issues/141365
Commit: 55ec6373f99c23f70ea27cd96280b929e81503ac
https://github.com/llvm/llvm-project/commit/55ec6373f99c23f70ea27cd96280b929e81503ac
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/test/ELF/lto/comdat-nodeduplicate.ll
M lld/test/MachO/stabs.s
Log Message:
-----------
[lld] Update tests redirecting multiple commands to FileCheck
This patch updates two LLD tests that were redirecting multiple commands
to the same FileCheck invocation to not use this strategy. This
construction is not supported by lit's internal shell and given its
rarirty, it does not make sense to add support. The workaround is to
dump the contents of multiple commands into a file and then run
FileCheck on that.
Towards #102700.
Reviewers: petrhosek, mysterymath, cmtice, ilovepi, carlocab, MaskRay
Reviewed By: carlocab, cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/156526
Commit: 5545a92079012b5e501e5d7a5cbe1105a5dec9a4
https://github.com/llvm/llvm-project/commit/5545a92079012b5e501e5d7a5cbe1105a5dec9a4
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir] Port #156374: ptr_add shaped operands support (#156706)
Commit: 3b3fc701d8f83d4ca30ee1c818fb7687336ac178
https://github.com/llvm/llvm-project/commit/3b3fc701d8f83d4ca30ee1c818fb7687336ac178
Author: dlav-sc <daniil.avdeev at syntacore.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/test/API/riscv/step/TestSoftwareStep.py
M lldb/test/API/riscv/step/branch.c
M lldb/test/API/riscv/step/incomplete_sequence_without_lr.c
M lldb/test/API/riscv/step/incomplete_sequence_without_sc.c
M lldb/test/API/riscv/step/main.c
Log Message:
-----------
[lldb][RISCV][test] make atomic region stepping test more robust (#156506)
Currently, the tests that check stepping through atomic sequences use a
hardcoded step distance, which is unreliable because this distance
depends on LLVM's codegeneration. The relocations that clang emits can
change the distance of the step.
Additionally, it was a poor idea to compute and check the step distance
because that is not what we should actually be verifying. In the tests
we already know where execution should stop after the step - for
example, at a branch instruction - therefore, it is better to check the
opcode of the instruction rather than the step distance. The step
distance itself is not important and can sometimes be misleading.
This patch rewrites the tests, so now they checks the opcode of the
instruction after the step instead of the step distance.
Commit: 688d12ca09b1b434b5e22f7e2a6bee1dcd79050f
https://github.com/llvm/llvm-project/commit/688d12ca09b1b434b5e22f7e2a6bee1dcd79050f
Author: Chaitanya Koparkar <ckoparkar at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Headers][X86] Allow FMA intrinsics to be used in constexpr (#156385)
Fixes #155265
Add constexpr support for the following:
_mm512_fmadd_pd _mm512_mask_fmadd_pd _mm512_mask3_fmadd_pd
_mm512_maskz_fmadd_pd _mm512_fmadd_ps _mm512_mask_fmadd_ps
_mm512_mask3_fmadd_ps _mm512_maskz_fmadd_ps _mm_mask_fmadd_pd
_mm_mask3_fmadd_pd _mm_maskz_fmadd_pd _mm_mask_fmadd_ps
_mm_mask3_fmadd_ps _mm_maskz_fmadd_ps _mm256_mask_fmadd_pd
_mm256_mask3_fmadd_pd _mm256_maskz_fmadd_pd _mm256_mask_fmadd_ps
_mm256_mask3_fmadd_ps _mm256_maskz_fmadd_ps
_mm512_fmsub_pd _mm512_mask_fmsub_pd _mm512_mask3_fmsub_pd
_mm512_maskz_fmsub_pd _mm512_fmsub_ps _mm512_mask_fmsub_ps
_mm512_mask3_fmsub_ps _mm512_maskz_fmsub_ps _mm_mask_fmsub_pd
_mm_mask3_fmsub_pd _mm_maskz_fmsub_pd _mm_mask_fmsub_ps
_mm_mask3_fmsub_ps _mm_maskz_fmsub_ps _mm256_mask_fmsub_pd
_mm256_mask3_fmsub_pd _mm256_maskz_fmsub_pd _mm256_mask_fmsub_ps
_mm256_mask3_fmsub_ps _mm256_maskz_fmsub_ps
_mm512_fnmadd_pd _mm512_mask_fnmadd_pd _mm512_mask3_fnmadd_pd
_mm512_maskz_fnmadd_pd _mm512_fnmsub_pd _mm512_mask_fnmsub_pd
_mm512_mask3_fnmsub_pd _mm512_maskz_fnmsub_pd _mm_mask_fnmadd_pd
_mm_mask3_fnmadd_pd _mm_maskz_fnmadd_pd _mm_mask_fnmadd_ps
_mm_mask3_fnmadd_ps _mm_maskz_fnmadd_ps _mm256_mask_fnmadd_pd
_mm256_mask3_fnmadd_pd _mm256_maskz_fnmadd_pd _mm256_mask_fnmadd_ps
_mm256_mask3_fnmadd_ps _mm256_maskz_fnmadd_ps
_mm512_fnmadd_ps _mm512_mask_fnmadd_ps _mm512_mask3_fnmadd_ps
_mm512_maskz_fnmadd_ps _mm512_fnmsub_ps _mm512_mask_fnmsub_ps
_mm512_mask3_fnmsub_ps _mm512_maskz_fnmsub_ps _mm_mask_fnmsub_pd
_mm_mask3_fnmsub_pd _mm_maskz_fnmsub_pd _mm_mask_fnmsub_ps
_mm_mask3_fnmsub_ps _mm_maskz_fnmsub_ps _mm256_mask_fnmsub_pd
_mm256_mask3_fnmsub_pd _mm256_maskz_fnmsub_pd _mm256_mask_fnmsub_ps
_mm256_mask3_fnmsub_ps _mm256_maskz_fnmsub_ps
Commit: 6e65e6a31356bdac8c81376f2b8b32ececd3c76a
https://github.com/llvm/llvm-project/commit/6e65e6a31356bdac8c81376f2b8b32ececd3c76a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/test/MachO/cgdata-generate-merge.s
M lld/test/MachO/cgdata-generate.s
Log Message:
-----------
[lld] Update cgdata-* tests to not use subshells
Subshells are not supported in the lit internal shell. We can remove
them by constructing sed commands directly inside of a separate file.
Towards #102700.
Reviewers: ilovepi, MaskRay, petrhosek, mysterymath, cmtice, kyulee-com
Reviewed By: MaskRay, cmtice, petrhosek
Pull Request: https://github.com/llvm/llvm-project/pull/156533
Commit: 9c7727c62af0b366358df9e030f5cde659422eb2
https://github.com/llvm/llvm-project/commit/9c7727c62af0b366358df9e030f5cde659422eb2
Author: Un1q32 <joey.t.reinhart at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libcxx/include/__cxx03/__config
Log Message:
-----------
[libc++][C++03] remove unused macro in __config (#156609)
The only place this macro was used was in `__memory/aligned_alloc.h`,
but the code that used this macro also checked for C++17 so it was
removed, now this macro is never used.
Commit: 303bea8e6350bb2ff0c29d4aaf9621569918d836
https://github.com/llvm/llvm-project/commit/303bea8e6350bb2ff0c29d4aaf9621569918d836
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/test/COFF/lto-cache-warnings.ll
M lld/test/ELF/lto/cache-warnings.ll
M lld/test/MachO/lto-cache-warnings.ll
M lld/test/wasm/lto/cache-warnings.ll
Log Message:
-----------
[lld] Make cache-warning* tests work with internal shell
These tests were using subexpressions to change the cache size. Change
them up to write out the necessary commands to a response file and then
load that on the lld command line.
Towards #102700.
Reviewers: ilovepi, cmtice, mysterymath, MaskRay, petrhosek
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/156537
Commit: c5a141bb8b5dfc4be06bb165d88e724e66bf5c4c
https://github.com/llvm/llvm-project/commit/c5a141bb8b5dfc4be06bb165d88e724e66bf5c4c
Author: Ian Li <ianayl.work at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
Log Message:
-----------
[mlir][spirv] Add pattern matching for arith.index_cast index to i1 for ArithToSPIRV (#156031)
Currently, `arith.index_cast` gets converted to `OpSConvert`:
https://github.com/llvm/llvm-project/blob/9bf5bf3baf3c7aec82cdd235c6a2fd57b4dd55ab/mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp#L1331
[OpSConvert requires its operands to be of integer
type](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpSConvert),
which poses an issue for `i1` since SPIRV distinguishes between booleans
and integers. As a result, the following example doesn't get converted,
leaving behind illegal ops:
```
%0 = arith.index_cast %arg0 : index to i1
```
This PR adds additional logic to convert `arith.index_casts` to SPIRV
dialect when casting from `index` to `i1`. Converting `index_cast`s from
`i1` to `index` is submitted as
https://github.com/llvm/llvm-project/pull/155729.
---------
Co-authored-by: Md Abdullah Shahneous Bari <98356296+mshahneo at users.noreply.github.com>
Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
Commit: 96b1dfb57fc822ea69bf75a8f0a69eb168776faa
https://github.com/llvm/llvm-project/commit/96b1dfb57fc822ea69bf75a8f0a69eb168776faa
Author: Krishna Pandey <kpandey81930 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/aarch64/entrypoints.txt
M libc/config/darwin/x86_64/entrypoints.txt
M libc/config/gpu/amdgpu/entrypoints.txt
M libc/config/gpu/nvptx/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/windows/entrypoints.txt
M libc/docs/headers/math/index.rst
M libc/src/math/CMakeLists.txt
A libc/src/math/fmodbf16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/fmodbf16.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/fmodbf16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/FModTest.h
A libc/test/src/math/smoke/fmodbf16_test.cpp
Log Message:
-----------
[libc][math][c++23] Add fmodbf16 math function (#155575)
This PR adds fmodbf16 basic math function for BFloat16 type along with
the tests.
---------
Signed-off-by: Krishna Pandey <kpandey81930 at gmail.com>
Commit: f5006e043143717e2e8ade9a009e1209b4a3563b
https://github.com/llvm/llvm-project/commit/f5006e043143717e2e8ade9a009e1209b4a3563b
Author: Zentrik <llvm.zentrik at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/tools/mlir-irdl-to-cpp/CMakeLists.txt
Log Message:
-----------
[MLIR][IRDL][CMake] Switch to using `setup_host_tool` to fix cross compilation (#156606)
Using `build_native_tool` directly doesn't seem to be standard, instead
other tools seem to call `setup_host_tool` (e.g. milr-linalg-ods-gen and
`add_tablegen` seems to have a copy of `setup_host_tool` internally).
When cross compiling llvm in two stages, the first building all native
tools and then the second using those built tools to cross compile, this
prevents the second stage from trying to rebuild mlir-irdl-to-cpp, which
fails.
Commit: 714f6b03bc89bff766ae628092cd059fd8aa0aa1
https://github.com/llvm/llvm-project/commit/714f6b03bc89bff766ae628092cd059fd8aa0aa1
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/test/MachO/objc-category-merging-minimal.s
M lld/test/lit.cfg.py
Log Message:
-----------
[lld] Make lld tests use lit internal shell by default
This patch updates the lld lit test config to use the internal shell by
default. This has some performance advantages (~10-15%) and also
produces nicer failure output. This should have no impact on test
coverage now that all tests previously requiring a shell have been
ported over to work with the internal shell.
Fixes #102700.
Reviewers: MaskRay, petrhosek, cmtice, mysterymath, ilovepi
Reviewed By: MaskRay, petrhosek, cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/156538
Commit: 4829dedfa9bb3d1e15aaa88cf1ff329c7b0e59de
https://github.com/llvm/llvm-project/commit/4829dedfa9bb3d1e15aaa88cf1ff329c7b0e59de
Author: Amara Emerson <amara at apple.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
Log Message:
-----------
[GlobalISel] Add multi-way splitting support for wide scalar shifts. (#155353)
This patch implements direct N-way splitting for wide scalar shifts
instead
of recursive binary splitting. For example, an i512 G_SHL can now be
split
directly into 8 i64 operations rather than going through i256 -> i128 ->
i64.
The main motivation behind this is to alleviate (although not entirely
fix)
pathological compile time issues with huge types, like i4224. The
problem
we see is that the recursive splitting strategy combined with our messy
artifact combiner ends up with terribly long compiles as tons of
intermediate
artifacts are generated, and then attempted to be combined ad-nauseum.
Going directly from the large shifts to the destination types
short-circuits
a lot of these issues, but it's still an abuse of the backend and
front-ends
should never be doing this sort of thing.
Commit: c93e2de67f3d4fb558edf9b69fd824b1fb9d29c2
https://github.com/llvm/llvm-project/commit/c93e2de67f3d4fb558edf9b69fd824b1fb9d29c2
Author: Anatoly Myachev <anatoliimyachev at mail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/test/python/ir/auto_location.py
Log Message:
-----------
Fix `python/ir/auto_location.py` test on Windows (#156711)
Initially found in:
https://github.com/llvm/llvm-project/pull/151246#discussion_r2318830512
To fix:
```txt
******************** TEST 'MLIR :: python/ir/auto_location.py' FAILED ********************
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
"C:/hostedtoolcache/windows/Python/3.11.9/x64/python3.exe" D:\a\triton\triton\llvm-project\mlir\test\python\ir\auto_location.py | d:\a\triton\triton\llvm-project\build\bin\filecheck.exe D:\a\triton\triton\llvm-project\mlir\test\python\ir\auto_location.py
# executed command: C:/hostedtoolcache/windows/Python/3.11.9/x64/python3.exe 'D:\a\triton\triton\llvm-project\mlir\test\python\ir\auto_location.py'
# executed command: 'd:\a\triton\triton\llvm-project\build\bin\filecheck.exe' 'D:\a\triton\triton\llvm-project\mlir\test\python\ir\auto_location.py'
# .---command stderr------------
# | D:\a\triton\triton\llvm-project\mlir\test\python\ir\auto_location.py:37:11: error: CHECK: expected string not found in input
# | # CHECK: loc(callsite("testInferLocations"("{{.*}}[[SEP:[/\\]]]test[[SEP]]python[[SEP]]ir[[SEP]]auto_location.py":31:13 to :43) at callsite("run"("{{.*}}[[SEP]]test[[SEP]]python[[SEP]]ir[[SEP]]auto_location.py":13:4 to :7) at "<module>"("{{.*}}[[SEP]]test[[SEP]]python[[SEP]]ir[[SEP]]auto_location.py":26:1 to :4))))
# | ^
# | <stdin>:2:25: note: scanning from here
# | TEST: testInferLocations
# | ^
# |
# | Input file: <stdin>
# | Check file: D:\a\triton\triton\llvm-project\mlir\test\python\ir\auto_location.py
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<<<<<
# | 1:
# | 2: TEST: testInferLocations
# | check:37 X error: no match found
# | 3: loc(callsite("testInferLocations"("D:\\a\\triton\\triton\\llvm-project\\mlir\\test\\python\\ir\\auto_location.py":31:13 to :43) at callsite("run"("D:\\a\\triton\\triton\\llvm-project\\mlir\\test\\python\\ir\\auto_location.py":13:4 to :7) at "<module>"("D:\\a\\triton\\triton\\llvm-project\\mlir\\test\\python\\ir\\auto_location.py":26:1 to :4))))
# | check:37
```
Commit: b176ba78c8ded98cca955d4d32234fac8ada506c
https://github.com/llvm/llvm-project/commit/b176ba78c8ded98cca955d4d32234fac8ada506c
Author: Bhasawut Singhaphan <bhasawut at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/smmintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/X86/sse41-builtins.c
Log Message:
-----------
[Headers][X86] Allow MMX/SSE integer min/max intrinsics to be used in constexpr (#156678)
Update the MMX/SSE integer min/max intrinsics to be constexpr compatible.
This is a part of #153153.
Commit: 4d72bb381bf2aff8aa84c0b70d8384b6fdf98d1d
https://github.com/llvm/llvm-project/commit/4d72bb381bf2aff8aa84c0b70d8384b6fdf98d1d
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
Log Message:
-----------
[PowerPC][NFC] Refactor PPCInstrFutureMMA.td to combine sections (#151194)
Combine same predicate sections into one and move some mma instructions
into the proper section.
Commit: adc0a2caff44e3884ce3189932fa0e9c8a28620d
https://github.com/llvm/llvm-project/commit/adc0a2caff44e3884ce3189932fa0e9c8a28620d
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[mlir][acc] Introduce acc data bounds accessors (#156545)
Add acc.get_lowerbound, acc.get_upperbound, acc.get_stride, and
acc.get_extent operations to extract information from acc bounds.
This simplifies the arguments needed for recipes when handling slices
and makes bound information consistent with data clauses. Update recipe
documentation to clarify argument ordering and add examples
demonstrating slice handling with bounds arguments.
Commit: 722339dc0927545834afffd8aca9a75efd450ca9
https://github.com/llvm/llvm-project/commit/722339dc0927545834afffd8aca9a75efd450ca9
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/bindings/interface/SBStructuredDataExtensions.i
M lldb/test/API/python_api/sbstructureddata/TestStructuredDataAPI.py
Log Message:
-----------
[lldb] Revert custom __str__ in SBStructuredDataExtensions.i (#156721)
`__str__` was implemented in #155061, however its behavior was limited
to only a some kinds of `SBStructuredData`. That was a breaking change,
and this change removes that implementation of `__str__`, relying on the
existing behavior which calls `GetDescription`.
Commit: 878fa7b2686a8776d1f36a5bb516c95a07838825
https://github.com/llvm/llvm-project/commit/878fa7b2686a8776d1f36a5bb516c95a07838825
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
Log Message:
-----------
[OpenACC] Change lowering signature for 'destroy' (#156716)
Patch #156545 is introducing a different syntax for the 'destroy'
section of a recipe, which takes the 'original' value as the first
argument, and the one-to-be-destroyed as the 2nd. This patch corrects
the lowering to match that signature.
Commit: ded5f433dedf4a3419548929ac3dfa826e11d2e1
https://github.com/llvm/llvm-project/commit/ded5f433dedf4a3419548929ac3dfa826e11d2e1
Author: enh-google <enh at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libc/src/string/string_utils.h
M libc/test/src/string/strcspn_test.cpp
M libc/test/src/string/strpbrk_test.cpp
M libc/test/src/string/strsep_test.cpp
M libc/test/src/string/strspn_test.cpp
M libc/test/src/string/strtok_r_test.cpp
M libc/test/src/string/strtok_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
Log Message:
-----------
[libc] fixed signed char issues in strsep()/strtok()/strtok_r(). (#156705)
Also add the missing tests for all the related functions (even the ones
that were already right), and add the missing bazel build rules.
Commit: 6aa9d928a86019ab8997fa9fb7c5533a67ed1a8d
https://github.com/llvm/llvm-project/commit/6aa9d928a86019ab8997fa9fb7c5533a67ed1a8d
Author: Ian Li <ian.li at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
Log Message:
-----------
[mlir][spirv] Add pattern matching for arith.index_cast i1 to index for ArithToSPIRV (#155729)
Currently, `arith.index_cast` gets converted to `OpSConvert`:
https://github.com/llvm/llvm-project/blob/9bf5bf3baf3c7aec82cdd235c6a2fd57b4dd55ab/mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp#L1331
[OpSConvert requires its operands to be of integer
type](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpSConvert),
which poses an issue for `i1` since SPIRV distinguishes between booleans
and integers. As a result, the following example doesn't get converted,
leaving behind illegal ops:
```
%0 = arith.index_cast %arg0 : i1 to index
```
This PR adds additional logic to convert `arith.index_casts` to SPIRV
dialect when casting from `i1` to `index`. Converting `index_cast`s from
`index` to `i1` is a part of
https://github.com/llvm/llvm-project/pull/156031.
Commit: 2b9328c788f60d70f8cf021c56fc6dfa080e1c32
https://github.com/llvm/llvm-project/commit/2b9328c788f60d70f8cf021c56fc6dfa080e1c32
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lld/test/MachO/objc-category-merging-minimal.s
M lld/test/lit.cfg.py
Log Message:
-----------
Revert "[lld] Make lld tests use lit internal shell by default"
This reverts commit 714f6b03bc89bff766ae628092cd059fd8aa0aa1.
This caused some build failures.
https://lab.llvm.org/buildbot/#/builders/23/builds/13543
Reverting for now until I have a chance to investigate.
Commit: 83c1cf6251c95f8ffbe55238e43dc2d9fee9c8ea
https://github.com/llvm/llvm-project/commit/83c1cf6251c95f8ffbe55238e43dc2d9fee9c8ea
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/lib/Semantics/compute-offsets.cpp
M flang/lib/Semantics/symbol.cpp
M flang/test/Semantics/cuf-device-procedures01.cuf
A flang/test/Semantics/offsets05.f90
Log Message:
-----------
[flang][OpenMP] Fix offsets for EQUIVALENCE in firstprivate(/block/) (#156492)
When a common block appears in firstprivate, its contents become host
associations, which the symbol offset computation code for equivalences
wasn't expecting. Add a GetUltimate() call, and extend symbol dumping
for HostAssocDetails.
Commit: 4e36508e392ebfe7979b36ff65ecc4ddd49ee651
https://github.com/llvm/llvm-project/commit/4e36508e392ebfe7979b36ff65ecc4ddd49ee651
Author: Derek Schuff <dschuff at chromium.org>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
Add Derek Schuff and Heejin Ahn as WebAssembly backend maintainers (#156553)
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: be616b4c5b68d7832e46f70bde439b5be2f9e1cd
https://github.com/llvm/llvm-project/commit/be616b4c5b68d7832e46f70bde439b5be2f9e1cd
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/global03.f90
Log Message:
-----------
[flang] Fix false errors in function result derived type checking (#156509)
When checking function result types that are implicitly declared at
their pointer of use against the actual definitions of those functions
(when available), be sure to use the type equivalence checker that
allows for USE association and sequence type equivalence.
Commit: 8c716bec1dbd00267e2260d558df4d1ab0e5b506
https://github.com/llvm/llvm-project/commit/8c716bec1dbd00267e2260d558df4d1ab0e5b506
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/statement-exprs.c
M clang/test/CIR/CodeGen/variable-decomposition.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
A clang/test/CIR/IR/copy.cir
A clang/test/CIR/IR/invalid-copy.cir
Log Message:
-----------
[CIR] Emit copy for aggregate initialization (#155697)
This adds the implementation of aggEmitFinalDestCopy for the case where
the destination value is not ignored. This requires adding the cir.copy
operation and associated interface code.
Commit: 7753f61f6161700c0c6f12b6ef785b96f3f7675c
https://github.com/llvm/llvm-project/commit/7753f61f6161700c0c6f12b6ef785b96f3f7675c
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-async-load-store-lds.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
Log Message:
-----------
[AMDGPU] Support cluster_load_async_to_lds instructions on gfx1250 (#156595)
Commit: 899ee375e99c04ef2c4a67dc70b266c929ad43f4
https://github.com/llvm/llvm-project/commit/899ee375e99c04ef2c4a67dc70b266c929ad43f4
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
Log Message:
-----------
[llvm-exegesis] Exclude loads/stores from aliasing instruction set (#156300)
In the serial snippet generator and function that computes the aliasing
instructions, we don't want to include load/store instructions
to create a chain as that could make the results more unreliable.
There is a hasMemoryOperands() check, but currently that looks like a X86
way for checking for loads/stores. For AArch64 and other architectures, we
should check mayLoad() and mayStore().
Commit: 0c6f98333fd23c09c8180f078691817dc8869461
https://github.com/llvm/llvm-project/commit/0c6f98333fd23c09c8180f078691817dc8869461
Author: Karthik Senthil <karthik.senthil at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
A llvm/test/CodeGen/X86/AMX/amx-sink-config-after-calls.mir
Log Message:
-----------
[AMX][PreTileConfig] Ensure that PLDTILECFGV instruction is sinked closer to tile use instruction. (#155673)
According AMX ABI, tile registers (including config) are volatile hence
requiring caller to save/restore config register. This is done in X86's
FastPreTileConfig pass. Currently the PLDTILECFGV instruction is emitted
immediately after the call which can be problematic if call returns a
value in say rax register and AMX tile is configured using the same
register. This PR addresses this issue by ensuring that PLDTILECFGV is
sinked closer to first instruction using a tile after the call.
Commit: 7c10e57f54210b0ed9b863301222c58d503dedbb
https://github.com/llvm/llvm-project/commit/7c10e57f54210b0ed9b863301222c58d503dedbb
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
R llvm/test/Analysis/ScalarEvolution/zext-signed-addrec.ll
A llvm/test/Transforms/LoopStrengthReduce/X86/zext-signed-addrec.ll
Log Message:
-----------
[LSR] Move test from Analysis/ScalarEvolution to Transforms, regen.
Move transform test to llvm/test/Transforms/LoopStrengthReduce/X86,
clean up the names a bit and regenerate check lines.
Commit: 5777f71bcef03fe833de257a85f6a908941280f2
https://github.com/llvm/llvm-project/commit/5777f71bcef03fe833de257a85f6a908941280f2
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
Log Message:
-----------
[MLIR][XeGPU] Scattered ops sg-to-wi distribution (#154949)
This PR adds distribution patterns for scattered load and store ops,
chunk size included.
XeGPU moves toward offsets being part of the load/store ops, so the pass
only supports this case. Manipulating a vector of offsets indirectly
through create_tdesc is complex and soon to become obsolete anyway.
This PR assumes the SIMT-adapted scatter ops verification introduced in
https://github.com/llvm/llvm-project/pull/154653. The distribution
itself can be reviewed in the meantime.
Commit: a26cd2d504acff037cea8703a8926f4cf8e5b836
https://github.com/llvm/llvm-project/commit/a26cd2d504acff037cea8703a8926f4cf8e5b836
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
A flang/test/Transforms/dummy-procedure-common-block-name.f
Log Message:
-----------
[Flang] Fix symbol name clash when dummy procedure name is the same as common-block-name (#155508)
Dummy procedures in interface blocks are not external procedures that
need to be linked. Do not externalize those.
Fixes #122822
Commit: 6026ca301d0759031736c0b4a6642ea94f922287
https://github.com/llvm/llvm-project/commit/6026ca301d0759031736c0b4a6642ea94f922287
Author: Chao Chen <chao.chen at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
Log Message:
-----------
[mlir][XeGPU] add unroll patterns for load_matrix and store_matrix (#154637)
Commit: 6222b29f15ebec6683125b3d3920c5300bff8300
https://github.com/llvm/llvm-project/commit/6222b29f15ebec6683125b3d3920c5300bff8300
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/test/lib/Transforms/TestTransformsOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in TestTransformsOps.cpp (NFC)
Commit: 8f1c39fb50283bfabe4f099d51e55cab22aa772f
https://github.com/llvm/llvm-project/commit/8f1c39fb50283bfabe4f099d51e55cab22aa772f
Author: Farzon Lotfi <farzonlotfi at microsoft.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/test/CodeGenHLSL/builtins/isinf-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/isinf.hlsl
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/OpIsInf.ll
Log Message:
-----------
[SPIRV] Add OpInf support for isinf hlsl intrinsic (#156570)
fixes #148051
- update EmitHLSLBuiltinExpr in CGHLSLBuiltins.cpp to toggle intrinsics
by target
- Add a GENERATE_HLSL_INTRINSIC_FUNCTION for isinf in CGHLSLRuntime.h
- Update the SPIRVInstructionSelector.cpp to emit the OpSinf instruction
- Updates the isinf.hlsl test to check spirv intrinsic generation
- add OpIsinf.ll tests
Commit: 7b96cd7f594cadea9baaa37155a3b1b2b1e3e17f
https://github.com/llvm/llvm-project/commit/7b96cd7f594cadea9baaa37155a3b1b2b1e3e17f
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
Log Message:
-----------
[AMDGPU] Use "v_bfi_b32 x, y, -1" to implement (y | ~x) (#156653)
Commit: a862225813c251c28b085603b7d32d4b111dbc57
https://github.com/llvm/llvm-project/commit/a862225813c251c28b085603b7d32d4b111dbc57
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
A lldb/test/Shell/SymbolFile/DWARF/objcxx-forward-decls.test
Log Message:
-----------
[lldb][DWARFASTParserClang] Don't complete conflicting Objective-C++ types (#156681)
This upstreams https://github.com/swiftlang/llvm-project/pull/10313.
If we detect a situation where a forward declaration is C++ and the
definition DIE is Objective-C, then just don't try to complete the type
(it would crash otherwise). In the long term we might want to add
support for completing such types.
We've seen real world crashes when debugging WebKit and wxWidgets
because of this. Both projects forward declare ObjC++ decls in the way
shown in the test.
rdar://145959981
Commit: 88c38258891fe7572b1d57b42dea059d422ced6f
https://github.com/llvm/llvm-project/commit/88c38258891fe7572b1d57b42dea059d422ced6f
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/vtt.cpp
M clang/test/CIR/Lowering/vtt-addrpoint.cir
Log Message:
-----------
[CIR] Add support for constructors with VTT parameters (#156521)
This adds the support for implicit VTT arguments in constructors.
Commit: d7a08c5a806fa3f59ef61d6a89ca9fff07555906
https://github.com/llvm/llvm-project/commit/d7a08c5a806fa3f59ef61d6a89ca9fff07555906
Author: Krishna Pandey <kpandey81930 at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M libc/src/__support/FPUtil/bfloat16.h
Log Message:
-----------
[libc] Fix buildbot failures (#156733)
Signed-off-by: Krishna Pandey <kpandey81930 at gmail.com>
Commit: 9d9a714f794b3e7ceb1d8d84a7137eb47eba06f0
https://github.com/llvm/llvm-project/commit/9d9a714f794b3e7ceb1d8d84a7137eb47eba06f0
Author: Dave Lee <davelee.com at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/bindings/interface/SBStructuredDataExtensions.i
M lldb/test/API/python_api/sbstructureddata/TestStructuredDataAPI.py
Log Message:
-----------
Revert "[lldb] Add Pythonic API to SBStructuredData extension (#155061)" (#156728)
Reverts #155061 (and #156721) which caused Crashlog shell tests to break.
Commit: 2729284db1b8c79f14190070c2487a3d9b0687b6
https://github.com/llvm/llvm-project/commit/2729284db1b8c79f14190070c2487a3d9b0687b6
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
Log Message:
-----------
[LV] Add early-exit tests with deref assumptions and scaled sizes.
Add tests where the size of dereferenceable assumption is multiplied by
a constant.
Commit: b15c6c222e2e79a5c60d9182be35ceccdd6b23c3
https://github.com/llvm/llvm-project/commit/b15c6c222e2e79a5c60d9182be35ceccdd6b23c3
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
R llvm/test/tools/llvm-exegesis/AArch64/no-aliasing-ld-str.s
M llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
Log Message:
-----------
Revert "[llvm-exegesis] Exclude loads/stores from aliasing instruction set" (#156735)
Reverts llvm/llvm-project#156300
Need to look at the X86 test failures.
Commit: 3052009afa549e619e8530532dc3b633d26b844d
https://github.com/llvm/llvm-project/commit/3052009afa549e619e8530532dc3b633d26b844d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-simplify-boolean-expr in Specialize.cpp (NFC) (#156738)
Commit: fee69dde12643c616209b0ec667280024a130a89
https://github.com/llvm/llvm-project/commit/fee69dde12643c616209b0ec667280024a130a89
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-simplify-boolean-expr in Specialize.cpp (NFC) (#156739)
Commit: 7949c2a9312f6311bd4a9344e1c9780307910fd2
https://github.com/llvm/llvm-project/commit/7949c2a9312f6311bd4a9344e1c9780307910fd2
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/utils/git/pre-push.py
Log Message:
-----------
Remove Phabricator-specific handling in pre-push.py, also don't print commits beyond 10
If you push a new branch, it would tend to explode printing all the commits.
Commit: 30e5d87e5ecad25603349412556aa4284c2ad8bb
https://github.com/llvm/llvm-project/commit/30e5d87e5ecad25603349412556aa4284c2ad8bb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-simplify-boolean-expr in Specialize.cpp (NFC) (#156743)
Commit: 15e9306f6d97c743b6d3fc80cda2fe37b09f4961
https://github.com/llvm/llvm-project/commit/15e9306f6d97c743b6d3fc80cda2fe37b09f4961
Author: Erich Keane <ekeane at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/test/SemaOpenACC/combined-construct-copy-clause.cpp
M clang/test/SemaOpenACC/combined-construct-copyin-clause.cpp
M clang/test/SemaOpenACC/combined-construct-copyout-clause.cpp
M clang/test/SemaOpenACC/combined-construct-create-clause.cpp
M clang/test/SemaOpenACC/combined-construct-firstprivate-clause.cpp
M clang/test/SemaOpenACC/combined-construct-no_create-clause.cpp
M clang/test/SemaOpenACC/combined-construct-present-clause.cpp
M clang/test/SemaOpenACC/compute-construct-copy-clause.cpp
M clang/test/SemaOpenACC/compute-construct-copyin-clause.cpp
M clang/test/SemaOpenACC/compute-construct-copyout-clause.cpp
M clang/test/SemaOpenACC/compute-construct-create-clause.cpp
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.cpp
M clang/test/SemaOpenACC/compute-construct-no_create-clause.cpp
M clang/test/SemaOpenACC/compute-construct-present-clause.cpp
M clang/test/SemaOpenACC/compute-construct-private-clause.cpp
Log Message:
-----------
[OpenACC] Fix crash because of miscalculated dependence. (#156745)
We were causing ANY dependence to cause the return type of the array
section to be dependent, when in reality it should only be so if one of
its Bounds/Base are dependent. This patch fixes that.
Commit: 13e60f36b9b20b5aba711570cebc19eebff0b00f
https://github.com/llvm/llvm-project/commit/13e60f36b9b20b5aba711570cebc19eebff0b00f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-container-size-empty in XeGPUOps.cpp (NFC) (#156752)
Commit: ce5a1158b8a2bca214ad37cd206f6c8eb659ea3c
https://github.com/llvm/llvm-project/commit/ce5a1158b8a2bca214ad37cd206f6c8eb659ea3c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-trunc-induction-steps.ll
Log Message:
-----------
[LV] Regenerate checks for missing branch weights.
Commit: 37e574c0042cafc5a6879e248d1bd49ddb61faab
https://github.com/llvm/llvm-project/commit/37e574c0042cafc5a6879e248d1bd49ddb61faab
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Shard/Interfaces/ShardingInterface.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for performance-unnecessary-copy-initialization in ShardingInterface.cpp (NFC)
Commit: 833f55f3daa5832e771aede0a86130803601cf97
https://github.com/llvm/llvm-project/commit/833f55f3daa5832e771aede0a86130803601cf97
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-container-size-empty in LLVMDialect.cpp (NFC)
Commit: f1e91bff426ffe0d12e91aac4cea9a1a2952816c
https://github.com/llvm/llvm-project/commit/f1e91bff426ffe0d12e91aac4cea9a1a2952816c
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
Log Message:
-----------
[LV] Regenerate more checks for missing branch weights.
Commit: 5cf9fd012e3d44c01b0f385a6893cc853985f12b
https://github.com/llvm/llvm-project/commit/5cf9fd012e3d44c01b0f385a6893cc853985f12b
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for modernize-use-default-member-init in SparseReinterpretMap.cpp (NFC)
Commit: e20ce964f7844e8d3227027ba943995ccc05ced2
https://github.com/llvm/llvm-project/commit/e20ce964f7844e8d3227027ba943995ccc05ced2
Author: cmtice <cmtice at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/utils/lit/lit/ShUtil.py
M llvm/utils/lit/tests/unit/ShUtil.py
Log Message:
-----------
lit] Update internal shell lexer to remove escape on '$' only for double-quoted strings. (#156742)
PR 156125 removed the escape (backslash) in front of '$' for all quoted
strings. It has since been pointed out this should only happen for
double-quoted strings. This PR fixes that.
Commit: 6a916f49b78de29a0ea00bcdb7d67ae8e7f4ddc9
https://github.com/llvm/llvm-project/commit/6a916f49b78de29a0ea00bcdb7d67ae8e7f4ddc9
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-qualified-auto in ConvertVectorToLLVM.cpp (NFC)
Commit: ab6be80f02cb76667e733c8f65ecf64ec8326c94
https://github.com/llvm/llvm-project/commit/ab6be80f02cb76667e733c8f65ecf64ec8326c94
Author: Bhasawut Singhaphan <bhasawut at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/Headers/avx512fintrin.h
M clang/test/CodeGen/X86/avx512f-builtins.c
Log Message:
-----------
[Headers][X86] Allow AVX512F mullox intrinsics to be used in constexpr (#156722)
This PR adds constexpr support for the following AVX512F mullox
intrinsics:
- _mm512_mullox_epi64
- _mm512_mask_mullox_epi64
Closes #156632
Fixes #155411
Commit: c1cc9d2c8a60b58410c50ff18c6135116665a03a
https://github.com/llvm/llvm-project/commit/c1cc9d2c8a60b58410c50ff18c6135116665a03a
Author: Thurston Dang <thurston at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
Log Message:
-----------
Revert "[MLIR][XeGPU] Scattered ops sg-to-wi distribution" (#156761)
Reverts llvm/llvm-project#154949 due to suspected buildbot breakage
(https://lab.llvm.org/buildbot/#/builders/55/builds/16630/steps/11/logs/stdio).
Previously commented on the original pull request:
https://github.com/llvm/llvm-project/pull/154949#issuecomment-3250709417
```
******************** TEST 'MLIR :: Dialect/XeGPU/subgroup-distribute.mlir' FAILED ********************
...
# | PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
# | Stack dump:
# | 0. Program arguments: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/mlir-opt -xegpu-subgroup-distribute -allow-unregistered-dialect -canonicalize -cse -split-input-file /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
# | #0 0x0000c0af4b066df0 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/lib/Support/Unix/Signals.inc:834:13
# | #1 0x0000c0af4b060e20 llvm::sys::RunSignalHandlers() /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/lib/Support/Signals.cpp:105:18
# | #2 0x0000c0af4b0691b4 SignalHandler(int, siginfo_t*, void*) /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/lib/Support/Unix/Signals.inc:426:38
# | #3 0x0000ee25a3dcb8f8 (linux-vdso.so.1+0x8f8)
# | #4 0x0000ee25a36c7608 (/lib/aarch64-linux-gnu/libc.so.6+0x87608)
# | #5 0x0000ee25a367cb3c raise (/lib/aarch64-linux-gnu/libc.so.6+0x3cb3c)
# | #6 0x0000ee25a3667e00 abort (/lib/aarch64-linux-gnu/libc.so.6+0x27e00)
# | #7 0x0000c0af4ae7e4b0 __sanitizer::Atexit(void (*)()) /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp:168:10
# | #8 0x0000c0af4ae7c354 __sanitizer::Die() /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_termination.cpp:52:5
# | #9 0x0000c0af4ae66a30 Unlock /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/../sanitizer_common/sanitizer_mutex.h:250:16
# | #10 0x0000c0af4ae66a30 ~GenericScopedLock /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/../sanitizer_common/sanitizer_mutex.h:386:51
# | #11 0x0000c0af4ae66a30 __hwasan::ScopedReport::~ScopedReport() /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/hwasan_report.cpp:54:5
# | #12 0x0000c0af4ae661b8 __hwasan::(anonymous namespace)::BaseReport::~BaseReport() /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/hwasan_report.cpp:477:7
# | #13 0x0000c0af4ae63f5c __hwasan::ReportTagMismatch(__sanitizer::StackTrace*, unsigned long, unsigned long, bool, bool, unsigned long*) /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/hwasan_report.cpp:1094:1
# | #14 0x0000c0af4ae4f8e0 Destroy /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/../sanitizer_common/sanitizer_common.h:532:31
# | #15 0x0000c0af4ae4f8e0 ~InternalMmapVector /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/../sanitizer_common/sanitizer_common.h:642:56
# | #16 0x0000c0af4ae4f8e0 __hwasan::HandleTagMismatch(__hwasan::AccessInfo, unsigned long, unsigned long, void*, unsigned long*) /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/hwasan.cpp:245:1
# | #17 0x0000c0af4ae51e8c __hwasan_tag_mismatch4 /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/hwasan/hwasan.cpp:764:1
# | #18 0x0000c0af4ae67b30 __interception::InterceptFunction(char const*, unsigned long*, unsigned long, unsigned long) /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/compiler-rt/lib/interception/interception_linux.cpp:60:0
# | #19 0x0000c0af5641cd24 getNumResults /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/include/mlir/IR/Operation.h:404:37
# | #20 0x0000c0af5641cd24 getOpResultImpl /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/include/mlir/IR/Operation.h:1010:5
# | #21 0x0000c0af5641cd24 getResult /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/include/mlir/IR/Operation.h:407:54
# | #22 0x0000c0af5641cd24 mlir::OpTrait::detail::MultiResultTraitBase<mlir::gpu::WarpExecuteOnLane0Op, mlir::OpTrait::VariadicResults>::getResult(unsigned int) /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/include/mlir/IR/OpDefinition.h:638:62
# | #23 0x0000c0af56426b60 getType /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/include/mlir/IR/Value.h:63:33
# | #24 0x0000c0af56426b60 getType /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/include/mlir/IR/Value.h:105:39
# | #25 0x0000c0af56426b60 (anonymous namespace)::LoadDistribution::matchAndRewrite(mlir::gpu::WarpExecuteOnLane0Op, mlir::PatternRewriter&) const /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp:991:55
...
```
Commit: 55e3b6d9213d9edccff10c77ee345ca766f32221
https://github.com/llvm/llvm-project/commit/55e3b6d9213d9edccff10c77ee345ca766f32221
Author: Ziyi Wang <144174031+zw3917 at users.noreply.github.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Target/Statistics.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Target/Statistics.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
A lldb/test/API/commands/statistics/basic/dwo_error_foo.cpp
A lldb/test/API/commands/statistics/basic/dwo_error_main.cpp
Log Message:
-----------
[lldb] Add count for errors of DWO files in statistics and combine DWO file count functions (#155023)
## Summary
A new `totalDwoErrorCount` counter is available in statistics when
calling `statistics dump` to track the number of DWO errors.
Additionally, this PR refactors the DWO file statistics by consolidating
the existing functionality for counting loaded and total DWO files
together with the number of DWO errors into a single function that
returns a new DWOStats struct.
1. A new struct, `DWOStats` is created to hold the number of loaded DWO
files, the total number of DWO files and the number of DWO errors.
2. Replaced the previous `GetDwoFileCounts` function for loaded and
total DWO file counts with a single `GetDwoStats()` function returning
the struct `DWOStats`. An override is implemented for `SymbolFileDWARF`
that computes the new DWO error count alongside existing counts in one
pass. If the status of a DWO CU is `Fail`, which means there is error
happened during the loading process, we increment the DWO error counter.
_Note: The newly created function `GetDwoStats` will only be called when
we try to get statistics. Other codepaths will not be affected._
3. In Statistics, we sum up the total number of DWO file loading errors.
This is done by getting `DWOStats` for each symbol file and adding up
the results for each module, then adding to the total count among all
modules.
4. In Statistics, we also updated call sites to use the new combined
function and struct for loaded and total DWO file counts. As it is
possible for one module to have several symbol files, the DWO file
counts in a module's stats are updated to be calculated by adding up the
counts from all symbol files.
## Expected Behavior
- When binaries are compiled with split-dwarf and separate DWO files,
`totalDwoLoadErrorCount` would be the number of dwo files with error
occurs during the loading process, 0 if no error occurs during a loading
process.
- When not using split-dwarf, we expect `totalDwoLoadErrorCount` to be 0
since there no DWO file loading errors would be caused.
- `totalLoadedDwoFileCount` and `totalDwoFileCount` should be correctly
calculated after refactoring and updating.
## Testing
### Manual Testing
We created some files to simulate the possible DWO errors manually and
observed the results generated by statistics dump.
For example, if we delete one of the DWO files generated after
compiling, we would get:
```
(lldb) statistics dump
{
...
"totalDwoLoadErrorCount": 1,
...
}
```
We also checked the time cost of `statistics dump` w/o the modification
to make sure no significant time cost increase imported.
### Unit test
Added two unit tests that build with new "dwo_error_foo.cpp" and
"dwo_error_main.cpp" files. For tests with flags -gsplit-dwarf, this
generates 2 DWO files.
In one of the tests, we delete both DWO files and check the result to
see if it reflects the number of DWO files with errors correctly. In
another test we update one of the files but loading the outdated .dwo
file of it, expecting it increments the error count by 1.
To run the test:
```
$ bin/lldb-dotest -p TestStats.py ~/local/llvm-project/lldb/test/API/commands/statistics/basic/ -G "dwo"
----------------------------------------------------------------------
Ran 27 tests in 2.680s
OK (skipped=21)
$ bin/lldb-dotest -p TestStats.py ~/local/llvm-project/lldb/test/API/commands/statistics/basic/
----------------------------------------------------------------------
Ran 27 tests in 370.131s
OK (skipped=3)
```
Commit: 82978dfc1356b7c18aabbc49372a044a6387a079
https://github.com/llvm/llvm-project/commit/82978dfc1356b7c18aabbc49372a044a6387a079
Author: Peter Collingbourne <peter at pcc.me.uk>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
A llvm/docs/DebuggingLLVM.rst
M llvm/docs/GettingStartedTutorials.rst
M llvm/docs/ProgrammersManual.rst
M llvm/lib/IR/AsmWriter.cpp
Log Message:
-----------
Add documentation on debugging LLVM.
Reviewers: fmayer, nikic
Reviewed By: fmayer
Pull Request: https://github.com/llvm/llvm-project/pull/156128
Commit: 74d52f9639ca7588c622c0790ca18fa5bff66837
https://github.com/llvm/llvm-project/commit/74d52f9639ca7588c622c0790ca18fa5bff66837
Author: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/ObjCopy/COFF/COFFObject.cpp
M llvm/lib/ObjCopy/COFF/COFFObject.h
M llvm/lib/ObjCopy/COFF/COFFWriter.cpp
M llvm/lib/ObjCopy/COFF/COFFWriter.h
A llvm/test/tools/llvm-objcopy/COFF/strip-invalid-symidx-section.test
A llvm/test/tools/llvm-objcopy/COFF/strip-update-symidx-section.test
Log Message:
-----------
[llvm-objcopy][COFF] Update .symidx values after stripping (#153322)
After deleting debug sections, symbol indices are shifted but sections
consisting of .symidx directives are completely ignored. Update symbol
indices as well.
Commit: 17bddd12245324311d10a681d606961914174c88
https://github.com/llvm/llvm-project/commit/17bddd12245324311d10a681d606961914174c88
Author: Zishan Mirza <zmirza at posteo.ch>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/headers/time.rst
A libc/hdr/localtime_overlay.h
M libc/include/time.yaml
M libc/src/time/CMakeLists.txt
M libc/src/time/baremetal/CMakeLists.txt
A libc/src/time/baremetal/localtime.cpp
A libc/src/time/baremetal/localtime_r.cpp
A libc/src/time/localtime.cpp
A libc/src/time/localtime.h
A libc/src/time/localtime_r.cpp
A libc/src/time/localtime_r.h
M libc/src/time/time_utils.h
M libc/test/src/time/CMakeLists.txt
A libc/test/src/time/localtime_r_test.cpp
A libc/test/src/time/localtime_test.cpp
Log Message:
-----------
[libc] implement template functions for localtime (#110363)
This is an implementation for template functions of localtime.
Update for this pull request: Implementation as been removed from this
pull request and will be added to a new one. This is because this pull
request is getting big. This pull request will only contain template
functions in order to implement localtime.
Update: The implementation is available in
https://github.com/zimirza/llvm-project/tree/localtime_implementation.
---------
Co-authored-by: Зишан Мирза <zmirza at tutanota.de>
Co-authored-by: Zishan Mirza <zmirza at posteo.de>
Commit: 1b12bc4bf9709bee43c415eb0417b1565b098d5a
https://github.com/llvm/llvm-project/commit/1b12bc4bf9709bee43c415eb0417b1565b098d5a
Author: Lei Huang <lei at ca.ibm.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
Log Message:
-----------
[NFC] Apply clang-format to PPCInstrFutureMMA.td (#156749)
Commit: 8edb5b4fb3eca44d16325a119257632e1ba003be
https://github.com/llvm/llvm-project/commit/8edb5b4fb3eca44d16325a119257632e1ba003be
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
Log Message:
-----------
[MLIR] Add LDBG() tracing to VectorTransferOpTransforms.cpp (NFC)
Had to debug an issue, more debugging helped here.
Commit: 6d21ef74bd3d8463ee9d20166b1764df4bcadf52
https://github.com/llvm/llvm-project/commit/6d21ef74bd3d8463ee9d20166b1764df4bcadf52
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-identifier-naming in TransformOps.cpp (NFC)
Commit: 9a7ad1687dc339985b3369903a0e2eaab3717c9d
https://github.com/llvm/llvm-project/commit/9a7ad1687dc339985b3369903a0e2eaab3717c9d
Author: Reid Kleckner <rnk at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/docs/DeveloperPolicy.rst
Log Message:
-----------
[docs] Refine some of the wording in the quality developer policy (#156555)
I split these edits out of PR #154441
Commit: 6c10ab8a3c7b212a73b4ad6673bad02cc34a28c4
https://github.com/llvm/llvm-project/commit/6c10ab8a3c7b212a73b4ad6673bad02cc34a28c4
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/include/lldb/API/SBFrame.h
M lldb/include/lldb/Core/FormatEntity.h
M lldb/include/lldb/Target/StackFrame.h
M lldb/source/API/SBFrame.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Plugins/Process/scripted/ScriptedThread.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/app_specific_backtrace_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_arm64_register.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_json.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_legacy.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/last_exception_backtrace_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test
M lldb/unittests/Core/FormatEntityTest.cpp
Log Message:
-----------
[lldb] Mark scripted frames as synthetic instead of artificial (#153117)
This patch changes the way frames created from scripted affordances like
Scripted Threads are displayed. Currently, they're marked artificial
which is used usually for compiler generated frames.
This patch changes that behaviour by introducing a new synthetic
StackFrame kind and moves 'artificial' to be a distinct StackFrame
attribut.
On top of making these frames less confusing, this allows us to know
when a frame was created from a scripted affordance.
rdar://155949703
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 881111065037d3b2de9af9d039bd78a16454aa33
https://github.com/llvm/llvm-project/commit/881111065037d3b2de9af9d039bd78a16454aa33
Author: Shilei Tian <i at tianshilei.me>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
[NFC] Remove trailing whitespaces from `clang/include/clang/Basic/AttrDocs.td`
Commit: fd8f549092b67cf06c1d571488a9fd321e427a2f
https://github.com/llvm/llvm-project/commit/fd8f549092b67cf06c1d571488a9fd321e427a2f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
Log Message:
-----------
[RISCV] Add exhausted_gprs_fprs test to calling-conv-half.ll. NFC (#156586)
The existing test case only exhausted the GPRs so the stack wasn't tested if FPRs were also available for arguments. This new test exhausts the GPRs and FPRs.
Commit: a34b110797e0793dd29c68ccad4927c10b7e6c70
https://github.com/llvm/llvm-project/commit/a34b110797e0793dd29c68ccad4927c10b7e6c70
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/bind-c01.f90
Log Message:
-----------
[flang] Check for BIND(C) name conflicts with alternate entries (#156563)
Added IsAlternateEntry() and modified IsExternalProcedureDefinition() to
also check for alternate entries.
(IsExternalProcedureDefinition() is called from
CheckHelper::CheckGlobalName(), which checks for duplicate global
symbols.)
Fixes #62778
Commit: 6aebbb0a85a6a675f58e4e727e2e161e03e6e13a
https://github.com/llvm/llvm-project/commit/6aebbb0a85a6a675f58e4e727e2e161e03e6e13a
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
Log Message:
-----------
[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)
This is a baseline support, it is not useable yet.
Commit: ac8e7be5fbd11f731ffc81bf3bbae50a5a4d83de
https://github.com/llvm/llvm-project/commit/ac8e7be5fbd11f731ffc81bf3bbae50a5a4d83de
Author: Jason Molenda <jmolenda at apple.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/tools/debugserver/source/RNBRemote.cpp
Log Message:
-----------
[lldb][debugserver] Max response size for qSpeedTest (#156099)
The qSpeedTest packet is used for experiments to determine the optimal
packet size for a given communication medium, e.g. to transfer 10MB of
memory, is it faster to send a hundred 100KB packets or ten 1MB packets.
It creates a packet of the requested size in a stack allocation, but is
not checking that its buffer is large enough for the requested size.
Change this allocation to be on heap, and impose a maximum size that can
be tested (4MB, for now).
rdar://158630250
Commit: cc0fb0d41dc67110132d540cebc87cdf12fe00c2
https://github.com/llvm/llvm-project/commit/cc0fb0d41dc67110132d540cebc87cdf12fe00c2
Author: cmtice <cmtice at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/test/Shell/Process/Optimization.test
M lldb/test/Shell/Process/UnsupportedLanguage.test
M lldb/test/Shell/SymbolFile/DWARF/dwo-missing-error.test
M lldb/test/Shell/lit.cfg.py
Log Message:
-----------
[LLDB] Make internal shell the default for running LLDB lit tests. (#156729)
This patch updates the lld lit test config to use the internal shell by
default. This has some performance advantages (~10-15%) and also
produces nicer failure output. It also updates the two LLDB tests to not
require shell (so that they run under the internal shell), after first
verifying that they run and pass using the internal shell; and it fixes
one test that was not passing under the internal shell.
Commit: d349daa135648e7e18da5be0c38ffbdbc7a208ca
https://github.com/llvm/llvm-project/commit/d349daa135648e7e18da5be0c38ffbdbc7a208ca
Author: bernhardu <bernhardu at mailbox.org>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M compiler-rt/lib/asan/asan_malloc_win.cpp
A compiler-rt/test/asan/TestCases/Windows/rtlallocateheap_realloc_in_place.cpp
Log Message:
-----------
[win/asan] Improve SharedReAlloc with HEAP_REALLOC_IN_PLACE_ONLY. (#132558)
Currently with HEAP_REALLOC_IN_PLACE_ONLY a new allocation
gets returned with the content copied from the original pointer,
which gets freed.
But applications may rely on HEAP_REALLOC_IN_PLACE_ONLY returning
the same pointer as they give as input to e.g. RtlReAllocateHeap.
If e.g. growing is not possible it fails without
modifying the input pointer.
Downside of this patch is, it won't detect accesses to the area
getting "free" by a shrinking reallocation.
Commit: 27114e4f302cb8724eec758077a430dd7fb300ef
https://github.com/llvm/llvm-project/commit/27114e4f302cb8724eec758077a430dd7fb300ef
Author: Michael Jones <michaelrj at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
Log Message:
-----------
[libc][NFC] disable localtime on aarch64/baremetal (#156776)
The fuchsia builder was broken by
https://github.com/llvm/llvm-project/pull/110363
This patch disables localtime for aarch64 baremetal, which is the
failing target.
Context: https://lab.llvm.org/buildbot/#/builders/11/builds/23186
Commit: 1959e12e7dd84f388547c3f85af7b919f2253377
https://github.com/llvm/llvm-project/commit/1959e12e7dd84f388547c3f85af7b919f2253377
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/a-v-ds-atomic-cmpxchg.ll
M llvm/test/MC/AMDGPU/gfx90a_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Add agpr variants of multi-data DS instructions (#156420)
The instruction definitions for loads and stores do not
accurately model the operand constraints of loads and stores
with AGPRs. They use AV register classes, plus a hack
a hack in getRegClass/getOpRegClass to avoid using AGPRs or
AV classes with the multiple operand cases, but it did not
consider the 3 operand case.
Model this correctly by using separate all-VGPR and all-AGPR
variants for the cases with multiple data operands.
This does regress the assembler errors on gfx908 for the
multi-operand cases. It now reports a generic operand
invalid error for GPU instead of the specific message
that agpr loads and stores aren't supported.
In the future AMDGPURewriteAGPRCopyMFMA should be taught
to replace the VGPR forms with the AGPR ones.
Most of the diff is fighting the DS pseudo structure. The
mnemonic was being used as the key to SIMCInstr, which is a
collision in the AGPR case. We also need to go out of our way
to make sure we are using the gfx9+ variants of the pseudos
without the m0 use. The DS multiclasses could use a lot of
cleanup.
Fixes #155777
Commit: c8d034a3b9db5394474098be1fc83d29e471380d
https://github.com/llvm/llvm-project/commit/c8d034a3b9db5394474098be1fc83d29e471380d
Author: David Peixotto <peix at meta.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/include/lldb/Symbol/SymbolFile.h
M lldb/include/lldb/Target/Statistics.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Target/Statistics.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
R lldb/test/API/commands/statistics/basic/dwo_error_foo.cpp
R lldb/test/API/commands/statistics/basic/dwo_error_main.cpp
Log Message:
-----------
Revert "[lldb] Add count for errors of DWO files in statistics and combine DWO file count functions" (#156777)
Reverts llvm/llvm-project#155023
The PR tests passed, but it failed in the CI. Reverting to give time to
investigate.
Commit: f3dcec0ee73fee6a33fcfb422e04297e4d466de6
https://github.com/llvm/llvm-project/commit/f3dcec0ee73fee6a33fcfb422e04297e4d466de6
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
A clang/test/SemaCXX/GH156458.cpp
Log Message:
-----------
[clang] fix error recovery for invalid nested name specifiers (#156772)
This fixes a regression which was introduced in #147835.
Since this regression was never released, there are no release notes.
Fixes #156458
Commit: aa02206fcd7ff5ff04a1c04fad9d1507cece1168
https://github.com/llvm/llvm-project/commit/aa02206fcd7ff5ff04a1c04fad9d1507cece1168
Author: Helena Kotas <hekotas at microsoft.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
Log Message:
-----------
[HLSL] Reorder arguments of __builtin_hlsl_resource_handlefromimplicitbinding (#155861)
Reorder the arguments of `__builtin_hlsl_resource_handlefromimplicitbinding` builtins to match the order of the `llvm.dx.resource.handlefromimplicitbinding` intrinsics, and also to match the arguments on the static create methods
for resource initialization ([described here](https://github.com/llvm/wg-hlsl/pull/336)).
Previously the arguments were in the same order as the resource class constructor for implicit binding. The `orderId` argument was intentionally at index `3` to make sure explicit & implicit binding constructors have different signature. Since we are going to replace the constructors that have binding info with static create methods, this is no longer necessary, and it is better for the argument order to match.
Related to #154221.
Commit: db3054a169e8452f301a637dbb2487b040fe2676
https://github.com/llvm/llvm-project/commit/db3054a169e8452f301a637dbb2487b040fe2676
Author: Piyush Jaiswal <piyushjais98 at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Options.td
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/DAP/DAPTest.cpp
M lldb/unittests/DAP/TestBase.cpp
Log Message:
-----------
[lldb-dap] Add `--no-lldbinit` as a CLI flag (#156131)
TLDR
----------
This PR adds `--no-lldbinit` as a new CLI flag to the `lldb-dap`
Motivation
-----------
Rcently Users reported being unable to control `.lldbinit` file sourcing
when debugging through VS Code.
https://github.com/llvm/llvm-project/issues/155802.
VS Code extensions cannot easily inject custom parameters into the DAP
initialize request. Adding `--no-lldbinit` as a CLI flag solves this
problem by allowing the decision to skip `.lldbinit` files to be made at
debugger startup, before any initialization requests are processed.
VS Code extensions can control this behavior by specifying the flag
through `debugAdapterArgs` or similar mechanisms in launch
configurations.
```
{
"type": <extension-type>,
"request": "launch",
"name": "Debug with --no-lldbinit",
"program": "${workspaceFolder}/your-program",
"debugAdapterArgs": ["--no-lldbinit"]
}
```
Summary
----------
This PR introduces a new command-line flag `--no-lldbinit` (with alias
`-x`) to `lldb-dap`. The flag prevents automatic parsing of `.lldbinit`
files during debugger initialization, giving users control over whether
their LLDB initialization scripts are loaded.
### Key Changes:
1. **CLI Option Definition** (`Options.td`): Added the `--no-lldbinit`
flag with `-x` alias
2. **Core Implementation** (`DAP.cpp`): Added support for storing and
using the no-lldbinit flag
3. **Initialization Handler** (`InitializeRequestHandler.cpp`): Modified
to respect the flag during debugger initialization
4. **Main Tool** (`lldb-dap.cpp`): Added argument parsing for the new
flag
5. **Test Infrastructure** (`dap_server.py & lldbdap_testcase.py`):
Enhanced test framework to support additional arguments
Test Plan
---------
### New Test Coverage (`TestDAP_launch.py`)
**Test Method:** `test_no_lldbinit_flag()`
**Test Strategy:**
1. **Setup**: Creates a temporary `.lldbinit` file with specific
settings that would normally be loaded
2. **Execution**: Launches lldb-dap with the `--no-lldbinit` flag
3. **Verification**: Confirms that the settings from `.lldbinit` are NOT
applied, proving the flag works correctly
**Test Environment:**
* Uses a temporary home directory with a custom `.lldbinit` file
* Sets specific LLDB settings (`stop-disassembly-display never`,
`target.x86-disassembly-flavor intel`)
* Launches debug adapter with `--no-lldbinit` flag via `additional_args`
parameter
**Validation Approach:**
* Executes `settings show stop-disassembly-display` command during
initialization
* Verifies the output does NOT contain "never" (which would indicate
`.lldbinit` was sourced)
* Confirms that initialization commands are still executed properly
### Testing Infrastructure Enhancements
**File Modifications:**
* `dap_server.py`: Enhanced to accept `additional_args` parameter for
passing extra CLI flags
* `lldbdap_testcase.py`: Updated `build_and_create_debug_adapter()`
method to support additional arguments and environment variables
### Unit Test Integration
**Unit Test Updates** (`DAPTest.cpp`):
* Added initialization of the new flag in test setup to ensure
consistent test behavior
**Test Run**
<img width="1759" height="1373" alt="Screenshot 2025-08-29 at 5 56
18 PM"
src="https://github.com/user-attachments/assets/769b319a-5009-4ade-aff8-c5f548b38123"
/>
---------
Co-authored-by: Piyush Jaiswal <piyushjais at meta.com>
Commit: dc170c7e315ee3f6a194ba81d044d7e8784b0221
https://github.com/llvm/llvm-project/commit/dc170c7e315ee3f6a194ba81d044d7e8784b0221
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir
Log Message:
-----------
AMDGPU: Special case align requirement for AV_MOV_B64_IMM_PSEUDO
This should not require aligned registers. Fixes expensive_checks
test failure. I don't see a better way until the new system
to specify the alignment per register is done.
Commit: c5078484ff8cf35c369832d903d363c3019ef3e1
https://github.com/llvm/llvm-project/commit/c5078484ff8cf35c369832d903d363c3019ef3e1
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
Log Message:
-----------
[LoongArch] Optimize extractelement containing variable index for lasx (#151475)
Ideas suggested by: @heiher @tangaac
Commit: efbf5f50f45c744922207d6ea692745d6c14599f
https://github.com/llvm/llvm-project/commit/efbf5f50f45c744922207d6ea692745d6c14599f
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M lld/test/COFF/reloc-discarded.s
M lld/test/ELF/msp430.s
M lld/test/ELF/weak-shared-gc.s
M lld/test/ELF/weak-undef-lib.s
Log Message:
-----------
[lld] Prefer printf over echo -e
Otherwise we break some MacOS bots when using the lit internal shell
because /bin/echo on MacOS does not support -e. Using the external shell
we end up using the echo builtin to /bin/bash, which does support this.
The echo builtin implementation in lit does support this, but that is
currently not enabled in pipelines. Might be worth looking into fixing
at some point.
Commit: 62ccea6a89d051272ec51555c3c1fac02e822c5a
https://github.com/llvm/llvm-project/commit/62ccea6a89d051272ec51555c3c1fac02e822c5a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M lld/test/lit.cfg.py
Log Message:
-----------
Reapply "[lld] Make lld tests use lit internal shell by default"
This reverts commit 2b9328c788f60d70f8cf021c56fc6dfa080e1c32.
This was broken originally because echo -e does not work on MacOS. This
has been fixed by the previous commit which updates the relevant tests
to use printf.
Commit: 0d292794650353352a33fcc856d4b52328d3da97
https://github.com/llvm/llvm-project/commit/0d292794650353352a33fcc856d4b52328d3da97
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/X86/shift-i128.ll
Log Message:
-----------
[DAGCombine] Propagate nuw when evaluating sub with narrower types (#156710)
Proof: https://alive2.llvm.org/ce/z/cdbzSL
Closes https://github.com/llvm/llvm-project/issues/156559.
Commit: c34cdd75fc5aa1da7fab697a247a164712f6696c
https://github.com/llvm/llvm-project/commit/c34cdd75fc5aa1da7fab697a247a164712f6696c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
Log Message:
-----------
AMDGPU: Add tests for every mfma intrinsic v-to-a mapping (#153026)
Make sure the MFMA VGPR to AGPR InstrMapping table is complete.
I think I got everything, except the full cross product of input
types with the mfma scale intrinsics. Also makes sure we have
coverage for smfmac and mfma_scale cases.
Commit: d7a3ab220d50e7022840f5764767b64857771aae
https://github.com/llvm/llvm-project/commit/d7a3ab220d50e7022840f5764767b64857771aae
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/lasx/shuffle-as-permute-and-shuffle.ll
Log Message:
-----------
[LoongArch] Use xvperm.w for cross-lane access within a single vector (#151634)
Commit: 71b64bc5c75c9d8466a962d27b852f60250319bd
https://github.com/llvm/llvm-project/commit/71b64bc5c75c9d8466a962d27b852f60250319bd
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
A clang/test/CIR/CodeGen/mms-bitfields.c
Log Message:
-----------
[CIR] Add support for discrete bit-field (#156085)
This PR adds support for the discrete bit-field layout.
It is the same as this PR: https://github.com/llvm/clangir/pull/1860
Commit: a95edec28a4900d15f6fce17561964071600609a
https://github.com/llvm/llvm-project/commit/a95edec28a4900d15f6fce17561964071600609a
Author: Luke Lau <luke at igalia.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
Log Message:
-----------
[RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOptimizer (#156618)
If an instruction's demanded VL is a virtual register defined by a vleff
instruction, it might not dominate and fail to have its VL reduced.
In leiu of the output VL, we can try and use the AVL passed to the vleff
itself since it will be at least greater than or equal the original VL.
I tried to create an LLVM IR test for this in but didn't have any luck
because the scheduler kept on moving the instruction past the vleff, so
it always dominated. So I've just included some mir tests instead.
Commit: 4e348bf628566b323790a02a85433cfdf8a482cb
https://github.com/llvm/llvm-project/commit/4e348bf628566b323790a02a85433cfdf8a482cb
Author: Lang Hames <lhames at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M orc-rt/include/orc-rt/WrapperFunctionResult.h
Log Message:
-----------
[orc-rt] Fix memory leak in WrapperFunctionResult. (#156795)
Previously `Tmp` could have been left owning a heap-allocated buffer and
would not have freed it on destruction (since Tmp was a C
orc_rt_WrapperFunctionResult).
This patch removes Tmp and simply resets R before swapping it with
Other.R.
Commit: a4104abb2b4392deeeb0806a005b3f8b564cb126
https://github.com/llvm/llvm-project/commit/a4104abb2b4392deeeb0806a005b3f8b564cb126
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
Log Message:
-----------
[RISCV] Fold (vslide1up undef, v, (extract_elt x, 0)) into (vslideup x, v, 1) (#154847)
To a slide1up, if the scalar value we're sliding in was extracted from
the first element of a vector, we can use a normal vslideup of 1 instead
with its passthru being that vector. This can eliminate an
extract_element instruction (i.e. vfmv.f.s, vmv.x.s).
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: 19d27b40c44cfcbd2c86ac3d9ce6a89de90477c7
https://github.com/llvm/llvm-project/commit/19d27b40c44cfcbd2c86ac3d9ce6a89de90477c7
Author: Lang Hames <lhames at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M orc-rt/unittests/WrapperFunctionResultTest.cpp
Log Message:
-----------
[orc-rt] Fix WrapperFunctionResultTest comments. NFC. (#156797)
Commit: 1ce90bcb29816578e758d96728715d5acf6d5758
https://github.com/llvm/llvm-project/commit/1ce90bcb29816578e758d96728715d5acf6d5758
Author: Kazu Hirata <kazu at google.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
Log Message:
-----------
[NVPTX] Remove unnecessary casts (NFC) (#156275)
getSubtargetImpl() already returns const NVPTXSubtarget *.
Commit: 93785ff4a025691c8f6a67dbe164801a1c35d1d4
https://github.com/llvm/llvm-project/commit/93785ff4a025691c8f6a67dbe164801a1c35d1d4
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
Log Message:
-----------
[BOLT][AArch64][instr] Remove red zone clobbering protection (#156129)
We can safely remove the red zone clobbering protection in arm64
instrumentation sequence, since there is no red zone in AArch64
ELF/Linux system.
Commit: 6af1247ecb950ae0e31499bb681afc9537985b7f
https://github.com/llvm/llvm-project/commit/6af1247ecb950ae0e31499bb681afc9537985b7f
Author: Lang Hames <lhames at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
A orc-rt/include/orc-rt-c/WrapperFunction.h
R orc-rt/include/orc-rt-c/WrapperFunctionResult.h
A orc-rt/include/orc-rt/WrapperFunction.h
R orc-rt/include/orc-rt/WrapperFunctionResult.h
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/WrapperFunctionBufferTest.cpp
R orc-rt/unittests/WrapperFunctionResultTest.cpp
Log Message:
-----------
[orc-rt] Rename WrapperFunctionBuffer and headers. (#156799)
Renames WrapperFunctionResult to WrapperFunctionBuffer. This reflects
intended usage as a buffer for both arguments and results.
The WrapperFunctionResult.h headers are renamed to WrapperFunction.h as
they will be extended with further wrapper-function related APIs in an
upcoming patch.
Commit: 8a2dd2bc49055a176501e3720073ba58bbb47a70
https://github.com/llvm/llvm-project/commit/8a2dd2bc49055a176501e3720073ba58bbb47a70
Author: masahi <masahi129 at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
M llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
M llvm/test/CodeGen/NVPTX/tcgen05-fence.ll
M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
M llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
Log Message:
-----------
[NVPTX] Add support for tcgen05 instructions for sm103 target (#156613)
Currently, NVPTX fails to lower some tcgen05 ops for the
sm103 target. It was observed in a downstream project, Triton, in
https://github.com/triton-lang/triton/pull/8045.
So, this patch adds sm103 targets to the hasTcgen05Instructions() method.
All the Lit tests for tcgen05-* are updated as well.
Commit: c5a8841a2a085bce32381d99ae22dc0acadf6a37
https://github.com/llvm/llvm-project/commit/c5a8841a2a085bce32381d99ae22dc0acadf6a37
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
AMDGPU: Change DS classes to use RegisterOperand parameters (#156580)
Start stripping out the uses of getLdStRegisterOperand. This
added a confusing level of indirection where the class at the
definition point was not the actual class used. This was also
pulling in the AV class usage for targets where it isn't
relevant. This was also inflexible for special cases.
Also fixes using default arguments which only served to wrap the
class argument in a RegisterOperand.
This should be done for all the memory instructions.
Commit: 3fa3932e98a865d347521a85f9a51d8516f79bde
https://github.com/llvm/llvm-project/commit/3fa3932e98a865d347521a85f9a51d8516f79bde
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
Log Message:
-----------
[RISCV] Correct getOperandLog2EEW for VCOMPRESS_VM. (#156719)
The mask operand has EEW=1.
Commit: 97d4c7d1eb1bb5d0a5e61867fa9594c6d5875d86
https://github.com/llvm/llvm-project/commit/97d4c7d1eb1bb5d0a5e61867fa9594c6d5875d86
Author: Craig Topper <craig.topper at sifive.com>
Date: 2025-09-03 (Wed, 03 Sep 2025)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
M llvm/test/CodeGen/RISCV/bittest.ll
Log Message:
-----------
[RISCV] Fold (X & (7 << 29)) == 0 -> (srliw X, 29) == 0 for RV64. (#156769)
This is similar to the recently added (X & -4096) == 0 -> (X >> 12) ==
0,
but operating only on the lower 32 bits.
This also removes the (X & (1 << 31)) == 0 -> (xor (srliw X, 31), 1)
isel pattern. seqz and xori 1 should have similar cost and encoding
size.
Commit: 917b45539b8c265665c7376c09f512c4c11c42a8
https://github.com/llvm/llvm-project/commit/917b45539b8c265665c7376c09f512c4c11c42a8
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
Log Message:
-----------
[clang][bytecode] Remove superfluous check for complex types (#156666)
`!E->getType()->isAnyComplexType()` is implied by `!canClassify()`.
Commit: 573627fbc76206a4790dc7ed6a1eb7334779bbda
https://github.com/llvm/llvm-project/commit/573627fbc76206a4790dc7ed6a1eb7334779bbda
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Fix definitions of DS ret atomics with AGPRs (#156655)
These are 2-data operations that need to use all-AGPR or all-VGPR
inputs. Stop defining them with AVLdSt data operands, and add _agpr
variants.
Commit: 76cb5fcfb6f9a4e1a4313648b7179051310c4fa8
https://github.com/llvm/llvm-project/commit/76cb5fcfb6f9a4e1a4313648b7179051310c4fa8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/DSInstructions.td
A llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
Log Message:
-----------
AMDGPU: Define agpr versions of ds permute instructions (#156695)
Correctly model these without AV_* operands. This is another
step towards removing the special casing in
TargetInstrInfo::getRegClass. Also add some tests for this.
Commit: a23a5b06839011569590af5c9bbfb5197b24261b
https://github.com/llvm/llvm-project/commit/a23a5b06839011569590af5c9bbfb5197b24261b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
AMDGPU: Remove the DS special case in getRegClass (#156696)
These instructions should now have proper representation
with separate instructions for operands which must be paired.
Commit: 99718444c4f665a8633d9a0a01cee1dadb3443c1
https://github.com/llvm/llvm-project/commit/99718444c4f665a8633d9a0a01cee1dadb3443c1
Author: Balázs Benics <108414871+balazs-benics-sonarsource at users.noreply.github.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
M clang/lib/StaticAnalyzer/Core/MemRegion.cpp
A clang/test/Analysis/modules/explicit-templ-inst-crash-in-modules.cppm
Log Message:
-----------
[analyzer] Canonicalize the Decls of FieldRegions (#156668)
When calculating the offset of a FieldRegion, we need to find out which
field index the given field refers to.
Previously, if for some reason the field was not found, then the `Idx`
passed to `Layout.getFieldOffset` was out of bounds and caused undefined
behavior when dereferenced an out of bounds element in
`ASTVector::FieldOffsets::operator[]`, which asserts this in debug
builds, but exposes the undefined behavior in release builds.
In this patch, I refactored how we enumerate the fields, and gracefully
handle the scenario where the field is not found.
That case is still bad, but at least it should not expose the undefined
behavior in release builds, and should assert earlier in debug builds
than before.
The motivational case was transformed into a regression test, that would
fail if no canonicalization would happen when creating a FieldRegion.
This was reduced from a production crash.
In the test case, due to how modules work, there would be multiple
copies of the same template specialization in the AST. This could lead
into inconsistent state when the FieldRegion's Decl was different to the
RecordDecl's field - because one referred to the first and the other to
the second. This made `calculateOffset` fail to compute the field index,
triggering the undefined behavior in production.
While this inconsistency gets fixed now, I think the assertion is still
warranted to avoid potential undefined behavior in release builds.
CPP-6691,CPP-6849
Co-authored-by: Marco Borgeaud <marco.borgeaud at sonarsource.com>
Commit: e90e76e15dee4b835b9b2cfd55c0c3f047bb6d76
https://github.com/llvm/llvm-project/commit/e90e76e15dee4b835b9b2cfd55c0c3f047bb6d76
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/declare_mapper_codegen.cpp
Log Message:
-----------
Trying to fix undefined symbol error caused by iterator variable (#141507)
When a mapper is declared with an iterator variable inside the map
clause, it results in unintended behavior due to the iterator being
implicitly created but left uninitialized.
Testcase:
```
typedef struct myvec{
size_t len;
double *data;
} myvec_t;
#pragma omp declare mapper(id:myvec_t v) map( iterator( iterator_variable=0:v.len), tofrom: v.data[iterator_variable])
int main()
{
int errors = 0;
myvec_t s;
#pragma omp target map(mapper(id), to:s)
{
}
return 0;
}
```
The error we get while compiling this is:
```
/usr/lib64/gcc/x86_64-suse-linux/14/../../../../x86_64-suse-linux/bin/ld: /tmp/test-f70647.o: in function `.omp_mapper._ZTS5myvec.id':
test.cpp:(.text+0x21a): undefined reference to `iterator_variable'
/llvm-project/install/bin/clang-linker-wrapper: error: 'ld' failed
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
```
This patch tries to fix this by initializing the iterator variable to a
null constant.
---------
Co-authored-by: Shashwathi N <nshashwa at pe31.hpc.amslabs.hpecorp.net>
Commit: 387860e9ced9210bedfd346c775476110077bb6c
https://github.com/llvm/llvm-project/commit/387860e9ced9210bedfd346c775476110077bb6c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M libcxx/test/libcxx/containers/associative/map/abi.compile.pass.cpp
M libcxx/test/libcxx/containers/associative/unord.map/abi.compile.pass.cpp
A libcxx/test/libcxx/utilities/tuple/abi.compile.pass.cpp
Log Message:
-----------
[libc++] Add ABI tests for introducing _LIBCPP_COMPRESSED_ELEMENT (#156416)
#134253 refactors a few classes to use `[[no_unique_address]]` instead
of the EBO. This adds tests to ensure there are no ABI breaks.
Commit: 3821885b433bb5db146a3749873209b350e0e969
https://github.com/llvm/llvm-project/commit/3821885b433bb5db146a3749873209b350e0e969
Author: Karthik Senthil <karthik.senthil at intel.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/test/CodeGen/X86/AMX/amx-sink-config-after-calls.mir
Log Message:
-----------
[AMX] Fix LIT test with adjustsStack attribute for expensive checks build. (#156808)
The generated MIR fails machine verifier as stack pointer is being
modified without appropriate attributes in frameInfo. This PR fixes this
issue by adding adjustsStack=true attribute. Fixes the post commit
regression identified in #155673.
Commit: cd44260ee64f948b5a8ac9e49082c0c14fabf33f
https://github.com/llvm/llvm-project/commit/cd44260ee64f948b5a8ac9e49082c0c14fabf33f
Author: A. Jiang <de34 at live.cn>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M libcxx/test/extensions/clang/thread/thread.mutex/lock.verify.cpp
Log Message:
-----------
[libc++][test] Get rid of warning on macOS about undefined macro (#156785)
`TEST_CLANG_VER` is not defined for Apple Clang, so it's better to
detect whether the macro is defined to get rid of warnings due to
`-Wundef`. This also corresponds to the guard in `<mutex>`.
Commit: e8fa13ca4edcae7da083555a1cb561e6f298c80c
https://github.com/llvm/llvm-project/commit/e8fa13ca4edcae7da083555a1cb561e6f298c80c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M libcxx/docs/ABIGuarantees.rst
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/include/__configuration/abi.h
M libcxx/include/__iterator/back_insert_iterator.h
M libcxx/include/__iterator/front_insert_iterator.h
M libcxx/include/__iterator/insert_iterator.h
M libcxx/include/__iterator/istream_iterator.h
M libcxx/include/__iterator/istreambuf_iterator.h
M libcxx/include/__iterator/iterator.h
M libcxx/include/__iterator/ostream_iterator.h
M libcxx/include/__iterator/ostreambuf_iterator.h
M libcxx/include/__iterator/reverse_iterator.h
M libcxx/include/__memory/raw_storage_iterator.h
Log Message:
-----------
[libc++] Split ABI flag for removing iterator bases and removing the second member in reverse_iterator (#143079)
Currently `_LIBCPP_NO_ITERATOR_BASES` controls both whether specific
classes derive from `iterator` and whether `reverse_iterator` has a
second member variable. These two changes are orthogonal though, and one
can be applied in all langauge modes while the other change is only
conforming for C++17 and later.
Commit: 34d4f0c13666ea25b4d27dcb96dfc70da005f286
https://github.com/llvm/llvm-project/commit/34d4f0c13666ea25b4d27dcb96dfc70da005f286
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M libcxx/CMakeLists.txt
M libcxx/docs/Modules.rst
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/docs/Status/Cxx17Papers.csv
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/include/__algorithm/simd_utils.h
M libcxx/include/__atomic/atomic.h
M libcxx/include/__configuration/abi.h
M libcxx/include/__configuration/availability.h
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/concepts.h
M libcxx/include/__math/hypot.h
M libcxx/include/__memory/compressed_pair.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/string_view
M libcxx/src/atomic.cpp
M libcxx/src/experimental/tzdb.cpp
M libcxx/test/extensions/posix/xopen_source.gen.py
M libcxx/test/libcxx-03/containers/associative/reference_comparator_abi.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.verify.cpp
M libcxx/test/libcxx-03/numerics/complex.number/cmplx.over.pow.pass.cpp
M libcxx/test/libcxx-03/vendor/apple/disable-availability.sh.cpp
M libcxx/test/libcxx/algorithms/alg.modifying.operations/copy_move_nontrivial.pass.cpp
M libcxx/test/libcxx/algorithms/callable-requirements-rvalue.compile.pass.cpp
M libcxx/test/libcxx/atomics/atomics.syn/wait.issue_85107.pass.cpp
M libcxx/test/libcxx/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
M libcxx/test/libcxx/containers/associative/reference_comparator_abi.compile.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.multiset/insert.temporary.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.multiset/insert_range.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.set/insert.temporary.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.set/insert_range.pass.cpp
M libcxx/test/libcxx/containers/strings/basic.string/asan_turning_off.pass.cpp
M libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.ctor.layout_stride.pass.cpp
M libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.ctor.layout_stride.pass.cpp
M libcxx/test/libcxx/input.output/iostream.format/output.streams/ostream.syn/includes.compile.pass.cpp
M libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
M libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_piecewise_pair.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_from_underaligned_buffer.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_in_geometric_progression.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.res.pool/unsynchronized_buffer.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/pmr.availability.verify.cpp
M libcxx/test/libcxx/vendor/apple/disable-availability.sh.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_backward.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.count/ranges.count.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/equal.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/ranges.equal.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/ranges.find.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/assign.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/ctor.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/exchange.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_all.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_one.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.float.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/store.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/wait.pass.cpp
M libcxx/test/std/containers/sequences/deque/deque.cons/from_range.pass.cpp
M libcxx/test/std/containers/sequences/vector.bool/shrink_to_fit.pass.cpp
M libcxx/test/std/containers/sequences/vector.bool/small_allocator_size.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.capacity/shrink_to_fit.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.cons/construct_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.cons/construct_iter_iter_alloc.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/conversion.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/copy.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcode/syserr.errcode.constructors/lwg3629.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcode/syserr.errcode.modifiers/lwg3629.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcondition/syserr.errcondition.constructors/lwg3629.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcondition/syserr.errcondition.modifiers/lwg3629.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/filebuf.assign/nonmember_swap_min.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/filebuf.virtuals/setbuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/print.fun/includes.compile.pass.cpp
M libcxx/test/std/input.output/iostreams.base/ios.base/ios.types/ios_Init/ios_Init.global.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.members/str.allocator_propagation.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.members/str.allocator_propagation.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.members/str.allocator_propagation.pass.cpp
M libcxx/test/std/numerics/c.math/cmath.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.special/gh_101960_ambiguous_ctor.pass.cpp
M libcxx/test/std/numerics/complex.number/complex/bit_cast.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.lcm/lcm.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/types.h
M libcxx/test/std/ranges/range.factories/range.iota.view/size.pass.cpp
M libcxx/test/std/ranges/range.req/range.view/enable_view.compile.pass.cpp
M libcxx/test/std/ranges/ranges_robust_against_no_unique_address.pass.cpp
M libcxx/test/std/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp
M libcxx/test/std/strings/basic.string/string.nonmembers/string_op+/string.string_view.pass.cpp
M libcxx/test/std/thread/futures/futures.task/futures.task.members/type.verify.cpp
M libcxx/test/std/thread/thread.jthread/join.deadlock.pass.cpp
M libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.id/cmp.pass.cpp
M libcxx/test/std/time/time.duration/time.duration.nonmember/ostream.pass.cpp
M libcxx/test/std/time/time.syn/formatter.duration.pass.cpp
M libcxx/test/std/utilities/allocator.adaptor/allocator.adaptor.cnstr/allocs.pass.cpp
M libcxx/test/std/utilities/allocator.adaptor/base-is-uglified.compile.pass.cpp
M libcxx/test/std/utilities/expected/expected.expected/ctor/ctor.copy.pass.cpp
M libcxx/test/std/utilities/expected/expected.expected/observers/has_value.pass.cpp
M libcxx/test/std/utilities/expected/types.h
M libcxx/test/std/utilities/format/format.functions/bug_81590.compile.pass.cpp
M libcxx/test/std/utilities/format/format.functions/format_tests.h
M libcxx/test/std/utilities/memory/allocator.uses/allocator.uses.construction/uses_allocator_construction_args.pass.cpp
M libcxx/test/std/utilities/memory/pointer.conversion/to_address.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/overload_compare_iterator.h
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.weak/util.smartptr.weak.const/pr40459.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/gh_101960_internal_ctor.compile.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.cons/char_ptr_ctor.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/nonstdmem.uglified.compile.pass.cpp
M libcxx/test/std/utilities/tuple/tuple.tuple/tuple.creation/tuple_cat.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.class.general/equality.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/assign.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/copy.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/default.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/memory_resource_convert.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/other_alloc.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.eq/equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.eq/not_equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/allocate_deallocate_bytes.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/allocate_deallocate_object.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair_const_lvalue_pair.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair_rvalue.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair_values.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_piecewise_pair.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_piecewise_pair_evil.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_types.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/deallocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/destroy.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/new_delete_object.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/select_on_container_copy_construction.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_deque_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_deque_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_forward_list_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_list_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_list_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_map_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_map_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_regex_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_set_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_set_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_string_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_string_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_map_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_map_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_set_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_set_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_vector_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_vector_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.global/default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.global/new_delete_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.global/null_memory_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.ctor/copy_move.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.ctor/with_default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.ctor/without_buffer.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_deallocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_exception_safety.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_from_initial_buffer.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_from_zero_sized_buffer.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_in_geometric_progression.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_overaligned_request.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_with_initial_size.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/equality.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.ctor/ctor_does_not_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.ctor/sync_with_default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.ctor/unsync_with_default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/equality.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_overaligned_request.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_reuse_blocks.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_deallocate_matches_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_overaligned_request.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_reuse_blocks.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_deallocate_matches_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/construct.verify.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.eq/equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.eq/not_equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.private/private_members.verify.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.private/protected_members.verify.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/deallocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/dtor.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/is_equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/nodiscard.verify.cpp
M libcxx/test/std/utilities/utility/pairs/pairs.pair/ctor.pair_like.pass.cpp
M libcxx/test/std/utilities/variant/variant.variant/variant.ctor/T.pass.cpp
M libcxx/test/std/utilities/variant/variant.visit.member/visit_return_type.pass.cpp
M libcxx/test/std/utilities/variant/variant.visit/visit_return_type.pass.cpp
M libcxx/test/support/is_transparent.h
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libc++][NFC] Use llvm.org/PR to link to bug reports (#156288)
We've built up quite a few links directly to github within the code
base. We should instead use `llvm.org/PR<issue-number>` to link to bugs,
since that is resilient to the bug tracker changing in the future. This
is especially relevant for tests linking to bugs, since they will
probably be there for decades to come. A nice side effect is that these
links are significantly shorter than the GH links, making them much less
of an eyesore.
This patch also replaces a few links that linked to the old bugzilla
instance on llvm.org.
Commit: 4d927a5faf42d025410586f0cdc3bf60ef198a86
https://github.com/llvm/llvm-project/commit/4d927a5faf42d025410586f0cdc3bf60ef198a86
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/include/llvm/IR/DataLayout.h
M llvm/lib/IR/DataLayout.cpp
M llvm/test/CodeGen/AArch64/alloca-oversized.ll
Log Message:
-----------
[DataLayout] Specialize the getTypeAllocSize() implementation (#156687)
getTypeAllocSize() currently works by taking the type store size and
aligning it to the ABI alignment. However, this ends up doing redundant
work in various cases, for example arrays will unnecessarily repeat the
alignment step, and structs will fetch the StructLayout multiple times.
As this code is rather hot (it is called every time we need to calculate
GEP offsets for example), specialize the implementation. This repeats a
small amount of logic from getAlignment(), but I think that's
worthwhile.
Commit: 3f757a39f2855cd06c62a85b8e27fd56fa017e78
https://github.com/llvm/llvm-project/commit/3f757a39f2855cd06c62a85b8e27fd56fa017e78
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/CodeGen/ARM/bswap-inline-asm.ll
M llvm/test/CodeGen/X86/bswap-inline-asm.ll
M llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll
M llvm/test/CodeGen/X86/pr67333.ll
Log Message:
-----------
[CodeGen] Remove ExpandInlineAsm hook (#156617)
This hook replaces inline asm with LLVM intrinsics. It was intended to
match inline assembly implementations of bswap in libc headers and
replace them more optimizable implementations.
At this point, it has outlived its usefulness (see
https://github.com/llvm/llvm-project/issues/156571#issuecomment-3247638412),
as libc implementations no longer use inline assembly for this purpose.
Additionally, it breaks the "black box" property of inline assembly,
which some languages like Rust would like to guarantee.
Fixes https://github.com/llvm/llvm-project/issues/156571.
Commit: 010f1ea3b3f425a1ef8bf4d25b89eae990ef591a
https://github.com/llvm/llvm-project/commit/010f1ea3b3f425a1ef8bf4d25b89eae990ef591a
Author: woruyu <1214539920 at qq.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
A llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp
M llvm/unittests/Target/ARM/CMakeLists.txt
Log Message:
-----------
[DAG][ARM] ComputeKnownBitsForTargetNode - add handling for ARMISD VORRIMM\VBICIMM nodes (#149494)
### Summary
This PR resolves https://github.com/llvm/llvm-project/issues/147179
Commit: 5a2499e3922997f7ebf06b23cdce9e83ce3b7f66
https://github.com/llvm/llvm-project/commit/5a2499e3922997f7ebf06b23cdce9e83ce3b7f66
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
AMDGPU: Change FLAT classes to use RegisterOperand parameters (#156581)
This will make it easier to precisely express operand constraints
without having the implicit getLdStRegisterOperand at the bottom.
Also prunes out using AV classes in some instructions where AGPRs
are not relevant.
Commit: d0246fe1e79c6ea06b6b72f66a71a96a3342aa42
https://github.com/llvm/llvm-project/commit/d0246fe1e79c6ea06b6b72f66a71a96a3342aa42
Author: Sergei Barannikov <barannikov88 at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/Sparc/SparcInstrInfo.td
Log Message:
-----------
[Sparc] Remove extra ASRRegs operand in SMAC/UMAC instructions (#156751)
The `$asr18` operand is not decoded/encoded/printed,
and ASR18 is already in the `Uses` list.
Extracted from #156358, where the extra operand causes DecoderEmitter
to emit an error about an operand with a missing encoding.
Commit: d1408667de830da8817c24cb9788da6caae551c7
https://github.com/llvm/llvm-project/commit/d1408667de830da8817c24cb9788da6caae551c7
Author: Nikita Popov <npopov at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Analysis/MemorySSAUpdater.cpp
A llvm/test/Transforms/LICM/pr117157.ll
Log Message:
-----------
[MemorySSA] Don't create phi nodes in fixupDefs() (#156021)
The general flow when inserting MemoryDefs is:
* Insert the def and set it's defining access (may insert phis)
* Insert IDF phis
* Update defining access for defs after the new one (fixupDefs)
* Rename uses if requested
fixupDefs() uses getPreviousDef() which can create new MemoryPHIs, but
for which we're not going to insert IDF phis, so the required dominance
property may not hold.
I believe this is a leftover from a time before the "Insert IDF phis"
step existed. Now that step should already ensure that all necessary
MemoryPhis have been inserted, and we only need to update them.
The fixupDefs() implementation was also returning after updating a
single access, which is not right.
Fixes https://github.com/llvm/llvm-project/issues/47875.
Fixes https://github.com/llvm/llvm-project/issues/117157.
Fixes https://github.com/llvm/llvm-project/issues/152998.
Fixes https://github.com/llvm/llvm-project/issues/155161.
Fixes https://github.com/llvm/llvm-project/issues/155184.
Commit: 018dc1b3977bb249d55a6808bb45802a10f818fa
https://github.com/llvm/llvm-project/commit/018dc1b3977bb249d55a6808bb45802a10f818fa
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
Log Message:
-----------
[AMDGPU] Tail call support for whole wave functions (#145860)
Support tail calls to whole wave functions (trivial) and from whole wave
functions (slightly more involved because we need a new pseudo for the
tail call return, that patches up the EXEC mask).
Move the expansion of whole wave function return pseudos (regular and
tail call returns) to prolog epilog insertion, since that's where we
patch up the EXEC mask.
Commit: 88effbff10449b79226743933bd3eae00228f626
https://github.com/llvm/llvm-project/commit/88effbff10449b79226743933bd3eae00228f626
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3cx.s
M llvm/test/MC/AMDGPU/vop3-literal.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3cx.txt
Log Message:
-----------
[AMDGPU] Do not use 64-bit literals with VOP3* encodings (#156602)
Encoding sometimes uses a 64-bit instead of 32-bit literal because it
does not know the signedness of the operand: if the value does not fit
in both a 32-bit signed and a 32-bit unsigned then it will use a 64-bit
literal for safety. However it should never do this for VOP3 and VOP3P
encoded instructions, because these encodings do not allow 64-bit
literal operands.
Commit: 3ec7b895be67f0d74613d35aa5aa1580a436aa05
https://github.com/llvm/llvm-project/commit/3ec7b895be67f0d74613d35aa5aa1580a436aa05
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/ConditionalController.py
M cross-project-tests/debuginfo-tests/dexter/feature_tests/commands/control/dex-continue.cpp
M cross-project-tests/debuginfo-tests/dexter/feature_tests/commands/control/dex_step_function.cpp
Log Message:
-----------
[Dexter] Only increment step index if we record the step (#156832)
Prior to this patch we incremented step_index every time the debugger
stopped. Now that some stops are not recorded, we should only increment
the step_index for those that are.
This should make the `-v` output more consistent between platforms and
debuggers.
Commit: e2bd10cf16c3f90813de5b64f348ece035a6bb68
https://github.com/llvm/llvm-project/commit/e2bd10cf16c3f90813de5b64f348ece035a6bb68
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-cooperative-atomics.cl
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-cooperative-atomics.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
A llvm/test/Verifier/AMDGPU/llvm.amdgcn.cooperative.atomic.ll
Log Message:
-----------
[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)
- Add clang built-ins + sema/codegen
- Add IR Intrinsic + verifier
- Add DAG/GlobalISel codegen for the intrinsics
- Add lowering in SIMemoryLegalizer using a MMO flag.
Commit: e4c0b3e1118d51a5f52b692dc49c5c62b68c7876
https://github.com/llvm/llvm-project/commit/e4c0b3e1118d51a5f52b692dc49c5c62b68c7876
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/blend-costs.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
Log Message:
-----------
[VPlan] Simplify x && false -> false, x | 0 -> x (#156345)
The OR x, 0 -> x simplification has been introduced to avoid
regressions.
Commit: 837a706fb67c4708347767cc0e7ebae3ad5352fa
https://github.com/llvm/llvm-project/commit/837a706fb67c4708347767cc0e7ebae3ad5352fa
Author: Jay Foad <jay.foad at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
A llvm/test/MC/AMDGPU/warnings.s
Log Message:
-----------
[AMDGPU] Fix source location for assembler warnings (#156621)
Call MCInst::setLoc earlier so it is available for warnings generated
during MatchInstructionImpl.
Commit: 68268c7db28541426948e0b35b684d630a3bfada
https://github.com/llvm/llvm-project/commit/68268c7db28541426948e0b35b684d630a3bfada
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[KeyInstr] Add release note following #149509 (#156005)
Key Instructions (-gkey-instructions) is now enabled by default when DWARF is
being emitted, the input is plain C/C++, and optimisations are enabled.
Add release note for the change in default behaviour.
Commit: 9539b75af0fc319137301810521f11641bbfa37f
https://github.com/llvm/llvm-project/commit/9539b75af0fc319137301810521f11641bbfa37f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/unittests/Target/ARM/CMakeLists.txt
Log Message:
-----------
Fix buildbots - add missing LLVMAnalysis.lib dependency from #149494
Commit: f0332eb1f2c110b189b84ba268076dbfa28a6f54
https://github.com/llvm/llvm-project/commit/f0332eb1f2c110b189b84ba268076dbfa28a6f54
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/unittests/Target/ARM/CMakeLists.txt
Log Message:
-----------
Fix buildbots - add missing LLVMAsmParser.lib dependency from #149494
Commit: eb191833c9f11cfb849eb83bb6fca48b85309f57
https://github.com/llvm/llvm-project/commit/eb191833c9f11cfb849eb83bb6fca48b85309f57
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
Log Message:
-----------
[AArch64] canCreateUndefOrPoisonForTargetNode - AArch64ISD::MOVI opcodes can't create undef/poison (#149323)
Possible fix for failed fold in #148191
Commit: c14052e20b87bc74a031d09fb312723e0751ed0f
https://github.com/llvm/llvm-project/commit/c14052e20b87bc74a031d09fb312723e0751ed0f
Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
Log Message:
-----------
[VPlan] Let Not preserve uniformity in isSingleScalar (#156676)
LogicalAnd and WidePtrAdd should also preserve uniformity, but we don't
have test coverage to enable adding them.
Commit: b400fd115145ccea0b62944e37e74eedc9da223f
https://github.com/llvm/llvm-project/commit/b400fd115145ccea0b62944e37e74eedc9da223f
Author: Florian Hahn <flo at fhahn.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
Log Message:
-----------
[LAA] Support assumptions with non-constant deref sizes. (#156758)
Update evaluatePtrAddrecAtMaxBTCWillNotWrap to support non-constant
sizes in dereferenceable assumptions.
Apply loop-guards in a few places needed to reason about expressions
involving trip counts of the from (BTC - 1).
PR: https://github.com/llvm/llvm-project/pull/156758
Commit: 05da1603e7132f8168a7f0c9655b2f9ae18c5ff7
https://github.com/llvm/llvm-project/commit/05da1603e7132f8168a7f0c9655b2f9ae18c5ff7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/test/CodeGen/X86/avx512fp16-fold-load-binops.ll
M llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/vec-strict-128-fp16.ll
Log Message:
-----------
[X86] Add assembly comment for VMOVSH instructions (#156848)
Matches existing MOVSD/S implementations
Commit: f831463704e163030c5dc374c406e9f4126a436e
https://github.com/llvm/llvm-project/commit/f831463704e163030c5dc374c406e9f4126a436e
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Analysis/MemoryLocation.cpp
A llvm/test/Analysis/BasicAA/scalable-dse-aa.ll
Log Message:
-----------
[MemoryLocation] Size Scalable Masked MemOps (#154785)
Scalable masked loads and stores with a get active lane mask whose size
is less than or equal to the scalable minimum number of elements can be
be proven to have a fixed size. Adding this infomation allows scalable
masked loads and stores to benefit from alias analysis optimizations.
Commit: faa7a87c86745b60650870a28934e542e8ee4a3a
https://github.com/llvm/llvm-project/commit/faa7a87c86745b60650870a28934e542e8ee4a3a
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/utils/TableGen/ClangSACheckersEmitter.cpp
Log Message:
-----------
[NFC][TableGen][analyzer] Fix some obsolete comments (#156677)
ClangSACheckersEmitter.cpp had some comments that described the
structure of its output, which would have been helpful, but became out
of sync with the code. This commit updates them to ensure they are
consistent with `CheckerRegistry.cpp`.
Commit: 465f79373519277fb80188a10176a231d3c74c46
https://github.com/llvm/llvm-project/commit/465f79373519277fb80188a10176a231d3c74c46
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
Log Message:
-----------
[SeparateConstOffsetFromGEP] Highlight that trunc is handled. NFC (#154563)
Update code comments and variable/function names to make it more clear
that we handle trunc instructions (and not only sext/zext) when
extracting constant offsets from a GEP index expressions.
This for example renames the vector ExtInsts to CastInsts.
Commit: 4e8b4d619030a53bd242bbea9a9fdf862c2e763c
https://github.com/llvm/llvm-project/commit/4e8b4d619030a53bd242bbea9a9fdf862c2e763c
Author: Ross Brunton <ross at codeplay.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M offload/tools/deviceinfo/CMakeLists.txt
M offload/tools/deviceinfo/llvm-offload-device-info.cpp
Log Message:
-----------
[Offload] Port llvm-offload-device-info to new offload API (#155626)
This is a tool similar to urinfo that simply prints properties of all
devices. The old openMP version has been ported to liboffload.
Commit: 371d1a8e3e8513becf0e25ec6e6830d29221a902
https://github.com/llvm/llvm-project/commit/371d1a8e3e8513becf0e25ec6e6830d29221a902
Author: Andrew Savonichev <andrew.savonichev at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/DynamicLoaderWindowsDYLD.h
A lldb/test/API/windows/launch/replace-dll/Makefile
A lldb/test/API/windows/launch/replace-dll/TestReplaceDLL.py
A lldb/test/API/windows/launch/replace-dll/bar.c
A lldb/test/API/windows/launch/replace-dll/foo.c
A lldb/test/API/windows/launch/replace-dll/test.c
Log Message:
-----------
[lldb] Use weak pointers instead of shared pointers in DynamicLoader (#156446)
DynamicLoaderWindowsDYLD uses pointers to Modules to maintain a map
from modules to their addresses, but it does not need to keep "strong"
references to them. Weak pointers should be enough, and would allow
modules to be released elsewhere.
Other DynamicLoader classes do not use shared pointers as well. For
example, DynamicLoaderPOSIXDYLD has a similar map with weak pointers.
Actually testing for modules being completely released can be tricky.
The test here is just to illustrate the case where shared pointers kept
modules in DynamicLoaderWindowsDYLD and prevented them from being
released. The test executes the following sequence:
1. Create a target, load an executable and run it.
2. Remove one module from the target. The target should be the last
actual use of the module, but we have another reference to it in the
shared module cache.
3. Call MemoryPressureDetected to remove this last reference from the
cache.
4. Replace the corresponding DLL file.
LLDB memory maps DLLs, and this makes files read-only on Windows. Unless
the modules are completely released (and therefore unmapped), (4) is
going to fail with "access denied".
However, the test does not trigger the bug completely - it passes with
and without the change.
Commit: 73c5bc5cfdc1e8e3dd8bbc048f9132170b80f748
https://github.com/llvm/llvm-project/commit/73c5bc5cfdc1e8e3dd8bbc048f9132170b80f748
Author: Paul Walker <paul.walker at arm.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bdep.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bext.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bgrp.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_sm4e.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_sm4ekey.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_b16b16.cpp
M llvm/test/CodeGen/AArch64/sve2-intrinsics-sm4.ll
Log Message:
-----------
[SVE ACLE] Remove explicit sve2 requirement from crypto and b16b16 builtins. (#156456)
The instructions have no direct dependency on SVE2, nor does the code
generator require it.
Commit: 5899bca6baa99977c48c7c053239e0028a14182d
https://github.com/llvm/llvm-project/commit/5899bca6baa99977c48c7c053239e0028a14182d
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
A llvm/test/CodeGen/AArch64/sme-streaming-mode-landingpads.ll
Log Message:
-----------
[AArch64][SME] Resume streaming-mode on entry to exception handlers (#156638)
This patch adds a new `TargetLowering` hook `lowerEHPadEntry()` that is
called at the start of lowering EH pads in SelectionDAG. This allows the
insertion of target-specific actions on entry to exception handlers.
This is used on AArch64 to insert SME streaming-mode switches at landing
pads. This is needed as exception handlers are always entered with
PSTATE.SM off, and the function needs to resume the streaming mode of
the function body.
Commit: f1c9950cc8b628e6f0ba7dcd1b1c0b393c54e032
https://github.com/llvm/llvm-project/commit/f1c9950cc8b628e6f0ba7dcd1b1c0b393c54e032
Author: Walter Lee <49250218+googlewalt at users.noreply.github.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang-tools-extra/test/clang-tidy/check_clang_tidy.py
Log Message:
-----------
[clang-tidy] Fix file extension inconsistency (#156528)
This fixes an issue with #150791. In CheckRunner, we treat files with
unrecognized extensions as ".cpp", by forcefully assigning `extension =
".cpp"` if it's not already one of `".c", ".hpp", ".m", or ".mm"`. Make
the new code which chooses the default `-std` argument be consistent
with that, so that using other file extensions doesn't trigger an error
message like `error: invalid argument '-std=c99' not allowed with 'C++'`
Commit: 5eb0ec4c1c4f3751bb5f00aa13053567a86ce70d
https://github.com/llvm/llvm-project/commit/5eb0ec4c1c4f3751bb5f00aa13053567a86ce70d
Author: Lang Hames <lhames at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M orc-rt/include/CMakeLists.txt
Log Message:
-----------
[orc-rt] Fix header list in CMakeLists.txt after 6af1247ecb9. (#156867)
6af1247ecb9 renamed both C and C++ WrapperFunctionResult.h headers to
WrapperFunction.h. This commit updates CMakeLists.txt to reflect that
change.
Commit: 83ca87715974d386e1ffee8ae8797d8f0f1db205
https://github.com/llvm/llvm-project/commit/83ca87715974d386e1ffee8ae8797d8f0f1db205
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/test/AST/ByteCode/openmp.cpp
Log Message:
-----------
[clang][bytecode] Reject final ltor casts on string literals (#156669)
Similar to what the current interpreter does.
Commit: f84d23183aaa84e594459db83c057d8923497557
https://github.com/llvm/llvm-project/commit/f84d23183aaa84e594459db83c057d8923497557
Author: Lang Hames <lhames at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M orc-rt/include/orc-rt-c/WrapperFunction.h
Log Message:
-----------
[orc-rt] Fix typo in include guard comment. NFC. (#156869)
Commit: 8f376689ecdb76f78053f9186646dc14c82d5628
https://github.com/llvm/llvm-project/commit/8f376689ecdb76f78053f9186646dc14c82d5628
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/Disasm.cpp
Log Message:
-----------
[clang][bytecode] Print 8 bit integers as 32 bit in Function::dump() (#156858)
Otherwise we get the char representation in our disassembly output,
which we don't want.
Commit: 379e121122ab43d85c6946c56c99c7bfd99e689c
https://github.com/llvm/llvm-project/commit/379e121122ab43d85c6946c56c99c7bfd99e689c
Author: Hongyu Chen <xxs_chy at outlook.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-vpmadd52.ll
Log Message:
-----------
[X86] Compute the known bits for VPMADD52L/VPMADD52H in SimplifyDemandedBitsForTargetNode (#156847)
Address TODO and compute the known bits with the intermediate result.
Commit: c0f84d31ed3e481d902b92efe676e7793abafe27
https://github.com/llvm/llvm-project/commit/c0f84d31ed3e481d902b92efe676e7793abafe27
Author: Muhammad Omair Javaid <omair.javaid at linaro.org>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M lldb/test/API/python_api/basename/TestGetBaseName.py
Log Message:
-----------
[lldb] Add issue no to xfail decorators in TestGetBaseName (#155939)
TestGetBaseName.py is currently marked as an expected failure on Windows
because SBFunction::GetBaseName() and SBSymbol::GetBaseName() don’t yet
handle MSVC-style mangling.
This patch updates the @expectedFailureAll decorator to include a
reference to https://github.com/llvm/llvm-project/issues/156861
Commit: 209d91d9e4c43966a908646a1b4ab2526bfc899d
https://github.com/llvm/llvm-project/commit/209d91d9e4c43966a908646a1b4ab2526bfc899d
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M offload/test/tools/llvm-omp-device-info.c
Log Message:
-----------
[Offload] Fix CHECK string in llvm-omp-device-info test (#156872)
Commit: 8bdd9090d0c75226b47232380d96051ff173b067
https://github.com/llvm/llvm-project/commit/8bdd9090d0c75226b47232380d96051ff173b067
Author: moorabbit <moorabbit at proton.me>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/Headers/avx512dqintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Headers][X86] Add constexpr support for some AVX[512] intrinsics. (#156567)
The following AVX[512] intrinsics are now constexpr:
- `_mm_mask_cvtepi32_pd`
- `_mm_maskz_cvtepi32_pd`
- `_mm_mask_cvtepi32_ps`
- `_mm_maskz_cvtepi32_ps`
- `_mm_cvtepu32_pd`
- `_mm_mask_cvtepu32_pd`
- `_mm_maskz_cvtepu32_pd`
- `_mm_cvtepu32_ps`
- `_mm_mask_cvtepu32_ps`
- `_mm_maskz_cvtepu32_ps`
- `_mm256_mask_cvtepi32_pd`
- `_mm256_maskz_cvtepi32_pd`
- `_mm256_mask_cvtepi32_ps`
- `_mm256_maskz_cvtepi32_ps`
- `_mm256_cvtepu32_pd`
- `_mm256_mask_cvtepu32_pd`
- `_mm256_maskz_cvtepu32_pd`
- `_mm256_cvtepu32_ps`
- `_mm256_mask_cvtepu32_ps`
- `_mm256_maskz_cvtepu32_ps`
- `_mm512_cvtepi64_pd`
- `_mm512_mask_cvtepi64_pd`
- `_mm512_maskz_cvtepi64_pd`
- `_mm512_cvtepu64_pd`
- `_mm512_mask_cvtepu64_pd`
- `_mm512_maskz_cvtepu64_pd`
This PR is part 2 [[part
1](https://github.com/llvm/llvm-project/pull/156187)] of a series of PRs
fixing #155798
Commit: f8f96a4d4e607b60579e88e7054dbdd544f861e6
https://github.com/llvm/llvm-project/commit/f8f96a4d4e607b60579e88e7054dbdd544f861e6
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
Log Message:
-----------
[flang][OpenMP] Rename variable `block` to `body`, NFC (#156702)
`block` is a global variable that represents the Block parser, so avoid
using local variables with the same name.
Commit: 13f97f013adbe7ad0ef2bf3634d14b6fccfae90d
https://github.com/llvm/llvm-project/commit/13f97f013adbe7ad0ef2bf3634d14b6fccfae90d
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
Log Message:
-----------
[flang][OpenMP] Simplify LooselyStructuredBlockParser, NFC (#156701)
Part of the logic in this parser was dealing with a list of executable
constructs that begins with BLOCK. Since after 6b92a3bc21cdc we're doing
it via a lookahead, this handling can be simplified.
Commit: bcb1a896d840ea31bab72d64e21ecda34a94d522
https://github.com/llvm/llvm-project/commit/bcb1a896d840ea31bab72d64e21ecda34a94d522
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
Log Message:
-----------
[NFC][IntrinsicEmitter] Include source location with enum definition (#156800)
Commit: 08fd349adff6cbbeb58107815d2aef5adeef6af0
https://github.com/llvm/llvm-project/commit/08fd349adff6cbbeb58107815d2aef5adeef6af0
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Log Message:
-----------
[NFC][MC][ARM] Reorder decoder functions 4/N (#156690)
Commit: c8e760e03b41a327b05b71ab76a120dc0927f6a5
https://github.com/llvm/llvm-project/commit/c8e760e03b41a327b05b71ab76a120dc0927f6a5
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[LLVM][MC][DecoderEmitter] Fail fatally if `Insn` and decoder table bitwidths mismatch (#156734)
Commit: 21532f008461c65438475c53444f33f185f9574f
https://github.com/llvm/llvm-project/commit/21532f008461c65438475c53444f33f185f9574f
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[NFC][MC][DecoderEmitter] Refactor code related to EncodingField (#156759)
Commit: faca9ddce6f9480ef1e768e1df6f9f95349d15ea
https://github.com/llvm/llvm-project/commit/faca9ddce6f9480ef1e768e1df6f9f95349d15ea
Author: Chaitanya Koparkar <ckoparkar at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/Headers/avx512vlintrin.h
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Headers][X86] Group related AVX512VL FMA intrinsics together (NFC) (#156794)
Follow-up of #156385.
Commit: 4931c3afc347f3ea099ebbe3d056dfc63e9eba45
https://github.com/llvm/llvm-project/commit/4931c3afc347f3ea099ebbe3d056dfc63e9eba45
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/cxx23.cpp
Log Message:
-----------
[clang][bytecode] Reject null pointers in CheckStore() (#156645)
In the attached test case, the global variable later only points to
gargbage, because the MaterializeTemporaryExpr used to initialize it is
a local variable, which is gone by the time we try to evaluate the
store.
Fixes #156223
Commit: 5520e16d2a5e2d233248be5a85f0cfe42fefef41
https://github.com/llvm/llvm-project/commit/5520e16d2a5e2d233248be5a85f0cfe42fefef41
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Parser/OpenMP/fail-construct1.f90
M flang/test/Parser/OpenMP/ordered-block-vs-standalone.f90
M flang/test/Semantics/OpenMP/missing-end-directive.f90
M flang/test/Semantics/OpenMP/ordered01.f90
Log Message:
-----------
[flang][OpenMP] Parse ORDERED as standalone when DEPEND/DOACROSS is p… (#156693)
…resent
The OpenMP spec 4.5-5.1 defines ORDERED as standalone when a DEPEND
clause is present (with either SOURCE or SINK as argument). The OpenMP
spec 5.2+ defines ORDERED as standalone when a DOACROSS clause is
present.
Commit: c6b6d859cf75b98f547c95e1bfac4be34fead5dc
https://github.com/llvm/llvm-project/commit/c6b6d859cf75b98f547c95e1bfac4be34fead5dc
Author: Sadiinso <32017313+SadiinsoSnowfall at users.noreply.github.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512fp16intrin.h
M clang/lib/Headers/avx512vlfp16intrin.h
Log Message:
-----------
[X86] make the set/r/4 intrinsics macros into functions (#156819)
Change the definitions of `_mm_setr_ph`, `_mm256_setr_ph` and `_mm512_setr_ph` to be functions instead of macros.
Resolves #156709
Commit: 1b47135c9da92a8de3ded888f709081ff599ce03
https://github.com/llvm/llvm-project/commit/1b47135c9da92a8de3ded888f709081ff599ce03
Author: Aleksandar Spasojevic <aleksandar.spasojevic at amd.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/MC/AMDGPU/gfx12_err.s
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_buffer_err.txt
Log Message:
-----------
[AMDGPU] Ensure positive InstOffset for buffer operations (#145504)
GFX12+ buffer ops require positive InstOffset per AMD hardware spec.
Modified assembler/disassembler to reject negative buffer offsets.
Commit: 9e755445f167af1b41fc0c64252789197b449981
https://github.com/llvm/llvm-project/commit/9e755445f167af1b41fc0c64252789197b449981
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/cxx03.cpp
Log Message:
-----------
[clang][bytecode] Create implicit variables for wider base types (#156658)
If we create an implicit local variable for a derived-to-base cast, we
still should allocate enough space for the entire derived type.
Fixes #156219
Commit: 36fb493b8f42b5585acf0a1ffd918eca202e5775
https://github.com/llvm/llvm-project/commit/36fb493b8f42b5585acf0a1ffd918eca202e5775
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/lib/StaticAnalyzer/Checkers/CallAndMessageChecker.cpp
M clang/test/Analysis/analyzer-enabled-checkers.c
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
Log Message:
-----------
[analyzer] Clean up bug types in CallAndMessageChecker (#156073)
In CallAndMessageChecker the initialization of bug types was highly
obfuscated (even compared to other `mutable std::unique_ptr` hacks).
This commit cleans up this situation and removes a totally superfluous
hidded 'modeling' sub-checker that did not have any role apart from
obstructing the normal initialization of bug types.
(Note that if we need to reintroduce CallAndMessageModeling in the
future, we can do it cleanly within the CheckerFamily framework, so we
wouldn't need to re-obfuscate the bug type initialization.)
This change is mostly non-functional, the only visible change is the
removal of the hidden modeling checker.
Commit: 5d13f2864de3f21e00f22056220ed1cc8127f491
https://github.com/llvm/llvm-project/commit/5d13f2864de3f21e00f22056220ed1cc8127f491
Author: Bhasawut Singhaphan <bhasawut at gmail.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
Log Message:
-----------
[Headers][X86] Allow AVX2/AVX512 integer min/max intrinsics to be used in constexpr (#156833)
Update the AVX2/AVX512 min/max integer intrinsics to be constexpr
compatible.
This PR is a follow-up to #156678. The AVX512 mask/maskz variants will
be addressed in the next follow-up.
Part of #153153.
Commit: cc220b1d55297b5939eb7eb197767a8b27aa71f8
https://github.com/llvm/llvm-project/commit/cc220b1d55297b5939eb7eb197767a8b27aa71f8
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M lldb/test/Shell/Process/UnsupportedLanguage.test
Log Message:
-----------
[lldb] Mark UnsupportedLanguage.test Unsupported on Windows
This is to fix buildbot fallout post #156729 without needing to revert the
original patch.
Commit: 9c1828f6e6c03bd9addc8b60498291a2f564e03b
https://github.com/llvm/llvm-project/commit/9c1828f6e6c03bd9addc8b60498291a2f564e03b
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M .ci/monolithic-linux.sh
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/runtime/instr.cpp
M bolt/test/link_fdata.py
A bolt/test/runtime/copy_file.py
M bolt/test/runtime/instrumentation-indirect-2.c
M bolt/test/timers.c
M clang-tools-extra/clang-reorder-fields/CMakeLists.txt
A clang-tools-extra/clang-reorder-fields/Designator.cpp
A clang-tools-extra/clang-reorder-fields/Designator.h
M clang-tools-extra/clang-reorder-fields/ReorderFieldsAction.cpp
M clang-tools-extra/clang-tidy/.clang-tidy
M clang-tools-extra/clang-tidy/fuchsia/MultipleInheritanceCheck.cpp
M clang-tools-extra/clang-tidy/modernize/MakeSmartPtrCheck.cpp
M clang-tools-extra/clang-tidy/modernize/MakeSmartPtrCheck.h
M clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
M clang-tools-extra/clang-tidy/readability/UppercaseLiteralSuffixCheck.cpp
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-reorder-fields/AggregatePartialInitialization.c
M clang-tools-extra/test/clang-reorder-fields/AggregatePartialInitialization.cpp
A clang-tools-extra/test/clang-reorder-fields/DesignatedInitializerList.c
A clang-tools-extra/test/clang-reorder-fields/DesignatedInitializerList.cpp
A clang-tools-extra/test/clang-reorder-fields/IdiomaticZeroInitializer.c
A clang-tools-extra/test/clang-reorder-fields/InitializerListExcessElements.c
M clang-tools-extra/test/clang-tidy/check_clang_tidy.py
A clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/stdfloat
M clang-tools-extra/test/clang-tidy/checkers/bugprone/unchecked-optional-access.cpp
M clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/make-shared.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/make-unique.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/container-size-empty.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-c23.c
A clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-cxx23.cpp
R clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-float16.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point-opencl-half.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-hexadecimal-floating-point.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-custom-list.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-ms.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/analyzer/checkers.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/JSONNodeDumper.h
M clang/include/clang/AST/Stmt.h
M clang/include/clang/AST/TextNodeDumper.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/LangOptions.def
M clang/include/clang/Basic/StmtNodes.td
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/Options.td
M clang/include/clang/Frontend/ASTUnit.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Scope.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/include/clang/StaticAnalyzer/Checkers/Checkers.td
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h
M clang/include/clang/Tooling/Tooling.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Disasm.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/Stmt.cpp
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/Analysis/CFG.cpp
M clang/lib/Analysis/LifetimeSafety.cpp
M clang/lib/Basic/LangOptions.cpp
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprComplex.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
M clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.h
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.h
M clang/lib/CIR/CodeGen/CIRGenValue.h
M clang/lib/CIR/Dialect/IR/CIRDataLayout.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIRMemorySlot.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCall.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
M clang/lib/CrossTU/CrossTranslationUnit.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineFormatter.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Headers/avx2intrin.h
M clang/lib/Headers/avx512bwintrin.h
M clang/lib/Headers/avx512dqintrin.h
M clang/lib/Headers/avx512fintrin.h
M clang/lib/Headers/avx512fp16intrin.h
M clang/lib/Headers/avx512vlbwintrin.h
M clang/lib/Headers/avx512vldqintrin.h
M clang/lib/Headers/avx512vlfp16intrin.h
M clang/lib/Headers/avx512vlintrin.h
M clang/lib/Headers/avxintrin.h
M clang/lib/Headers/emmintrin.h
M clang/lib/Headers/fmaintrin.h
M clang/lib/Headers/smmintrin.h
M clang/lib/Headers/xmmintrin.h
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/Scope.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaCXXScopeSpec.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaOpenACC.cpp
M clang/lib/Sema/SemaOpenACCClause.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTypeTraits.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterStmt.cpp
M clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt
M clang/lib/StaticAnalyzer/Checkers/CallAndMessageChecker.cpp
R clang/lib/StaticAnalyzer/Checkers/CastSizeChecker.cpp
M clang/lib/StaticAnalyzer/Core/MemRegion.cpp
M clang/lib/StaticAnalyzer/Frontend/ModelInjector.cpp
M clang/lib/Tooling/Syntax/BuildTree.cpp
M clang/lib/Tooling/Tooling.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx03.cpp
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/openmp.cpp
M clang/test/AST/ByteCode/vectors.cpp
M clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl
M clang/test/AST/HLSL/RootSignatures-AST.hlsl
M clang/test/AST/HLSL/StructuredBuffers-AST.hlsl
M clang/test/AST/HLSL/TypedBuffers-AST.hlsl
A clang/test/AST/ast-dump-labeled-break-continue.c
A clang/test/AST/ast-print-labeled-break-continue.c
M clang/test/Analysis/Malloc+MismatchedDeallocator+NewDelete.cpp
M clang/test/Analysis/Malloc+MismatchedDeallocator_intersections.cpp
M clang/test/Analysis/MismatchedDeallocator-checker-test.mm
M clang/test/Analysis/NewDelete-checker-test.cpp
M clang/test/Analysis/NewDelete-intersections.mm
M clang/test/Analysis/analyzer-enabled-checkers.c
R clang/test/Analysis/castsize.c
M clang/test/Analysis/cfg.c
A clang/test/Analysis/ctu-import-type-decl-definition.c
M clang/test/Analysis/malloc-annotations.c
M clang/test/Analysis/malloc-annotations.cpp
M clang/test/Analysis/malloc.c
M clang/test/Analysis/malloc.cpp
M clang/test/Analysis/misc-ps.m
A clang/test/Analysis/model-file-missing.cpp
A clang/test/Analysis/modules/explicit-templ-inst-crash-in-modules.cppm
M clang/test/Analysis/qt_malloc.cpp
M clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c
M clang/test/Analysis/unix-fns.c
A clang/test/CIR/CodeGen/builtins-elementwise.c
R clang/test/CIR/CodeGen/complex-arithmetic.cpp
A clang/test/CIR/CodeGen/complex-plus-minus.cpp
M clang/test/CIR/CodeGen/complex.cpp
A clang/test/CIR/CodeGen/mms-bitfields.c
M clang/test/CIR/CodeGen/statement-exprs.c
M clang/test/CIR/CodeGen/variable-decomposition.cpp
A clang/test/CIR/CodeGen/volatile.cpp
M clang/test/CIR/CodeGen/vtt.cpp
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.c
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause-templates.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
A clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-unsigned-int.c
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
A clang/test/CIR/IR/copy.cir
A clang/test/CIR/IR/invalid-copy.cir
M clang/test/CIR/Lowering/vtt-addrpoint.cir
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesd.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aese.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_aesmc.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bdep.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bext.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_bgrp.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullb_128.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_pmullt_128.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_sm4e.c
M clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_sm4ekey.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfadd.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmax.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmaxnm.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmin.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfminnm.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmla.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmls.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmul.c
M clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfsub.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics-constrained.c
M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
M clang/test/CodeGen/X86/avx-builtins.c
M clang/test/CodeGen/X86/avx2-builtins.c
M clang/test/CodeGen/X86/avx512bw-builtins.c
M clang/test/CodeGen/X86/avx512cd-builtins.c
M clang/test/CodeGen/X86/avx512dq-builtins.c
M clang/test/CodeGen/X86/avx512f-builtins.c
M clang/test/CodeGen/X86/avx512fp16-builtins.c
M clang/test/CodeGen/X86/avx512vl-builtins.c
M clang/test/CodeGen/X86/avx512vlbw-builtins.c
M clang/test/CodeGen/X86/avx512vlcd-builtins.c
M clang/test/CodeGen/X86/avx512vldq-builtins.c
M clang/test/CodeGen/X86/builtin_test_helpers.h
M clang/test/CodeGen/X86/mmx-builtins.c
M clang/test/CodeGen/X86/rot-intrinsics.c
M clang/test/CodeGen/X86/sse2-builtins.c
M clang/test/CodeGen/X86/sse41-builtins.c
M clang/test/CodeGen/X86/x86-builtins.c
M clang/test/CodeGen/X86/xop-builtins.c
M clang/test/CodeGen/attr-counted-by.c
A clang/test/CodeGen/complex_Float16.c
A clang/test/CodeGen/labeled-break-continue.c
M clang/test/CodeGen/union-tbaa1.c
A clang/test/CodeGenCXX/labeled-break-continue.cpp
M clang/test/CodeGenHLSL/builtins/isinf-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/isinf.hlsl
A clang/test/CodeGenHLSL/resources/res-array-global-subarray-many.hlsl
A clang/test/CodeGenHLSL/resources/res-array-global-subarray-one.hlsl
A clang/test/CodeGenObjC/labeled-break-continue.m
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-async-load-store-lds.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-cluster-load.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-cooperative-atomics.cl
M clang/test/DebugInfo/CXX/structured-binding.cpp
M clang/test/Driver/cl-options.c
M clang/test/Driver/print-supported-extensions-riscv.c
A clang/test/Modules/Inputs/umbrella_header_order/module.modulemap
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/A.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/B.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/C.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/D.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/E.h
A clang/test/Modules/Inputs/umbrella_header_order/umbrella/F.h
A clang/test/Modules/implicit-opt-level.c
M clang/test/Modules/safe_buffers_optout.cpp
A clang/test/Modules/umbrella_dir_order.m
M clang/test/OpenMP/declare_mapper_codegen.cpp
M clang/test/OpenMP/error_message.cpp
M clang/test/OpenMP/for_loop_messages.cpp
M clang/test/OpenMP/scan_messages.cpp
A clang/test/OpenMP/spirv_locstr.cpp
M clang/test/OpenMP/target_data_use_device_addr_codegen.cpp
M clang/test/OpenMP/target_has_device_addr_messages.cpp
M clang/test/OpenMP/task_in_reduction_message.cpp
M clang/test/OpenMP/taskgroup_task_reduction_messages.cpp
M clang/test/OpenMP/teams_reduction_messages.cpp
A clang/test/Parser/labeled-break-continue.c
M clang/test/Sema/Float16.c
M clang/test/Sema/__try.c
M clang/test/Sema/aarch64-sve2-intrinsics/acle_sve2_aes_bitperm_sha3_sm4.cpp
M clang/test/Sema/aarch64-sve2p1-intrinsics/acle_sve2p1_b16b16.cpp
M clang/test/Sema/fp16-sema.c
A clang/test/Sema/labeled-break-continue.c
M clang/test/Sema/riscv-fp16.c
M clang/test/Sema/warn-alloc-size.c
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
A clang/test/SemaCXX/GH156458.cpp
M clang/test/SemaCXX/constant-expression-p2280r4.cpp
A clang/test/SemaCXX/labeled-break-continue-constexpr.cpp
A clang/test/SemaCXX/labeled-break-continue.cpp
M clang/test/SemaCXX/lambda-expressions.cpp
A clang/test/SemaCXX/type-trait-synthesises-from-spaceship.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags-std.cpp
M clang/test/SemaCXX/type-traits-unsatisfied-diags.cpp
A clang/test/SemaObjC/labeled-break-continue.m
M clang/test/SemaOpenACC/combined-construct-copy-clause.cpp
M clang/test/SemaOpenACC/combined-construct-copyin-clause.cpp
M clang/test/SemaOpenACC/combined-construct-copyout-clause.cpp
M clang/test/SemaOpenACC/combined-construct-create-clause.cpp
M clang/test/SemaOpenACC/combined-construct-firstprivate-clause.cpp
M clang/test/SemaOpenACC/combined-construct-no_create-clause.cpp
M clang/test/SemaOpenACC/combined-construct-present-clause.cpp
M clang/test/SemaOpenACC/combined-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/compute-construct-copy-clause.cpp
M clang/test/SemaOpenACC/compute-construct-copyin-clause.cpp
M clang/test/SemaOpenACC/compute-construct-copyout-clause.cpp
M clang/test/SemaOpenACC/compute-construct-create-clause.cpp
M clang/test/SemaOpenACC/compute-construct-firstprivate-clause.cpp
M clang/test/SemaOpenACC/compute-construct-no_create-clause.cpp
M clang/test/SemaOpenACC/compute-construct-present-clause.cpp
M clang/test/SemaOpenACC/compute-construct-private-clause.cpp
M clang/test/SemaOpenACC/compute-construct-reduction-clause.c
M clang/test/SemaOpenACC/compute-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/loop-construct-reduction-clause.cpp
M clang/test/SemaOpenACC/no-branch-in-out.c
A clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-cooperative-atomics.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
M clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestTableGen.cpp
M clang/unittests/Sema/HeuristicResolverTest.cpp
M clang/utils/TableGen/ClangSACheckersEmitter.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/www/c_status.html
M clang/www/features.html
M compiler-rt/lib/asan/asan_malloc_win.cpp
M compiler-rt/lib/builtins/crtbegin.c
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
M compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
M compiler-rt/test/asan/TestCases/Windows/heaprealloc_alloc_zero.cpp
A compiler-rt/test/asan/TestCases/Windows/rtlallocateheap_realloc_in_place.cpp
M compiler-rt/test/asan/TestCases/zero_alloc.cpp
M compiler-rt/test/msan/zero_alloc.cpp
M cross-project-tests/debuginfo-tests/dexter/dex/command/ParseCommand.py
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DAP.py
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/DebuggerControllers/ConditionalController.py
M cross-project-tests/debuginfo-tests/dexter/dex/debugger/lldb/LLDB.py
M cross-project-tests/debuginfo-tests/dexter/dex/tools/test/Tool.py
A cross-project-tests/debuginfo-tests/dexter/feature_tests/commands/control/dex-continue.cpp
A cross-project-tests/debuginfo-tests/dexter/feature_tests/commands/control/dex_step_function.cpp
M flang-rt/lib/runtime/CMakeLists.txt
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Runtime/freestanding-tools.h
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/ConvertConstant.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-call.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/compute-offsets.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/symbol.cpp
M flang/test/Driver/atomic-control-options.f90
M flang/test/Parser/OpenMP/fail-construct1.f90
M flang/test/Parser/OpenMP/ordered-block-vs-standalone.f90
M flang/test/Semantics/OpenMP/missing-end-directive.f90
M flang/test/Semantics/OpenMP/ordered01.f90
M flang/test/Semantics/bind-c01.f90
M flang/test/Semantics/cuf-device-procedures01.cuf
A flang/test/Semantics/global03.f90
A flang/test/Semantics/offsets05.f90
M flang/test/Semantics/reduce01.f90
M flang/test/Transforms/debug-allocatable-1.fir
M flang/test/Transforms/debug-assumed-rank-array.fir
M flang/test/Transforms/debug-assumed-shape-array-2.fir
M flang/test/Transforms/debug-assumed-shape-array.fir
M flang/test/Transforms/debug-ptr-type.fir
A flang/test/Transforms/dummy-procedure-common-block-name.f
M flang/tools/f18/CMakeLists.txt
M libc/cmake/modules/LLVMLibCLibraryRules.cmake
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/baremetal/riscv/entrypoints.txt
M libc/config/darwin/aarch64/entrypoints.txt
M libc/config/darwin/x86_64/entrypoints.txt
M libc/config/gpu/amdgpu/entrypoints.txt
M libc/config/gpu/nvptx/entrypoints.txt
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/windows/entrypoints.txt
M libc/docs/headers/math/index.rst
M libc/docs/headers/time.rst
A libc/hdr/localtime_overlay.h
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/dl_info.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/math.yaml
M libc/include/time.yaml
M libc/src/__support/CPP/CMakeLists.txt
M libc/src/__support/CPP/algorithm.h
A libc/src/__support/CPP/simd.h
M libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/macros/attributes.h
M libc/src/__support/macros/properties/cpu_features.h
M libc/src/__support/threads/thread.cpp
M libc/src/__support/threads/thread.h
M libc/src/dlfcn/CMakeLists.txt
M libc/src/dlfcn/dladdr.cpp
M libc/src/dlfcn/dladdr.h
M libc/src/math/CMakeLists.txt
A libc/src/math/atanpif16.h
A libc/src/math/fmodbf16.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/atanpif16.cpp
A libc/src/math/generic/fmodbf16.cpp
M libc/src/stdlib/exit.cpp
M libc/src/string/CMakeLists.txt
A libc/src/string/memory_utils/generic/inline_strlen.h
M libc/src/string/string_utils.h
M libc/src/time/CMakeLists.txt
M libc/src/time/baremetal/CMakeLists.txt
A libc/src/time/baremetal/localtime.cpp
A libc/src/time/baremetal/localtime_r.cpp
A libc/src/time/localtime.cpp
A libc/src/time/localtime.h
A libc/src/time/localtime_r.cpp
A libc/src/time/localtime_r.h
M libc/src/time/time_utils.h
M libc/test/integration/src/__support/threads/CMakeLists.txt
A libc/test/integration/src/__support/threads/double_exit_test.cpp
A libc/test/integration/src/__support/threads/main_exit_test.cpp
M libc/test/src/math/CMakeLists.txt
A libc/test/src/math/atanpif16_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/fmodbf16_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/FModTest.h
A libc/test/src/math/smoke/atanpif16_test.cpp
A libc/test/src/math/smoke/fmodbf16_test.cpp
M libc/test/src/string/strcspn_test.cpp
M libc/test/src/string/strpbrk_test.cpp
M libc/test/src/string/strsep_test.cpp
M libc/test/src/string/strspn_test.cpp
M libc/test/src/string/strtok_r_test.cpp
M libc/test/src/string/strtok_test.cpp
M libc/test/src/time/CMakeLists.txt
A libc/test/src/time/localtime_r_test.cpp
A libc/test/src/time/localtime_test.cpp
M libc/utils/MPFRWrapper/MPCommon.cpp
M libc/utils/MPFRWrapper/MPCommon.h
M libc/utils/MPFRWrapper/MPFRUtils.cpp
M libc/utils/MPFRWrapper/MPFRUtils.h
M libclc/clc/include/clc/clc_convert.h
R libclc/clc/include/clc/clcmacro.h
M libclc/clc/include/clc/mem_fence/clc_mem_fence.h
A libclc/clc/include/clc/mem_fence/clc_mem_semantic.h
M libclc/clc/include/clc/synchronization/clc_work_group_barrier.h
M libclc/clc/lib/amdgcn/math/clc_ldexp_override.cl
M libclc/clc/lib/amdgcn/mem_fence/clc_mem_fence.cl
M libclc/clc/lib/amdgcn/synchronization/clc_work_group_barrier.cl
M libclc/clc/lib/amdgpu/math/clc_native_exp2.cl
M libclc/clc/lib/amdgpu/math/clc_sqrt_fp64.cl
M libclc/clc/lib/clspv/math/clc_sw_fma.cl
M libclc/clc/lib/generic/common/clc_degrees.cl
M libclc/clc/lib/generic/common/clc_radians.cl
M libclc/clc/lib/generic/common/clc_smoothstep.cl
M libclc/clc/lib/generic/common/clc_step.cl
M libclc/clc/lib/generic/integer/clc_clz.cl
M libclc/clc/lib/generic/integer/clc_ctz.cl
M libclc/clc/lib/generic/integer/clc_mad_sat.cl
M libclc/clc/lib/generic/math/clc_cbrt.cl
M libclc/clc/lib/generic/math/clc_cos.cl
M libclc/clc/lib/generic/math/clc_exp10.cl
M libclc/clc/lib/generic/math/clc_fmod.cl
M libclc/clc/lib/generic/math/clc_fract.cl
M libclc/clc/lib/generic/math/clc_frexp.inc
M libclc/clc/lib/generic/math/clc_hypot.cl
M libclc/clc/lib/generic/math/clc_ilogb.cl
M libclc/clc/lib/generic/math/clc_ldexp.cl
M libclc/clc/lib/generic/math/clc_lgamma_r.cl
M libclc/clc/lib/generic/math/clc_log.cl
M libclc/clc/lib/generic/math/clc_log10.cl
M libclc/clc/lib/generic/math/clc_log2.cl
M libclc/clc/lib/generic/math/clc_logb.cl
M libclc/clc/lib/generic/math/clc_nextafter.cl
M libclc/clc/lib/generic/math/clc_pow.cl
M libclc/clc/lib/generic/math/clc_pown.cl
M libclc/clc/lib/generic/math/clc_powr.cl
M libclc/clc/lib/generic/math/clc_remainder.cl
M libclc/clc/lib/generic/math/clc_remquo.cl
M libclc/clc/lib/generic/math/clc_sin.cl
M libclc/clc/lib/generic/math/clc_sw_fma.cl
M libclc/clc/lib/generic/relational/clc_bitselect.cl
M libclc/clc/lib/ptx-nvidiacl/mem_fence/clc_mem_fence.cl
M libclc/clc/lib/ptx-nvidiacl/synchronization/clc_work_group_barrier.cl
M libclc/clc/lib/r600/math/clc_native_rsqrt.cl
M libclc/clc/lib/r600/math/clc_rsqrt_override.cl
M libclc/clc/lib/spirv/math/clc_fmax.cl
M libclc/clc/lib/spirv/math/clc_fmin.cl
M libclc/opencl/include/clc/opencl/synchronization/utils.h
M libclc/opencl/lib/amdgcn/mem_fence/fence.cl
M libclc/opencl/lib/amdgcn/synchronization/barrier.cl
M libclc/opencl/lib/generic/common/sign.cl
M libclc/opencl/lib/generic/common/smoothstep.cl
M libclc/opencl/lib/generic/math/atan2.cl
M libclc/opencl/lib/generic/math/atan2pi.cl
M libclc/opencl/lib/generic/math/log.cl
M libclc/opencl/lib/generic/math/log10.cl
M libclc/opencl/lib/generic/math/log2.cl
M libclc/opencl/lib/generic/math/nan.cl
M libclc/opencl/lib/ptx-nvidiacl/mem_fence/fence.cl
M libclc/opencl/lib/ptx-nvidiacl/synchronization/barrier.cl
M libcxx/CMakeLists.txt
M libcxx/docs/ABIGuarantees.rst
M libcxx/docs/Modules.rst
M libcxx/docs/ReleaseNotes/22.rst
M libcxx/docs/Status/Cxx17Papers.csv
M libcxx/docs/Status/Cxx20Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__algorithm/simd_utils.h
M libcxx/include/__atomic/atomic.h
M libcxx/include/__config
M libcxx/include/__configuration/abi.h
M libcxx/include/__configuration/availability.h
M libcxx/include/__cxx03/__config
M libcxx/include/__cxx03/bitset
M libcxx/include/__cxx03/forward_list
M libcxx/include/__cxx03/list
M libcxx/include/__functional/function.h
M libcxx/include/__fwd/tuple.h
M libcxx/include/__iterator/back_insert_iterator.h
M libcxx/include/__iterator/bounded_iter.h
M libcxx/include/__iterator/concepts.h
M libcxx/include/__iterator/front_insert_iterator.h
M libcxx/include/__iterator/insert_iterator.h
M libcxx/include/__iterator/istream_iterator.h
M libcxx/include/__iterator/istreambuf_iterator.h
M libcxx/include/__iterator/iterator.h
M libcxx/include/__iterator/ostream_iterator.h
M libcxx/include/__iterator/ostreambuf_iterator.h
M libcxx/include/__iterator/reverse_iterator.h
M libcxx/include/__math/hypot.h
M libcxx/include/__memory/compressed_pair.h
M libcxx/include/__memory/raw_storage_iterator.h
M libcxx/include/__ranges/as_rvalue_view.h
M libcxx/include/__tree
R libcxx/include/__tuple/make_tuple_types.h
M libcxx/include/__tuple/tuple_element.h
M libcxx/include/__tuple/tuple_like_ext.h
M libcxx/include/__tuple/tuple_size.h
M libcxx/include/__type_traits/invoke.h
M libcxx/include/__vector/vector_bool.h
M libcxx/include/map
M libcxx/include/module.modulemap.in
M libcxx/include/mutex
M libcxx/include/set
M libcxx/include/string
M libcxx/include/string_view
M libcxx/include/tuple
M libcxx/src/atomic.cpp
M libcxx/src/experimental/tzdb.cpp
A libcxx/test/extensions/clang/thread/thread.mutex/lock.verify.cpp
M libcxx/test/extensions/posix/xopen_source.gen.py
M libcxx/test/libcxx-03/containers/associative/reference_comparator_abi.compile.pass.cpp
M libcxx/test/libcxx-03/iterators/contiguous_iterators.verify.cpp
M libcxx/test/libcxx-03/numerics/complex.number/cmplx.over.pow.pass.cpp
M libcxx/test/libcxx-03/vendor/apple/disable-availability.sh.cpp
M libcxx/test/libcxx/algorithms/alg.modifying.operations/copy_move_nontrivial.pass.cpp
M libcxx/test/libcxx/algorithms/callable-requirements-rvalue.compile.pass.cpp
M libcxx/test/libcxx/atomics/atomics.syn/wait.issue_85107.pass.cpp
M libcxx/test/libcxx/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
M libcxx/test/libcxx/containers/associative/map/abi.compile.pass.cpp
M libcxx/test/libcxx/containers/associative/reference_comparator_abi.compile.pass.cpp
M libcxx/test/libcxx/containers/associative/unord.map/abi.compile.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.multiset/insert.temporary.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.multiset/insert_range.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.set/insert.temporary.pass.cpp
M libcxx/test/libcxx/containers/container.adaptors/flat.set/insert_range.pass.cpp
M libcxx/test/libcxx/containers/strings/basic.string/asan_turning_off.pass.cpp
M libcxx/test/libcxx/containers/views/mdspan/layout_left/assert.ctor.layout_stride.pass.cpp
M libcxx/test/libcxx/containers/views/mdspan/layout_right/assert.ctor.layout_stride.pass.cpp
M libcxx/test/libcxx/input.output/iostream.format/output.streams/ostream.syn/includes.compile.pass.cpp
M libcxx/test/libcxx/iterators/contiguous_iterators.verify.cpp
M libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp
A libcxx/test/libcxx/utilities/tuple/abi.compile.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_piecewise_pair.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_from_underaligned_buffer.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_in_geometric_progression.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/mem.res.pool/unsynchronized_buffer.pass.cpp
M libcxx/test/libcxx/utilities/utility/mem.res/pmr.availability.verify.cpp
M libcxx/test/libcxx/vendor/apple/disable-availability.sh.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_backward.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/ranges.copy_backward.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.count/ranges.count.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/equal.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/ranges.equal.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/ranges.find.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/assign.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_strong.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/compare_exchange_weak.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/ctor.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/exchange.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_add.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/fetch_sub.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/lockfree.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_all.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/notify_one.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.float.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.minus_equals.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/operator.plus_equals.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/store.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/wait.pass.cpp
M libcxx/test/std/containers/associative/map/map.modifiers/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/associative/set/insert_iter_iter.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.cons/move_assign_noexcept.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.map/flat.map.erasure/erase_if_exceptions.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.cons/move_assign_noexcept.compile.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.multimap/flat.multimap.erasure/erase_if_exceptions.pass.cpp
M libcxx/test/std/containers/container.adaptors/flat.set/flat.set.erasure/erase_if_exceptions.pass.cpp
M libcxx/test/std/containers/sequences/deque/deque.cons/from_range.pass.cpp
M libcxx/test/std/containers/sequences/forwardlist/types.pass.cpp
M libcxx/test/std/containers/sequences/list/types.pass.cpp
M libcxx/test/std/containers/sequences/vector.bool/shrink_to_fit.pass.cpp
M libcxx/test/std/containers/sequences/vector.bool/small_allocator_size.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.capacity/shrink_to_fit.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.cons/construct_iter_iter.pass.cpp
M libcxx/test/std/containers/sequences/vector/vector.cons/construct_iter_iter_alloc.pass.cpp
M libcxx/test/std/containers/views/mdspan/mdspan/conversion.pass.cpp
M libcxx/test/std/containers/views/views.span/span.cons/copy.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcode/syserr.errcode.constructors/lwg3629.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcode/syserr.errcode.modifiers/lwg3629.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcondition/syserr.errcondition.constructors/lwg3629.pass.cpp
M libcxx/test/std/diagnostics/syserr/syserr.errcondition/syserr.errcondition.modifiers/lwg3629.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/filebuf.assign/nonmember_swap_min.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/filebuf.virtuals/setbuf.pass.cpp
M libcxx/test/std/input.output/iostream.format/print.fun/includes.compile.pass.cpp
M libcxx/test/std/input.output/iostreams.base/ios.base/ios.types/ios_Init/ios_Init.global.pass.cpp
M libcxx/test/std/input.output/string.streams/istringstream/istringstream.members/str.allocator_propagation.pass.cpp
M libcxx/test/std/input.output/string.streams/ostringstream/ostringstream.members/str.allocator_propagation.pass.cpp
M libcxx/test/std/input.output/string.streams/stringstream/stringstream.members/str.allocator_propagation.pass.cpp
M libcxx/test/std/iterators/iterator.requirements/indirectcallable/indirectinvocable/indirect_result_t.compile.pass.cpp
M libcxx/test/std/numerics/c.math/cmath.pass.cpp
M libcxx/test/std/numerics/complex.number/complex.special/gh_101960_ambiguous_ctor.pass.cpp
M libcxx/test/std/numerics/complex.number/complex/bit_cast.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.lcm/lcm.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.as.rvalue/adaptor.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.lazy.split/types.h
M libcxx/test/std/ranges/range.factories/range.iota.view/size.pass.cpp
M libcxx/test/std/ranges/range.req/range.view/enable_view.compile.pass.cpp
M libcxx/test/std/ranges/ranges_robust_against_no_unique_address.pass.cpp
M libcxx/test/std/strings/basic.string/string.capacity/shrink_to_fit.pass.cpp
M libcxx/test/std/strings/basic.string/string.nonmembers/string_op+/string.string_view.pass.cpp
M libcxx/test/std/thread/futures/futures.task/futures.task.members/type.verify.cpp
M libcxx/test/std/thread/thread.jthread/join.deadlock.pass.cpp
M libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.id/cmp.pass.cpp
M libcxx/test/std/time/time.duration/time.duration.nonmember/ostream.pass.cpp
M libcxx/test/std/time/time.syn/formatter.duration.pass.cpp
M libcxx/test/std/utilities/allocator.adaptor/allocator.adaptor.cnstr/allocs.pass.cpp
M libcxx/test/std/utilities/allocator.adaptor/base-is-uglified.compile.pass.cpp
M libcxx/test/std/utilities/expected/expected.expected/ctor/ctor.copy.pass.cpp
M libcxx/test/std/utilities/expected/expected.expected/observers/has_value.pass.cpp
M libcxx/test/std/utilities/expected/types.h
M libcxx/test/std/utilities/format/format.functions/bug_81590.compile.pass.cpp
M libcxx/test/std/utilities/format/format.functions/format_tests.h
M libcxx/test/std/utilities/memory/allocator.uses/allocator.uses.construction/uses_allocator_construction_args.pass.cpp
M libcxx/test/std/utilities/memory/pointer.conversion/to_address.pass.cpp
M libcxx/test/std/utilities/memory/specialized.algorithms/overload_compare_iterator.h
M libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/ranges_destroy_at.pass.cpp
M libcxx/test/std/utilities/memory/util.smartptr/util.smartptr.weak/util.smartptr.weak.const/pr40459.pass.cpp
M libcxx/test/std/utilities/meta/meta.rel/is_convertible.pass.cpp
M libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.compile.pass.cpp
M libcxx/test/std/utilities/optional/optional.object/optional.object.ctor/gh_101960_internal_ctor.compile.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.cons/char_ptr_ctor.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/index_const.pass.cpp
M libcxx/test/std/utilities/template.bitset/bitset.members/nonstdmem.uglified.compile.pass.cpp
M libcxx/test/std/utilities/tuple/tuple.tuple/tuple.creation/tuple_cat.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.class.general/equality.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/assign.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/copy.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/default.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/memory_resource_convert.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.ctor/other_alloc.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.eq/equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.eq/not_equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/allocate_deallocate_bytes.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/allocate_deallocate_object.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair_const_lvalue_pair.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair_rvalue.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_pair_values.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_piecewise_pair.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_piecewise_pair_evil.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/construct_types.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/deallocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/destroy.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/new_delete_object.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.poly.allocator.class/mem.poly.allocator.mem/select_on_container_copy_construction.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_deque_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_deque_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_forward_list_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_list_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_list_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_map_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_map_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_regex_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_set_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_set_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_string_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_string_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_map_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_map_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_set_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_unordered_set_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_vector_synop.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.aliases/header_vector_synop2.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.global/default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.global/new_delete_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.global/null_memory_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.ctor/copy_move.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.ctor/with_default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.ctor/without_buffer.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_deallocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_exception_safety.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_from_initial_buffer.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_from_zero_sized_buffer.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_in_geometric_progression.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_overaligned_request.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_with_initial_size.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/equality.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.ctor/ctor_does_not_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.ctor/sync_with_default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.ctor/unsync_with_default_resource.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/equality.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_overaligned_request.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_reuse_blocks.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_deallocate_matches_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_overaligned_request.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_reuse_blocks.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_deallocate_matches_allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/construct.verify.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.eq/equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.eq/not_equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.private/private_members.verify.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.private/protected_members.verify.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/allocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/deallocate.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/dtor.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/mem.res/mem.res.public/is_equal.pass.cpp
M libcxx/test/std/utilities/utility/mem.res/nodiscard.verify.cpp
M libcxx/test/std/utilities/utility/pairs/pairs.pair/ctor.pair_like.pass.cpp
M libcxx/test/std/utilities/variant/variant.variant/variant.ctor/T.pass.cpp
M libcxx/test/std/utilities/variant/variant.visit.member/visit_return_type.pass.cpp
M libcxx/test/std/utilities/variant/variant.visit/visit_return_type.pass.cpp
M libcxx/test/support/is_transparent.h
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/libcxx/test/features.py
M libunwind/src/DwarfParser.hpp
A libunwind/test/eh_frame_fde_pc_range.pass.cpp
M lld/MachO/Driver.cpp
M lld/test/COFF/color-diagnostics.test
M lld/test/COFF/linkrepro-res.test
M lld/test/COFF/linkrepro.test
M lld/test/COFF/lto-cache-warnings.ll
M lld/test/COFF/reloc-discarded.s
M lld/test/ELF/arm-exidx-range.s
M lld/test/ELF/color-diagnostics.test
M lld/test/ELF/file-access.s
M lld/test/ELF/linkerscript/invalid.test
M lld/test/ELF/lto/cache-warnings.ll
M lld/test/ELF/lto/comdat-nodeduplicate.ll
M lld/test/ELF/lto/resolution-err.ll
M lld/test/ELF/msp430.s
M lld/test/ELF/weak-shared-gc.s
M lld/test/ELF/weak-undef-lib.s
M lld/test/MachO/cgdata-generate-merge.s
M lld/test/MachO/cgdata-generate.s
M lld/test/MachO/color-diagnostics.test
M lld/test/MachO/framework.s
M lld/test/MachO/implicit-and-allowable-clients.test
M lld/test/MachO/link-search-at-loader-path-symlink.s
M lld/test/MachO/lto-cache-warnings.ll
A lld/test/MachO/read-workers.s
M lld/test/MachO/reexport-with-symlink.s
M lld/test/MachO/reexport-without-rpath.s
M lld/test/MachO/reproduce.s
M lld/test/MachO/stabs.s
M lld/test/MachO/tapi-rpath.s
M lld/test/lit.cfg.py
M lld/test/wasm/lto/cache-warnings.ll
M lld/test/wasm/reproduce.s
M lldb/include/lldb/API/SBFrame.h
M lldb/include/lldb/Core/Disassembler.h
M lldb/include/lldb/Core/FormatEntity.h
M lldb/include/lldb/Host/File.h
M lldb/include/lldb/Target/CoreFileMemoryRanges.h
M lldb/include/lldb/Target/StackFrame.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py
M lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py
M lldb/source/API/SBFrame.cpp
M lldb/source/Commands/Options.td
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Host/common/File.cpp
M lldb/source/Host/windows/Host.cpp
M lldb/source/Plugins/DynamicLoader/Windows-DYLD/DynamicLoaderWindowsDYLD.h
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
M lldb/source/Plugins/Process/scripted/ScriptedThread.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/StackFrameList.cpp
M lldb/test/API/functionalities/scripted_process/TestScriptedProcess.py
M lldb/test/API/python_api/basename/TestGetBaseName.py
M lldb/test/API/riscv/step/TestSoftwareStep.py
M lldb/test/API/riscv/step/branch.c
M lldb/test/API/riscv/step/incomplete_sequence_without_lr.c
M lldb/test/API/riscv/step/incomplete_sequence_without_sc.c
M lldb/test/API/riscv/step/main.c
M lldb/test/API/tools/lldb-dap/launch/TestDAP_launch.py
A lldb/test/API/windows/launch/replace-dll/Makefile
A lldb/test/API/windows/launch/replace-dll/TestReplaceDLL.py
A lldb/test/API/windows/launch/replace-dll/bar.c
A lldb/test/API/windows/launch/replace-dll/foo.c
A lldb/test/API/windows/launch/replace-dll/test.c
M lldb/test/Shell/Process/Optimization.test
M lldb/test/Shell/Process/UnsupportedLanguage.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/app_specific_backtrace_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_arm64_register.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_json.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/interactive_crashlog_legacy.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/last_exception_backtrace_crashlog.test
M lldb/test/Shell/ScriptInterpreter/Python/Crashlog/skipped_status_interactive_crashlog.test
M lldb/test/Shell/Settings/TestFrameFormatFunctionReturnObjC.test
M lldb/test/Shell/SymbolFile/DWARF/dwo-missing-error.test
M lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test
A lldb/test/Shell/SymbolFile/DWARF/objcxx-forward-decls.test
M lldb/test/Shell/SymbolFile/NativePDB/Inputs/incomplete-tag-type.cpp
R lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.cpp
A lldb/test/Shell/SymbolFile/NativePDB/incomplete-tag-type.test
M lldb/test/Shell/lit.cfg.py
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/Handler/InitializeRequestHandler.cpp
M lldb/tools/lldb-dap/Options.td
M lldb/tools/lldb-dap/tool/lldb-dap.cpp
M lldb/unittests/Core/FormatEntityTest.cpp
M lldb/unittests/DAP/DAPTest.cpp
M lldb/unittests/DAP/TestBase.cpp
M llvm/CMakeLists.txt
M llvm/Maintainers.md
R llvm/clang/test/Modules/implicit-opt-level.c
M llvm/cmake/modules/GetHostTriple.cmake
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/cmake/modules/LLVMExternalProjectUtils.cmake
M llvm/docs/AddingConstrainedIntrinsics.rst
M llvm/docs/BigEndianNEON.rst
M llvm/docs/BranchWeightMetadata.rst
M llvm/docs/CMake.rst
M llvm/docs/CodeGenerator.rst
A llvm/docs/DebuggingLLVM.rst
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/GettingStartedTutorials.rst
M llvm/docs/GitHub.rst
M llvm/docs/LangRef.rst
M llvm/docs/ProgrammersManual.rst
M llvm/include/llvm/ADT/APInt.h
M llvm/include/llvm/ADT/BitVector.h
M llvm/include/llvm/ADT/DenseMap.h
M llvm/include/llvm/ADT/PointerEmbeddedInt.h
M llvm/include/llvm/ADT/PointerUnion.h
M llvm/include/llvm/ADT/PriorityWorklist.h
M llvm/include/llvm/ADT/StringMap.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/MemoryBuiltins.h
M llvm/include/llvm/Analysis/TargetLibraryInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ExpandFp.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/Passes.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/Debuginfod/Debuginfod.h
M llvm/include/llvm/Debuginfod/HTTPServer.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/DataLayout.h
M llvm/include/llvm/IR/FixedMetadataKinds.def
M llvm/include/llvm/IR/GEPNoWrapFlags.h
M llvm/include/llvm/IR/GlobalVariable.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/RuntimeLibcalls.h
M llvm/include/llvm/MC/MCDecoder.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/ProfileData/MemProfYAML.h
M llvm/include/llvm/Support/TypeSize.h
M llvm/include/llvm/Support/YAMLTraits.h
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/Target/TargetLoweringObjectFile.h
M llvm/include/llvm/Target/TargetSelectionDAG.td
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/DevelopmentModeInlineAdvisor.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemoryBuiltins.cpp
M llvm/lib/Analysis/MemoryLocation.cpp
M llvm/lib/Analysis/MemorySSAUpdater.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ExpandFp.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/InterleavedAccessPass.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
M llvm/lib/CodeGen/ReachingDefAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetInstrInfo.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Debuginfod/Debuginfod.cpp
M llvm/lib/Debuginfod/HTTPServer.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/Attributes.cpp
M llvm/lib/IR/DataLayout.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/ObjCopy/COFF/COFFObject.cpp
M llvm/lib/ObjCopy/COFF/COFFObject.h
M llvm/lib/ObjCopy/COFF/COFFWriter.cpp
M llvm/lib/ObjCopy/COFF/COFFWriter.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DebugOptions.h
M llvm/lib/Support/TypeSize.cpp
M llvm/lib/Support/Unix/Threading.inc
M llvm/lib/Target/AArch64/AArch64BranchTargets.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AArch64/SVEInstrFormats.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/EvergreenInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/R600Instructions.td
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPDInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARC/ARCInstrFormats.td
M llvm/lib/Target/ARC/ARCInstrInfo.td
M llvm/lib/Target/ARM/ARMBlockPlacement.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrFormats.td
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstrNEON.td
M llvm/lib/Target/ARM/ARMInstrThumb.td
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
M llvm/lib/Target/ARM/MVETailPredication.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchTargetTransformInfo.cpp
M llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
M llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
M llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
M llvm/lib/Target/Mips/Mips16ISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCInstrMMA.td
M llvm/lib/Target/PowerPC/PPCInstrP10.td
M llvm/lib/Target/PowerPC/PPCInstrVSX.td
M llvm/lib/Target/PowerPC/README_P9.txt
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/Sparc/SparcISelLowering.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.td
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/TargetLoweringObjectFile.cpp
M llvm/lib/Target/VE/VEInstrInfo.td
M llvm/lib/Target/VE/VEInstrVec.td
M llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/InferAlignment.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Utils/IRNormalizer.cpp
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
M llvm/lib/Transforms/Vectorize/VPlanValue.h
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Analysis/BasicAA/scalable-dse-aa.ll
M llvm/test/Analysis/CostModel/AArch64/shuffle-extract.ll
A llvm/test/Analysis/CostModel/AArch64/sve-vls-shuffle-extract.ll
M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
M llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info-apply-to-adds.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-apply-to-adds.ll
R llvm/test/Analysis/ScalarEvolution/zext-signed-addrec.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
A llvm/test/CodeGen/AArch64/GlobalISel/split-wide-shifts-multiway.ll
A llvm/test/CodeGen/AArch64/alias_mask.ll
A llvm/test/CodeGen/AArch64/alias_mask_nosve.ll
A llvm/test/CodeGen/AArch64/alias_mask_scalable.ll
A llvm/test/CodeGen/AArch64/alias_mask_scalable_nosve2.ll
M llvm/test/CodeGen/AArch64/alloca-oversized.ll
M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
M llvm/test/CodeGen/AArch64/atomic-ops-msvc.ll
M llvm/test/CodeGen/AArch64/atomic-ops.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
M llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
A llvm/test/CodeGen/AArch64/bti-ehpad.ll
M llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
M llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll
M llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
A llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
A llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll
M llvm/test/CodeGen/AArch64/fp16_intrinsic_vector_1op.ll
A llvm/test/CodeGen/AArch64/scalable_masked_deinterleaved_loads.ll
M llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
A llvm/test/CodeGen/AArch64/sme-streaming-mode-landingpads.ll
M llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir
M llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-index-const-step-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-imm.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
M llvm/test/CodeGen/AArch64/sve-unaligned-load-store-strict-align.ll
M llvm/test/CodeGen/AArch64/sve2-intrinsics-sm4.ll
A llvm/test/CodeGen/AArch64/wineh-bti-funclet.ll
M llvm/test/CodeGen/AArch64/wineh-bti.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-packed.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if.xfail.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/a-v-ds-atomic-cmpxchg.ll
M llvm/test/CodeGen/AMDGPU/amdgcn-call-whole-wave.ll
M llvm/test/CodeGen/AMDGPU/andorn2.ll
M llvm/test/CodeGen/AMDGPU/anyext.ll
M llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
M llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir
M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
M llvm/test/CodeGen/AMDGPU/bitop3.ll
M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-select.ll
M llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
A llvm/test/CodeGen/AMDGPU/ds_permute_a_v.ll
A llvm/test/CodeGen/AMDGPU/ds_write2_a_v.ll
M llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll
M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/gfx1250-no-scope-cu-stores.ll
M llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
M llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll
M llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
M llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll
M llvm/test/CodeGen/AMDGPU/lds-initializer.ll
A llvm/test/CodeGen/AMDGPU/lds-size-pal-metadata.ll
M llvm/test/CodeGen/AMDGPU/liveness.mir
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-agent.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-basic.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-singlethread.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-system.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-wavefront.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cooperative.atomic-workgroup.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.nxv2i32.fail.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.unreachable.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
A llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-cse-ssa.mir
A llvm/test/CodeGen/AMDGPU/memory-legalizer-barriers.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
M llvm/test/CodeGen/AMDGPU/private-memory-atomics.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
M llvm/test/CodeGen/AMDGPU/rename-disconnected-bug.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx90a.ll
A llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.gfx950.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-misched-max-waves.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
A llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll
M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/ARM/atomic-cmpxchg.ll
M llvm/test/CodeGen/ARM/bswap-inline-asm.ll
M llvm/test/CodeGen/ARM/cmpxchg-idioms.ll
M llvm/test/CodeGen/ARM/cmpxchg-weak.ll
M llvm/test/CodeGen/ARM/fp16-promote.ll
M llvm/test/CodeGen/ARM/stack-guard-nomovt.ll
M llvm/test/CodeGen/Hexagon/atomic-opaque-basic.ll
M llvm/test/CodeGen/LoongArch/bittest.ll
M llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
M llvm/test/CodeGen/LoongArch/lasx/bswap.ll
M llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
M llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll
M llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
M llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
M llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll
M llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
M llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
M llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/extractelement.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
M llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
M llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
M llvm/test/CodeGen/LoongArch/lasx/mulh.ll
M llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
M llvm/test/CodeGen/LoongArch/lasx/shuffle-as-permute-and-shuffle.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-and.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-or.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smax.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-smin.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umax.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-umin.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-reduce-xor.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll
M llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll
M llvm/test/CodeGen/LoongArch/lasx/vselect.ll
M llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
M llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
M llvm/test/CodeGen/LoongArch/lsx/bswap.ll
M llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll
M llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
M llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
M llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
M llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll
M llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
M llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll
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M llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll
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M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll
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M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
M llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
M llvm/test/CodeGen/LoongArch/lsx/mulh.ll
M llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
M llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
M llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
M llvm/test/CodeGen/LoongArch/lsx/vselect.ll
M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
M llvm/test/CodeGen/LoongArch/select-const.ll
M llvm/test/CodeGen/MIR/AMDGPU/dead-flag-on-use-operand-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-fixed-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-invalid-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index-no-stack.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-frame-index2.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/killed-flag-on-def-parse-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-expect-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/noalias-addrspace-undefine-matadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/noconvergent-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/sgpr-for-exec-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-invalid.mir
M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs-not-a-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-invalid-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/wwm-reserved-regs-not-a-reg.mir
M llvm/test/CodeGen/NVPTX/access-non-generic.ll
M llvm/test/CodeGen/NVPTX/activemask.ll
M llvm/test/CodeGen/NVPTX/addrspacecast-ptx64.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/alias.ll
M llvm/test/CodeGen/NVPTX/annotations.ll
M llvm/test/CodeGen/NVPTX/applypriority.ll
M llvm/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll
M llvm/test/CodeGen/NVPTX/arithmetic-int.ll
M llvm/test/CodeGen/NVPTX/async-copy.ll
M llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll
M llvm/test/CodeGen/NVPTX/atomics-b128.ll
M llvm/test/CodeGen/NVPTX/atomics-sm60.ll
M llvm/test/CodeGen/NVPTX/atomics-sm70.ll
M llvm/test/CodeGen/NVPTX/atomics-sm90.ll
M llvm/test/CodeGen/NVPTX/atomics-with-scope.ll
M llvm/test/CodeGen/NVPTX/b52037.ll
M llvm/test/CodeGen/NVPTX/barrier.ll
M llvm/test/CodeGen/NVPTX/bf16-instructions.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/bmsk.ll
M llvm/test/CodeGen/NVPTX/bswap.ll
M llvm/test/CodeGen/NVPTX/byval-arg-vectorize.ll
M llvm/test/CodeGen/NVPTX/byval-const-global.ll
M llvm/test/CodeGen/NVPTX/calling-conv.ll
M llvm/test/CodeGen/NVPTX/cluster-dim.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
M llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll
M llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/NVPTX/combine-mad.ll
M llvm/test/CodeGen/NVPTX/combine-min-max.ll
M llvm/test/CodeGen/NVPTX/common-linkage.ll
M llvm/test/CodeGen/NVPTX/compare-int.ll
M llvm/test/CodeGen/NVPTX/convert-call-to-indirect.ll
M llvm/test/CodeGen/NVPTX/convert-fp.ll
M llvm/test/CodeGen/NVPTX/convert-int-sm20.ll
M llvm/test/CodeGen/NVPTX/convert-sm100.ll
M llvm/test/CodeGen/NVPTX/convert-sm100a.ll
M llvm/test/CodeGen/NVPTX/convert-sm80.ll
M llvm/test/CodeGen/NVPTX/convert-sm89.ll
M llvm/test/CodeGen/NVPTX/convert-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g.ll
M llvm/test/CodeGen/NVPTX/cp-async-bulk.ll
M llvm/test/CodeGen/NVPTX/discard.ll
M llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll
M llvm/test/CodeGen/NVPTX/dynamic_stackalloc.ll
M llvm/test/CodeGen/NVPTX/elect.ll
M llvm/test/CodeGen/NVPTX/f16-abs.ll
M llvm/test/CodeGen/NVPTX/f16-ex2.ll
M llvm/test/CodeGen/NVPTX/f16-instructions.ll
M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/f32-ex2.ll
M llvm/test/CodeGen/NVPTX/f32-lg2.ll
M llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
M llvm/test/CodeGen/NVPTX/fabs-intrinsics.ll
M llvm/test/CodeGen/NVPTX/fence-cluster.ll
M llvm/test/CodeGen/NVPTX/fence-nocluster.ll
M llvm/test/CodeGen/NVPTX/fence-proxy-tensormap.ll
M llvm/test/CodeGen/NVPTX/fexp2.ll
M llvm/test/CodeGen/NVPTX/flog2.ll
M llvm/test/CodeGen/NVPTX/fma-disable.ll
M llvm/test/CodeGen/NVPTX/fminimum-fmaximum.ll
M llvm/test/CodeGen/NVPTX/fns.ll
M llvm/test/CodeGen/NVPTX/fold-movs.ll
M llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
M llvm/test/CodeGen/NVPTX/global-addrspace.ll
M llvm/test/CodeGen/NVPTX/global-ordering.ll
M llvm/test/CodeGen/NVPTX/griddepcontrol.ll
M llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/idioms.ll
M llvm/test/CodeGen/NVPTX/indirect_byval.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test1.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test2.ll
M llvm/test/CodeGen/NVPTX/inline-asm-b128-test3.ll
M llvm/test/CodeGen/NVPTX/intrinsic-old.ll
M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
M llvm/test/CodeGen/NVPTX/intrinsics.ll
M llvm/test/CodeGen/NVPTX/kernel-param-align.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ld-generic.ll
M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
M llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
M llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
M llvm/test/CodeGen/NVPTX/load-store-scalars.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-70.ll
M llvm/test/CodeGen/NVPTX/load-store-sm-90.ll
M llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
M llvm/test/CodeGen/NVPTX/local-stack-frame.ll
M llvm/test/CodeGen/NVPTX/managed.ll
M llvm/test/CodeGen/NVPTX/match.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm53-ptx42.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72-autoupgrade.ll
M llvm/test/CodeGen/NVPTX/math-intrins-sm86-ptx72.ll
M llvm/test/CodeGen/NVPTX/math-intrins.ll
M llvm/test/CodeGen/NVPTX/mbarrier.ll
M llvm/test/CodeGen/NVPTX/nanosleep.ll
M llvm/test/CodeGen/NVPTX/nofunc.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nvcl-param-align.ll
M llvm/test/CodeGen/NVPTX/packed-aggr.ll
M llvm/test/CodeGen/NVPTX/param-overalign.ll
M llvm/test/CodeGen/NVPTX/pr126337.ll
M llvm/test/CodeGen/NVPTX/pr13291-i1-store.ll
M llvm/test/CodeGen/NVPTX/prefetch-inferas-test.ll
M llvm/test/CodeGen/NVPTX/prefetch.ll
M llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
M llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
M llvm/test/CodeGen/NVPTX/redux-sync.ll
M llvm/test/CodeGen/NVPTX/reg-types.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg-sm100a.ll
M llvm/test/CodeGen/NVPTX/setmaxnreg.ll
M llvm/test/CodeGen/NVPTX/sext-setcc.ll
M llvm/test/CodeGen/NVPTX/shfl-sync-p.ll
M llvm/test/CodeGen/NVPTX/shfl-sync.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/simple-call.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/NVPTX/st-generic.ll
M llvm/test/CodeGen/NVPTX/st-param-imm.ll
M llvm/test/CodeGen/NVPTX/st_bulk.ll
M llvm/test/CodeGen/NVPTX/stacksaverestore.ll
M llvm/test/CodeGen/NVPTX/surf-tex.py
M llvm/test/CodeGen/NVPTX/symbol-naming.ll
M llvm/test/CodeGen/NVPTX/szext.ll
M llvm/test/CodeGen/NVPTX/tanhf.ll
M llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
M llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
M llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
M llvm/test/CodeGen/NVPTX/tcgen05-fence.ll
M llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
M llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
M llvm/test/CodeGen/NVPTX/tcgen05-st.ll
M llvm/test/CodeGen/NVPTX/trunc-setcc.ll
M llvm/test/CodeGen/NVPTX/trunc-tofp.ll
M llvm/test/CodeGen/NVPTX/unreachable.ll
M llvm/test/CodeGen/NVPTX/vaargs.ll
M llvm/test/CodeGen/NVPTX/variadics-backend.ll
M llvm/test/CodeGen/NVPTX/vector-compare.ll
M llvm/test/CodeGen/NVPTX/vector-select.ll
M llvm/test/CodeGen/NVPTX/vote.ll
M llvm/test/CodeGen/NVPTX/weak-global.ll
M llvm/test/CodeGen/NVPTX/wgmma-sm90a-fence.ll
M llvm/test/CodeGen/NVPTX/wmma-ptx60-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx61-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm72.py
M llvm/test/CodeGen/NVPTX/wmma-ptx63-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx64-sm70.py
M llvm/test/CodeGen/NVPTX/wmma-ptx65-sm75.py
M llvm/test/CodeGen/NVPTX/wmma-ptx71-sm80.py
M llvm/test/CodeGen/NVPTX/wmma-ptx78-sm90.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm100a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm101a.py
M llvm/test/CodeGen/NVPTX/wmma-ptx86-sm120a.py
M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
M llvm/test/CodeGen/PowerPC/all-atomics.ll
M llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll
M llvm/test/CodeGen/PowerPC/atomic-float.ll
M llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll
M llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/PowerPC/atomics-regression.ll
M llvm/test/CodeGen/PowerPC/atomics.ll
M llvm/test/CodeGen/PowerPC/check-zero-vector.ll
M llvm/test/CodeGen/PowerPC/loop-comment.ll
A llvm/test/CodeGen/PowerPC/vsro-vsr-vsrq-dag-combine.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll
M llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll
A llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add-sub.ll
R llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add.ll
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv32.mir
R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/anyext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/icmp.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/implicit-def.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/load.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/select.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/store.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
M llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/zext.mir
M llvm/test/CodeGen/RISCV/GlobalISel/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
A llvm/test/CodeGen/RISCV/attributes-andes.ll
A llvm/test/CodeGen/RISCV/attributes-qc.ll
A llvm/test/CodeGen/RISCV/attributes-thead.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/redundant-vfmvsf.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
M llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir
M llvm/test/CodeGen/RISCV/xqciac.ll
M llvm/test/CodeGen/RISCV/xqcibm-insbi.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/OpIsInf.ll
M llvm/test/CodeGen/Thumb2/abds-crash.ll
M llvm/test/CodeGen/WebAssembly/global-set.ll
M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
A llvm/test/CodeGen/X86/AMX/amx-sink-config-after-calls.mir
M llvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
M llvm/test/CodeGen/X86/avx512fp16-fold-load-binops.ll
M llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/bswap-inline-asm.ll
M llvm/test/CodeGen/X86/call-graph-section.ll
M llvm/test/CodeGen/X86/combine-vpmadd52.ll
M llvm/test/CodeGen/X86/fpenv.ll
M llvm/test/CodeGen/X86/inline-asm-flag-clobber.ll
A llvm/test/CodeGen/X86/isel-ceil.ll
A llvm/test/CodeGen/X86/isel-floor.ll
A llvm/test/CodeGen/X86/isel-ftrunc.ll
A llvm/test/CodeGen/X86/isel-llvm.acos.ll
A llvm/test/CodeGen/X86/isel-llvm.asin.ll
A llvm/test/CodeGen/X86/isel-llvm.atan.ll
A llvm/test/CodeGen/X86/isel-llvm.atan2.ll
A llvm/test/CodeGen/X86/isel-llvm.cos.ll
A llvm/test/CodeGen/X86/isel-llvm.cosh.ll
A llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
A llvm/test/CodeGen/X86/isel-llvm.sin.ll
A llvm/test/CodeGen/X86/isel-llvm.sincos.ll
A llvm/test/CodeGen/X86/isel-llvm.sinh.ll
A llvm/test/CodeGen/X86/isel-llvm.tan.ll
A llvm/test/CodeGen/X86/isel-llvm.tanh.ll
R llvm/test/CodeGen/X86/llvm.acos.ll
R llvm/test/CodeGen/X86/llvm.asin.ll
R llvm/test/CodeGen/X86/llvm.atan.ll
R llvm/test/CodeGen/X86/llvm.atan2.ll
R llvm/test/CodeGen/X86/llvm.cos.ll
R llvm/test/CodeGen/X86/llvm.cosh.ll
R llvm/test/CodeGen/X86/llvm.sin.ll
R llvm/test/CodeGen/X86/llvm.sincos.ll
R llvm/test/CodeGen/X86/llvm.sinh.ll
R llvm/test/CodeGen/X86/llvm.tan.ll
R llvm/test/CodeGen/X86/llvm.tanh.ll
M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
A llvm/test/CodeGen/X86/pr156256.ll
M llvm/test/CodeGen/X86/pr67333.ll
M llvm/test/CodeGen/X86/shift-i128.ll
M llvm/test/CodeGen/X86/vec-strict-128-fp16.ll
A llvm/test/DebugInfo/Generic/structor-declaration-linkage-names.ll
M llvm/test/DebugInfo/NVPTX/dbg-value-const-byref.ll
M llvm/test/DebugInfo/NVPTX/debug-info.ll
M llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
M llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
A llvm/test/ExecutionEngine/JITLink/lit.local.cfg
A llvm/test/ExecutionEngine/Orc/lit.local.cfg
M llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2_512ni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2ni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl_vnni-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl_vnni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vnni-intrinsics-upgrade.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vnni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx_vnni-intrinsics.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avxvnniint8-intrinsics.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vflat_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3cx.s
M llvm/test/MC/AMDGPU/gfx1250_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vopc_t16_promote.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/AMDGPU/gfx90a_err.s
M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s
M llvm/test/MC/AMDGPU/user-sgpr-count-diag.s
M llvm/test/MC/AMDGPU/vop3-literal.s
A llvm/test/MC/AMDGPU/warnings.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3cx.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_buffer_err.txt
M llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
M llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
M llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
M llvm/test/MC/RISCV/xmips-invalid.s
M llvm/test/MC/RISCV/xmips-valid.s
M llvm/test/MC/RISCV/xqciac-valid.s
M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
M llvm/test/MachineVerifier/AMDGPU/undef-should-only-be-set-on-subreg-defs.mir
M llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
M llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
M llvm/test/MachineVerifier/AMDGPU/verify-av-mov-imm-pseudo.mir
M llvm/test/MachineVerifier/AMDGPU/verify-implicit-def.mir
M llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/basic.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/cycles.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/mixed2.mir
M llvm/test/MachineVerifier/convergencectrl/AMDGPU/region-nesting.mir
A llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td
M llvm/test/TableGen/DecoderEmitterFnTable.td
M llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td
M llvm/test/TableGen/HwModeEncodeDecode3.td
M llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td
M llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td
M llvm/test/TableGen/RuntimeLibcallEmitter.td
M llvm/test/TableGen/VarLenDecoder.td
A llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-private-gas.ll
M llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll
M llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll
M llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll
A llvm/test/Transforms/ConstraintElimination/implied-by-bounded-memory-access.ll
A llvm/test/Transforms/Coroutines/coro-split-dbg-labels-inlined.ll
M llvm/test/Transforms/Coroutines/coro-split-dbg.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem-inf.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/frem.ll
A llvm/test/Transforms/ExpandFp/AMDGPU/lit.local.cfg
A llvm/test/Transforms/GVN/PRE/no-phi-translate.ll
A llvm/test/Transforms/InferAlignment/masked.ll
M llvm/test/Transforms/InstCombine/2006-12-15-Range-Test.ll
M llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll
M llvm/test/Transforms/InstCombine/canonicalize-gep-constglob.ll
M llvm/test/Transforms/InstCombine/cast.ll
M llvm/test/Transforms/InstCombine/cast_phi.ll
M llvm/test/Transforms/InstCombine/gep-addrspace.ll
M llvm/test/Transforms/InstCombine/gep-alias.ll
M llvm/test/Transforms/InstCombine/gep-canonicalize-constant-indices.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepofconstgepi8.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/load-bitcast-select.ll
M llvm/test/Transforms/InstCombine/load-cmp.ll
M llvm/test/Transforms/InstCombine/loadstore-alignment.ll
M llvm/test/Transforms/InstCombine/mem-gep-zidx.ll
M llvm/test/Transforms/InstCombine/memchr-11.ll
M llvm/test/Transforms/InstCombine/memcmp-8.ll
M llvm/test/Transforms/InstCombine/memcpy-addrspace.ll
M llvm/test/Transforms/InstCombine/memcpy-from-global.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/pr58901.ll
M llvm/test/Transforms/InstCombine/ptrtoint-nullgep.ll
M llvm/test/Transforms/InstCombine/remove-loop-phi-multiply-by-zero.ll
M llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll
M llvm/test/Transforms/InstCombine/strcmp-3.ll
M llvm/test/Transforms/InstCombine/strlen-1.ll
M llvm/test/Transforms/InstCombine/strlen-4.ll
M llvm/test/Transforms/InstCombine/strlen-7.ll
M llvm/test/Transforms/InstCombine/strlen-8.ll
M llvm/test/Transforms/InstCombine/strlen-9.ll
M llvm/test/Transforms/InstCombine/strnlen-3.ll
M llvm/test/Transforms/InstCombine/strnlen-4.ll
M llvm/test/Transforms/InstCombine/strnlen-5.ll
M llvm/test/Transforms/InstCombine/sub-gep.ll
A llvm/test/Transforms/InstCombine/usub_sat_to_msb_mask.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
M llvm/test/Transforms/InstCombine/wcslen-1.ll
M llvm/test/Transforms/InstCombine/wcslen-3.ll
M llvm/test/Transforms/InstCombine/wcslen-5.ll
M llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll
M llvm/test/Transforms/LICM/hoist-speculatable-load.ll
A llvm/test/Transforms/LICM/pr117157.ll
M llvm/test/Transforms/LoopInterchange/profitability-vectorization-heuristic.ll
M llvm/test/Transforms/LoopInterchange/profitability-vectorization.ll
A llvm/test/Transforms/LoopStrengthReduce/X86/zext-signed-addrec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/blend-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/check-prof-info.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
A llvm/test/Transforms/LoopVectorize/AArch64/fixed-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call-scalarize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-wide-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/tail-fold-uniform-memops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-unroll.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
A llvm/test/Transforms/LoopVectorize/ARM/active-lane-mask.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll
M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
A llvm/test/Transforms/LoopVectorize/RISCV/gather-scatter-cost.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr154103.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/X86/constant-fold.ll
A llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/masked-store-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
M llvm/test/Transforms/LoopVectorize/X86/replicate-uniform-call.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
A llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size-needs-loop-guards.ll
M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-trunc-induction-steps.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/hints-trans.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
M llvm/test/Transforms/LoopVectorize/make-followup-loop-id.ll
M llvm/test/Transforms/LoopVectorize/miniters.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
M llvm/test/Transforms/LoopVectorize/pr36983-multiple-lcssa.ll
M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
M llvm/test/Transforms/LoopVectorize/predicatedinst-loop-invariant.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-deref-assumptions.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
M llvm/test/Transforms/LoopVectorize/single_early_exit.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/vect.stats.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll
M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
M llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll
M llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
M llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
M llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll
M llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
M llvm/test/Transforms/PhaseOrdering/single-iteration-loop-sroa.ll
M llvm/test/Transforms/RelLookupTableConverter/X86/relative_lookup_table.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/many-uses-fma-candidate.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/vecreduceadd.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/reduced-copyable-element.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/vec3-base.ll
A llvm/test/Transforms/SLPVectorizer/X86/no-schedule-terminate-inst.ll
M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
M llvm/test/Transforms/SLPVectorizer/X86/redux-feed-buildvector.ll
A llvm/test/Transforms/SLPVectorizer/X86/reschedule-only-scheduled.ll
A llvm/test/Transforms/SLPVectorizer/X86/revectorize-phis.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-callee-profile-mismatch.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-dangle.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-dangle2.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-desc-guid.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-inline.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-instsched.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-invoke.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-missing-probe.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-no-debug-info.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-peep.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch-error.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch-thinlto.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-selectionDAG.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-slotindex.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-matching-LCS.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-matching-lto.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-matching.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-renaming-recursive.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-renaming.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-stale-profile-toplev-func.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-verify.ll
M llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
M llvm/test/Transforms/SimplifyCFG/switch_create.ll
M llvm/test/Transforms/VectorCombine/X86/bitop-of-castops.ll
M llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
M llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll
M llvm/test/Verifier/AMDGPU/intrinsic-prefetch.ll
A llvm/test/Verifier/AMDGPU/llvm.amdgcn.cooperative.atomic.ll
M llvm/test/Verifier/AMDGPU/mfma-scale.ll
M llvm/test/Verifier/AMDGPU/wmma-f8f6f4.ll
A llvm/test/Verifier/nofree_metadata.ll
M llvm/test/lit.cfg.py
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
A llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
A llvm/test/tools/llvm-objcopy/COFF/strip-invalid-symidx-section.test
A llvm/test/tools/llvm-objcopy/COFF/strip-update-symidx-section.test
M llvm/test/tools/llvm-profdata/memprof-yaml.test
A llvm/test/tools/llvm-reduce/reduce-bb-callbr.ll
M llvm/tools/llvm-debuginfod/llvm-debuginfod.cpp
M llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
M llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
M llvm/tools/llvm-reduce/deltas/ReduceBasicBlocks.cpp
M llvm/tools/llvm-tli-checker/llvm-tli-checker.cpp
M llvm/tools/lto/CMakeLists.txt
M llvm/unittests/ADT/StringMapTest.cpp
M llvm/unittests/Analysis/IR2VecTest.cpp
M llvm/unittests/IR/RuntimeLibcallsTest.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
M llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp
A llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp
M llvm/unittests/Target/ARM/CMakeLists.txt
M llvm/unittests/Target/RISCV/CMakeLists.txt
A llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp
M llvm/utils/TableGen/Basic/RuntimeLibcallsEmitter.cpp
M llvm/utils/TableGen/CodeEmitterGen.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
M llvm/utils/TableGen/Common/CodeGenInstAlias.h
M llvm/utils/TableGen/Common/CodeGenInstruction.cpp
M llvm/utils/TableGen/Common/CodeGenInstruction.h
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/UpdateTestChecks/asm.py
M llvm/utils/git/pre-push.py
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/Disassembler/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Disassembler/BUILD.gn
M llvm/utils/lit/lit/ShUtil.py
M llvm/utils/lit/tests/unit/ShUtil.py
M llvm/utils/profcheck-xfail.txt
M llvm/utils/release/github-upload-release.py
M mlir/CMakeLists.txt
M mlir/docs/Bindings/Python.md
M mlir/examples/standalone/CMakeLists.txt
M mlir/examples/standalone/python/CMakeLists.txt
M mlir/include/mlir-c/IR.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrs.h
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/include/mlir/Dialect/Math/Transforms/Passes.h
M mlir/include/mlir/Dialect/Math/Transforms/Passes.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/Ptr/IR/CMakeLists.txt
M mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.h
M mlir/include/mlir/Dialect/Ptr/IR/MemorySpaceInterfaces.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrAttrs.h
A mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrEnums.td
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.h
M mlir/include/mlir/Dialect/Ptr/IR/PtrOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/EnumAttr.td
M mlir/include/mlir/IR/OpBase.td
M mlir/include/mlir/IR/Properties.td
M mlir/include/mlir/Query/Matcher/SliceMatchers.h
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
A mlir/include/mlir/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.h
M mlir/lib/Bindings/Python/IRAttributes.cpp
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/lib/Bindings/Python/Pass.cpp
M mlir/lib/Bindings/Python/TransformInterpreter.cpp
M mlir/lib/CAPI/Dialect/LLVM.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
M mlir/lib/Conversion/ConvertToLLVM/ConvertToLLVMPass.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Conversion/NVVMToLLVM/NVVMToLLVM.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/Arith/Transforms/CMakeLists.txt
M mlir/lib/Dialect/ArmNeon/Transforms/LowerContractToNeonPatterns.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp
M mlir/lib/Dialect/ControlFlow/Transforms/CMakeLists.txt
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/EmitC/Transforms/Transforms.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMAttrs.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/Math/Transforms/CMakeLists.txt
A mlir/lib/Dialect/Math/Transforms/ExpandOps.cpp
R mlir/lib/Dialect/Math/Transforms/ExpandPatterns.cpp
M mlir/lib/Dialect/MemRef/Transforms/BufferViewFlowOpInterfaceImpl.cpp
M mlir/lib/Dialect/Ptr/IR/CMakeLists.txt
A mlir/lib/Dialect/Ptr/IR/MemorySpaceInterfaces.cpp
M mlir/lib/Dialect/Ptr/IR/PtrAttrs.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/Quant/Transforms/CMakeLists.txt
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
A mlir/lib/Dialect/SPIRV/IR/ArmGraphOps.cpp
M mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
M mlir/lib/Dialect/SPIRV/IR/SPIRVOpDefinition.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp
M mlir/lib/Dialect/SPIRV/Transforms/UpdateVCEPass.cpp
M mlir/lib/Dialect/Shard/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
M mlir/lib/Dialect/SparseTensor/IR/Detail/Var.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/lib/Dialect/Transform/IR/TransformOps.cpp
M mlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/IR/AsmPrinter.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/Location.cpp
M mlir/lib/Interfaces/ValueBoundsOpInterface.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/lib/Target/LLVMIR/Dialect/Ptr/CMakeLists.txt
A mlir/lib/Target/LLVMIR/Dialect/Ptr/PtrToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Target/LLVMIR/TypeToLLVM.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Tools/mlir-query/MlirQueryMain.cpp
M mlir/lib/Tools/mlir-reduce/MlirReduceMain.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Conversion/ArithToEmitC/arith-to-emitc.mlir
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
A mlir/test/Conversion/FuncToLLVM/func-to-llvm-datalayout.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/PtrToLLVM/ptr-to-llvm.mlir
M mlir/test/Conversion/VectorToLLVM/use-vector-alignment.mlir
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm-interface.mlir
M mlir/test/Dialect/EmitC/form-expressions.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
A mlir/test/Dialect/GPU/broadcast-speculatability.mlir
M mlir/test/Dialect/GPU/int-range-interface.mlir
M mlir/test/Dialect/GPU/ops.mlir
M mlir/test/Dialect/LLVMIR/debuginfo.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
A mlir/test/Dialect/LLVMIR/ptr.mlir
M mlir/test/Dialect/Math/expand-math.mlir
M mlir/test/Dialect/Math/ops.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
M mlir/test/Dialect/Ptr/invalid.mlir
M mlir/test/Dialect/Ptr/ops.mlir
M mlir/test/Dialect/SPIRV/IR/availability.mlir
A mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Dialect/Tosa/level_check.mlir
M mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
M mlir/test/Examples/standalone/test.toy
M mlir/test/IR/array-of-attr.mlir
M mlir/test/Target/Cpp/control_flow.mlir
M mlir/test/Target/Cpp/expressions.mlir
M mlir/test/Target/Cpp/for.mlir
M mlir/test/Target/Cpp/switch.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir-invalid.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/nvvm/prefetch.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-cp.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-shift.mlir
M mlir/test/Target/LLVMIR/nvvmir-invalid.mlir
A mlir/test/Target/LLVMIR/ptr.mlir
M mlir/test/Transforms/remove-dead-values.mlir
M mlir/test/lib/Dialect/Math/CMakeLists.txt
R mlir/test/lib/Dialect/Math/TestExpandMath.cpp
M mlir/test/lib/Dialect/SPIRV/TestAvailability.cpp
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
M mlir/test/lib/Dialect/Test/TestEnumDefs.td
M mlir/test/lib/Transforms/TestTransformsOps.cpp
M mlir/test/mlir-runner/test-expand-math-approx.mlir
M mlir/test/mlir-tblgen/attr-or-type-format-roundtrip.mlir
M mlir/test/mlir-tblgen/attr-or-type-format.td
M mlir/test/python/ir/auto_location.py
M mlir/test/python/ir/module.py
M mlir/test/python/ir/operation.py
M mlir/test/python/ir/symbol_table.py
M mlir/test/python/pass_manager.py
M mlir/tools/mlir-irdl-to-cpp/CMakeLists.txt
M mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/tools/mlir-tblgen/AttrOrTypeFormatGen.cpp
M mlir/tools/mlir-tblgen/EnumsGen.cpp
M mlir/tools/mlir-tblgen/mlir-tblgen.cpp
M mlir/unittests/ExecutionEngine/Invoke.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/test/CMakeLists.txt
M offload/test/offloading/mandatory_but_no_devices.c
M offload/test/offloading/memory_manager.cpp
M offload/test/tools/llvm-omp-device-info.c
M offload/tools/deviceinfo/CMakeLists.txt
M offload/tools/deviceinfo/llvm-offload-device-info.cpp
M openmp/runtime/src/CMakeLists.txt
M openmp/tools/omptest/CMakeLists.txt
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt-c/WrapperFunction.h
R orc-rt/include/orc-rt-c/WrapperFunctionResult.h
A orc-rt/include/orc-rt/WrapperFunction.h
R orc-rt/include/orc-rt/WrapperFunctionResult.h
M orc-rt/unittests/CMakeLists.txt
A orc-rt/unittests/WrapperFunctionBufferTest.cpp
R orc-rt/unittests/WrapperFunctionResultTest.cpp
M polly/lib/External/CMakeLists.txt
M utils/bazel/WORKSPACE
M utils/bazel/llvm-project-overlay/clang/unittests/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/string/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
Merge remote-tracking branch 'origin/main' into users/ccc/clang-tidy/query-check
Commit: 2a3e0f1c26970563cae44a57936234ab4b103742
https://github.com/llvm/llvm-project/commit/2a3e0f1c26970563cae44a57936234ab4b103742
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2025-09-04 (Thu, 04 Sep 2025)
Changed paths:
M clang-tools-extra/docs/clang-tidy/QueryBasedCustomChecks.rst
Log Message:
-----------
doc
Compare: https://github.com/llvm/llvm-project/compare/0a99d0c12ed6...2a3e0f1c2697
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