[all-commits] [llvm/llvm-project] b88085: [AMDGPU] Define 1024 VGPRs on gfx1250

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/users/rampitec/09-03-_amdgpu_reginfo_changes_to_define_1024_vgprs
  Home:   https://github.com/llvm/llvm-project
  Commit: b8808533bf048519a7edbf010bac6dea3d8849ba
      https://github.com/llvm/llvm-project/commit/b8808533bf048519a7edbf010bac6dea3d8849ba
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2025-09-03 (Wed, 03 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
    M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
    M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm-out-of-bounds-register.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
    M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
    M llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

  Log Message:
  -----------
  [AMDGPU] Define 1024 VGPRs on gfx1250

This is a baseline support, it is not useable yet.



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