[all-commits] [llvm/llvm-project] 7d6e72: [RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_AT...

[Kane Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7d6e72f11033685af069e40697cd9fc0bad0a682
      https://github.com/llvm/llvm-project/commit/7d6e72f11033685af069e40697cd9fc0bad0a682
  Author: Kane Wang <wangqiang1 at kylinos.cn>
  Date:   2025-09-03 (Wed, 03 Sep 2025)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add-sub.ll
    R llvm/test/CodeGen/RISCV/GlobalISel/atomicrmw-add.ll
    R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv32.mir
    R llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/atomicrmw-add-sub-rv64.mir
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
    R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv32.mir
    R llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-atomicrmw-add-sub-rv64.mir

  Log Message:
  -----------
  [RISCV][GlobalISel] Lower G_ATOMICRMW_SUB via G_ATOMICRMW_ADD (#155972)

RISCV does not provide a native atomic subtract instruction, so this
patch lowers `G_ATOMICRMW_SUB` by negating the RHS value and performing
an atomic add. The legalization rules in `RISCVLegalizerInfo` are
updated accordingly, with libcall fallbacks when `StdExtA` is not
available, and intrinsic legalization is extended to support
`riscv_masked_atomicrmw_sub`.

For example, lowering

`%1 = atomicrmw sub ptr %a, i32 1 seq_cst`

on riscv32a produces:

```
li      a1, -1
amoadd.w.aqrl   a0, a1, (a0)
```

On riscv64a, where the RHS type is narrower than XLEN, it currently
produces:

```
li      a1, 1
neg     a1, a1
amoadd.w.aqrl   a0, a1, (a0)
```

There is still a constant-folding or InstConbiner gap. For instance,
lowering

```
%b = sub i32 %x, %y
%1 = atomicrmw sub ptr %a, i32 %b seq_cst
```

generates:

```
subw    a1, a1, a2
neg     a1, a1
amoadd.w.aqrl   a0, a1, (a0)
```

This sequence could be optimized further to eliminate the redundant neg.
Addressing this may require improvements in the Combiner or Peephole
Optimizer in future work.

---------

Co-authored-by: Kane Wang <kanewang95 at foxmail.com>



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