[all-commits] [llvm/llvm-project] 20b4f5: [RISCV] add computeKnownBitsForTargetNode for RISC...

[Shreeyash Pandey via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 20b4f59ccad51e26e7cbd8b317c9f331d1ada6e5
      https://github.com/llvm/llvm-project/commit/20b4f59ccad51e26e7cbd8b317c9f331d1ada6e5
  Author: Shreeyash Pandey <shreeyash335 at gmail.com>
  Date:   2025-09-03 (Wed, 03 Sep 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/unittests/Target/RISCV/CMakeLists.txt
    A llvm/unittests/Target/RISCV/RISCVSelectionDAGTest.cpp

  Log Message:
  -----------
  [RISCV] add computeKnownBitsForTargetNode for RISCVISD::SRLW (#155995)

I've added support for computeKnownBitsForTargetNode for the SRLW
instruction. A test has been included which uses the snippet of IR as
suggested by topperc.

Fixed #154913

---------

Signed-off-by: Shreeyash Pandey <shreeyash335 at gmail.com>
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>



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