[all-commits] [llvm/llvm-project] 73bed6: [AArch64] Improve lowering for scalable masked dei...

[David Sherwood via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73bed64433072338d11ebf770d6db99c2ce810aa
      https://github.com/llvm/llvm-project/commit/73bed64433072338d11ebf770d6db99c2ce810aa
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2025-09-03 (Wed, 03 Sep 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/fixed_masked_deinterleaved_loads.ll
    A llvm/test/CodeGen/AArch64/scalable_masked_deinterleaved_loads.ll

  Log Message:
  -----------
  [AArch64] Improve lowering for scalable masked deinterleaving loads (#154338)

For IR like this:

%mask = ... @llvm.vector.interleave2(<vscale x 16 x i1> %a, <vscale x 16
x i1> %a)
  %vec = ... @llvm.masked.load(..., <vscale x 32 x i1> %mask, ...)
  %dvec = ... @llvm.vector.deinterleave2(<vscale x 32 x i8> %vec)

where we're deinterleaving a wide masked load of the supported type
and with an interleaved mask we can lower this directly to a ld2b
instruction. Similarly we can also support other variants of ld2
and ld4.

This PR adds a DAG combine to spot such patterns and lower to ld2X
or ld4X variants accordingly, whilst being careful to ensure the
masked load is only used by the deinterleave intrinsic.



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