[all-commits] [llvm/llvm-project] 4ec890: AMDGPU: Try to constrain av registers to VGPR to e...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4ec890857da327adf547d3fece986e125ff2e2cb
      https://github.com/llvm/llvm-project/commit/4ec890857da327adf547d3fece986e125ff2e2cb
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-09-03 (Wed, 03 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    A llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
    M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir

  Log Message:
  -----------
  AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation (#156400)

In future changes we will have more AV_ virtual registers, which
currently
block the formation of write2. Most of the time these registers can
simply
be constrained to VGPR, so do that.

Also relaxes the constraint in flat merging case. We already have the
necessary
code to insert copies to the original result registers, so there's no
point
in avoiding it.

Addresses the easy half of #155769



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