[all-commits] [llvm/llvm-project] b0c453: AMDGPU: Try to constrain av registers to VGPR to e...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/issue155769/amdgpu-try-constrain-to-vgpr-ds-write2
  Home:   https://github.com/llvm/llvm-project
  Commit: b0c453633f83a8e3f031c9e3dd8ba11e38a9d7de
      https://github.com/llvm/llvm-project/commit/b0c453633f83a8e3f031c9e3dd8ba11e38a9d7de
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-09-03 (Wed, 03 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
    A llvm/test/CodeGen/AMDGPU/load-store-opt-ds-regclass-constrain.mir
    M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
    M llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir

  Log Message:
  -----------
  AMDGPU: Try to constrain av registers to VGPR to enable ds_write2 formation

In future changes we will have more AV_ virtual registers, which currently
block the formation of write2. Most of the time these registers can simply
be constrained to VGPR, so do that.

Also relaxes the constraint in flat merging case. We already have the necessary
code to insert copies to the original result registers, so there's no point
in avoiding it.

Addresses the easy half of #155769


  Commit: beb9b6cbba9df94bd53c5644f92788804bd50366
      https://github.com/llvm/llvm-project/commit/beb9b6cbba9df94bd53c5644f92788804bd50366
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-09-03 (Wed, 03 Sep 2025)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir

  Log Message:
  -----------
  rename test functions


Compare: https://github.com/llvm/llvm-project/compare/b60de2d0a971...beb9b6cbba9d

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