[all-commits] [llvm/llvm-project] d8fd51: [VPlan] Introduce CSE pass (#151872)

[Ramkumar Ramachandra via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d8fd51148069bdea95974b3877abc31bcf5bf5ab
      https://github.com/llvm/llvm-project/commit/d8fd51148069bdea95974b3877abc31bcf5bf5ab
  Author: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
  Date:   2025-09-02 (Tue, 02 Sep 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
    M llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/licm-calls.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/masked-call-scalarize.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/masked-call.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
    M llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll
    M llvm/test/Transforms/LoopVectorize/X86/replicate-uniform-call.ll
    M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
    M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
    M llvm/test/Transforms/LoopVectorize/pr36983-multiple-lcssa.ll
    M llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
    M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
    M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll
    M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll

  Log Message:
  -----------
  [VPlan] Introduce CSE pass (#151872)

Introduce a simple common-subexpression-elimination pass at the
VPlan-level, running late during the execution of the VPlan. The
long-term vision is to get rid of the legacy non-VPlan-based cse routine
in LV, but this patch doesn't yet fully subsume it.



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