[all-commits] [llvm/llvm-project] 76a694: AMDGPU: Add agpr variants of multi-data DS instruc...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/define-agpr-variants-ds-write2-insts
  Home:   https://github.com/llvm/llvm-project
  Commit: 76a69476c07c11bb997c93b15a3f13a20e8acdf0
      https://github.com/llvm/llvm-project/commit/76a69476c07c11bb997c93b15a3f13a20e8acdf0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-09-02 (Tue, 02 Sep 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/DSInstructions.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/a-v-ds-atomic-cmpxchg.ll
    M llvm/test/MC/AMDGPU/gfx90a_err.s
    M llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s

  Log Message:
  -----------
  AMDGPU: Add agpr variants of multi-data DS instructions

The instruction definitions for loads and stores do not
accurately model the operand constraints of loads and stores
with AGPRs. They use AV register classes, plus a hack
a hack in getRegClass/getOpRegClass to avoid using AGPRs or
AV classes with the multiple operand cases, but it did not
consider the 3 operand case.

Model this correctly by using separate all-VGPR and all-AGPR
variants for the cases with multiple data operands.

This does regress the assembler errors on gfx908 for the
multi-operand cases. It now reports a generic operand
invalid error for GPU instead of the specific message
that agpr loads and stores aren't supported.

In the future AMDGPURewriteAGPRCopyMFMA should be taught
to replace the VGPR forms with the AGPR ones.

Most of the diff is fighting the DS pseudo structure. The
mnemonic was being used as the key to SIMCInstr, which is a
collision in the AGPR case. We also need to go out of our way
to make sure we are using the gfx9+ variants of the pseudos
without the m0 use. The DS multiclasses could use a lot of
cleanup.

Fixes #155777



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