[all-commits] [llvm/llvm-project] 865f95: [AArch64][SDAG] Add f16 -> i16 rounding NEON conve...

[Kajetan Puchalski via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 865f9566c383eede4e55d73924fda2ade917324a
      https://github.com/llvm/llvm-project/commit/865f9566c383eede4e55d73924fda2ade917324a
  Author: Kajetan Puchalski <kajetan.puchalski at arm.com>
  Date:   2025-08-31 (Sun, 31 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    A llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll
    M llvm/test/CodeGen/AArch64/fp16_intrinsic_vector_1op.ll

  Log Message:
  -----------
  [AArch64][SDAG] Add f16 -> i16 rounding NEON conversion intrinsics (#155851)

Add dedicated .i16.f16 formats for rounding NEON conversion intrinsics
in order to avoid issues with incorrect overflow behaviour caused by
using .i32.f16 formats to perform the same conversions.

Added intrinsic formats:
i16 @llvm.aarch64.neon.fcvtzs.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtzu.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtas.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtau.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtms.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtmu.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtns.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtnu.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtps.i16.f16(half)
i16 @llvm.aarch64.neon.fcvtpu.i16.f16(half)

Backend side of the solution to
https://github.com/llvm/llvm-project/issues/154343

---------

Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>



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