[all-commits] [llvm/llvm-project] 4a6435: [SelectionDAG] Add computeKnownBits for ISD::ROTL/...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4a6435397ba587022ecafa772cd504b8659da2fb
      https://github.com/llvm/llvm-project/commit/4a6435397ba587022ecafa772cd504b8659da2fb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-08-30 (Sat, 30 Aug 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
    M llvm/test/CodeGen/X86/pr67333.ll

  Log Message:
  -----------
  [SelectionDAG] Add computeKnownBits for ISD::ROTL/ROTR. (#156142)



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