[all-commits] [llvm/llvm-project] f3f717: [RISCV] Add computeKnownBitsForTargetNode for RISC...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3f717bbfa61600703b3b2149ebdb87fbee2dbac
      https://github.com/llvm/llvm-project/commit/f3f717bbfa61600703b3b2149ebdb87fbee2dbac
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-08-30 (Sat, 30 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

  Log Message:
  -----------
  [RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191)

This node reads the lower 32 bits, shifts it right arithmetically
then sign extends to i64. If we know some of the lower 32 bits we
can propagate that information.
    
For the test case I had to find something that didn't get optimized
before type legalizaton and didn't get type legalized to a sign
extended value. The bswap gets type legalized to (lshr (bswap), 32).



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications