[all-commits] [llvm/llvm-project] c17b29: AMDGPU: Add VS_64_Align2 class

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/add-vs_64_align2-regclass
  Home:   https://github.com/llvm/llvm-project
  Commit: c17b29d8623b5c772237a63e37d9661108225a7b
      https://github.com/llvm/llvm-project/commit/c17b29d8623b5c772237a63e37d9661108225a7b
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-08-30 (Sat, 30 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir

  Log Message:
  -----------
  AMDGPU: Add VS_64_Align2 class

We need an aligned version of the VS class to properly
represent operand constraints.

This fixes regressions with #155559



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