[all-commits] [llvm/llvm-project] 448811: [mlir][amx] Add write side effect to AMX tile crea...

[Arun Thangamani via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 448811dfc2ab93ec8d01c3afa93c98e83ac6376b
      https://github.com/llvm/llvm-project/commit/448811dfc2ab93ec8d01c3afa93c98e83ac6376b
  Author: Arun Thangamani <arun.thangamani at intel.com>
  Date:   2025-08-29 (Fri, 29 Aug 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/AMX/AMX.td
    A mlir/test/Dialect/AMX/side-effects.mlir

  Log Message:
  -----------
  [mlir][amx] Add write side effect to AMX tile creation ops (#155403)

Adds `MemWrite` side effect to `amx.tile_zero` and `amx.tile_load` ops.

Memory write models hardware populating AMX tiles with specified values
through tile zero and load ops.
Making the side effect explicit allows to use multiple op instances as a
compilation hint to use different AMX tile registers. This can prevent
less efficient lowering through tile store-load copies compared to
directly populating tiles with values.

To illustrate the trade off:
Without explicit side effects, `CSE` optimizes two `amx.tile_zero` into
a single op which lowers to a copy for the second tile:
```
  tilezero        %tmm0
  tilestored      %tmm0, -2032(%rbp,%rbx) # 1024-byte Folded Spill
  tileloadd       -2032(%rbp,%rbx), %tmm1 # 1024-byte Folded Reload
```
By keeping the two `amx.tile_zero` ops and, thus, lowering to two
separate intrinsic invocations, the two tile registers are zeroed out
directly without the additional round trip through memory:
```
  tilezero        %tmm0
  tilezero        %tmm1
```
The same principle applies to `amx.tile_load` ops.



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