[all-commits] [llvm/llvm-project] 6dd67f: [AArch64][SDAG] Lower f16->s16 FP_TO_INT_SAT to *v...

[Kajetan Puchalski via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6dd67f8c8a0ff5d8b46a69f2316c41bb11536881
      https://github.com/llvm/llvm-project/commit/6dd67f8c8a0ff5d8b46a69f2316c41bb11536881
  Author: Kajetan Puchalski <kajetan.puchalski at arm.com>
  Date:   2025-08-28 (Thu, 28 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll

  Log Message:
  -----------
  [AArch64][SDAG] Lower f16->s16 FP_TO_INT_SAT to *v1f16 (#154822)

Conversions from f16 to s16 performed by FP_TO_INT_SAT can be done
directly within FPRs, e.g. `fcvtzs h0, h0`.
Generating this format reduces the number of instruction required for
correct behaviour, as it sidesteps the issues with incorrect saturation
that arise when using `fcvtzs w0, h0` for the same casts.
Add new AArch64ISD::FCVTZS_HALF and AArch64ISD::FCVTZU_HALF nodes to
represent the necessary instruction sequence.

Related to https://github.com/llvm/llvm-project/issues/154343.

---------

Signed-off-by: Kajetan Puchalski <kajetan.puchalski at arm.com>



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