[all-commits] [llvm/llvm-project] 58df9b: [RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 58df9b1a01866e6f1f54f66356b1243920e5fe00
      https://github.com/llvm/llvm-project/commit/58df9b1a01866e6f1f54f66356b1243920e5fe00
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2025-08-27 (Wed, 27 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll
    M llvm/test/CodeGen/RISCV/imm.ll
    M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
    M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/shl-cttz.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/xqccmp-additional-stack.ll
    M llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll
    M llvm/test/CodeGen/RISCV/zcmp-additional-stack.ll

  Log Message:
  -----------
  [RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)

This block of code is currently conditional on the fusions being enabled
but as far as I can tell, does no harm to generally enable. The net
effect is the generically compiled code runs slightly better on machines
with this fusion.

The actual motivation is merely to stop confusing myself when I see the
sequence in code; the register allocators choice to sometimes blow two
registers instead of one is just generally weird, and my eyes spot it
when scanning disassembly.

(Note that this is just the regalloc hint; the scheduling changes remain
conditional, and probably should remain so.)



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