[all-commits] [llvm/llvm-project] 833b7f: AMDGPU: Allow folding multiple uses of some immedi...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/amdgpu/fold-immediate-allow-multiple-uses
  Home:   https://github.com/llvm/llvm-project
  Commit: 833b7faa2b47ada18e25e23ff820c668222e6a54
      https://github.com/llvm/llvm-project/commit/833b7faa2b47ada18e25e23ff820c668222e6a54
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-08-28 (Thu, 28 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/addrspacecast-gas.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/dagcomb-extract-vec-elt-different-sizes.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
    M llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
    M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.AFLCustomIRMutator.opt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
    M llvm/test/CodeGen/AMDGPU/mad-combine.ll
    M llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
    M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
    A llvm/test/CodeGen/AMDGPU/peephole-fold-imm-multi-use.mir
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/roundeven.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
    M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
    M llvm/test/CodeGen/AMDGPU/valu-i1.ll

  Log Message:
  -----------
  AMDGPU: Allow folding multiple uses of some immediates into copies

In some cases this will require an avoidable re-defining of
a register, but it works out better most of the time. Also allow
folding 64-bit immediates into subregister extracts, unless it would
break an inline constant.

We could be more aggressive here, but this set of conditions seems
to do a reasonable job without introducing too many regressions.



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