[all-commits] [llvm/llvm-project] 18f5e4: [RISCV] Added ROLW/RORW/SLLW/SRAW/SRLW for canCrea...

[Jasmine Tang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18f5e42b8ccb08516f5f79ca974e261d41d3b827
      https://github.com/llvm/llvm-project/commit/18f5e42b8ccb08516f5f79ca974e261d41d3b827
  Author: Jasmine Tang <jjasmine at igalia.com>
  Date:   2025-08-27 (Wed, 27 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Added ROLW/RORW/SLLW/SRAW/SRLW for canCreateUndefOrPoisonForTargetNode (#152609)

Fixes https://github.com/llvm/llvm-project/issues/149285.



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