[all-commits] [llvm/llvm-project] 818b39: [AArch64][SME] Simplify initialization of the TPID...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 818b39ef64e780127ecbaace0c0b27b351b5f987
      https://github.com/llvm/llvm-project/commit/818b39ef64e780127ecbaace0c0b27b351b5f987
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2025-08-27 (Wed, 27 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll
    M llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
    M llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
    M llvm/test/CodeGen/AArch64/sme-za-control-flow.ll
    M llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll
    M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
    M llvm/test/CodeGen/AArch64/stack-hazard.ll
    M llvm/test/CodeGen/AArch64/sve-stack-frame-layout.ll

  Log Message:
  -----------
  [AArch64][SME] Simplify initialization of the TPIDR2 block (#141049)

This patch updates the definition of `AArch64ISD::INIT_TPIDR2OBJ` to
take the number of save slices (which is currently always all ZA
slices). Using this, we can initialize the TPIDR2 block with a single
STP of the save buffer pointer and the number of save slices. The
reserved bytes (10-15) will be implicitly zeroed as the result of RDSVL
will always be <= 16-bits.

Note: We used to write the number of save slices to the TPIDR2 block
before every call with a lazy save; however, based on 6.6.9 "Changes to
the TPIDR2 block" in the aapcs64 
(https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#changes-to-the-tpidr2-block), 
it seems we can rely on callers preserving the contents of the TPIDR2 block.



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