[all-commits] [llvm/llvm-project] acaa92: [IA][RISCV] Recognize interleaving stores that cou...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: acaa925cb22b8559c491fff069b4b885cb4433f6
      https://github.com/llvm/llvm-project/commit/acaa925cb22b8559c491fff069b4b885cb4433f6
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-08-26 (Tue, 26 Aug 2025)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/lib/Target/X86/X86InterleavedAccess.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  [IA][RISCV] Recognize interleaving stores that could lower to strided segmented stores (#154647)

This is a sibling patch to #151612: passing gap masks to the renewal TLI
hooks for lowering interleaved stores that use shufflevector to do the
interleaving.



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