[all-commits] [llvm/llvm-project] f3520c: [VPlan] Replace EVL branch condition with (branch-...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3520c538d7760f8e76881831eac22e0a2f6e4ba
      https://github.com/llvm/llvm-project/commit/f3520c538d7760f8e76881831eac22e0a2f6e4ba
  Author: Luke Lau <luke at igalia.com>
  Date:   2025-08-26 (Tue, 26 Aug 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
    M llvm/test/Transforms/LoopVectorize/RISCV/bf16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/blocks-with-dead-instructions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/defaults.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/f16.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/induction-costs.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/lmul.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/mask-index-type.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr154103.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/pr88802.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/reductions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/remark-reductions.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-basics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-tailfold.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-bin-unary-ops-args.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-call-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cast-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-cond-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-div.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-gather-scatter.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-inloop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-intermediate-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-iv32.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-known-no-overflow.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-masked-loadstore.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-ordered-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reduction.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-safe-dep-distance.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vectorize-vp-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/vf-will-not-generate-any-vector-insts.ll

  Log Message:
  -----------
  [VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)

This changes the branch condition to use the AVL's backedge value
instead of the EVL-based IV.

This allows us to emit bnez on RISC-V and removes a use of the trip
count, which should reduce register pressure.

To match phis with VPlanPatternMatch I've had to relax the assert that
the number of operands must exactly match the pattern for the Phi
opcode, and I've copied over m_ZExtOrSelf from the LLVM IR
PatternMatch.h.

Fixes #151459



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