[all-commits] [llvm/llvm-project] 562896: [DAGCombiner] Preserve nuw when converting mul to ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56289647beb27972dfab46b78224b200a03eb22e
      https://github.com/llvm/llvm-project/commit/56289647beb27972dfab46b78224b200a03eb22e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-08-25 (Mon, 25 Aug 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll

  Log Message:
  -----------
  [DAGCombiner] Preserve nuw when converting mul to shl. Use nuw in srl+shl combine. (#155043)

If the srl+shl have the same shift amount and the shl has the nuw flag,
we can remove both.

In the affected test, the InterleavedAccess pass will emit a udiv after
the `mul nuw`. We expect them to combine away. The remaining shifts on
the RV64 tests are because we didn't add the zeroext attribute to the
incoming evl operand.



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