[all-commits] [llvm/llvm-project] 9db7e8: [RISCV] Refactor RVV builtin code generation for r...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9db7e8d070f2180c19564cd77f724b2732b489d0
      https://github.com/llvm/llvm-project/commit/9db7e8d070f2180c19564cd77f724b2732b489d0
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2025-08-26 (Tue, 26 Aug 2025)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/lib/CodeGen/TargetBuiltins/RISCV.cpp

  Log Message:
  -----------
  [RISCV] Refactor RVV builtin code generation for reduce compilation time [NFC] (#154906)

Extract ManualCodegen blocks from riscv_vector.td to dedicated helper
functions in RISCV.cpp to improve compilation times and code
organization.

This refactoring:
- Reduces riscv_vector_builtin_cg.inc from ~70,000 lines to ~30,000
lines
- Extracts lots of ManualCodegen blocks into helper functions in
RISCV.cpp
- Moves complex code generation logic from TableGen to C++
- Marks extracted functions with LLVM_ATTRIBUTE_NOINLINE to prevent
excessive inlining in EmitRISCVBuiltinExpr's large switch statement,
which would cause compilation time to increase significantly

Performance Impact on AMD Ryzen 9 3950X 16-Core with SSD (Release build)
with GCC 11:

Before: real 1m4.560s, user 0m0.529s, sys 0m0.175s
After:  real 0m22.577s, user 0m0.498s, sys 0m0.152s

Which reduced around 65% of compilation time.

During this refactoring, I also found few more opportunities to optimize
and simplify the code generation logic, but I think leave to next PR
since it already change a lot of code.

Fix #88368



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