[all-commits] [llvm/llvm-project] c9e5b6: [RISCV] Rename VALUrVV/VALUrVX/VALUrVF tablegen cl...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c9e5b6a03b23af963d2a0ebb82a9061372c47ff5
      https://github.com/llvm/llvm-project/commit/c9e5b6a03b23af963d2a0ebb82a9061372c47ff5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2025-08-22 (Fri, 22 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td

  Log Message:
  -----------
  [RISCV] Rename VALUrVV/VALUrVX/VALUrVF tablegen clases. NFC (#154989)

Rename them to VMACVV/VX/VF. The 'r' previously meant "reversed" since
their operand order is vs1, vs2 where other vector instructions are vs2,
vs1.

These instructions are also ternary and have a tied register. "MAC"
better reflects this property.

While doing this I also found a missing earlyclobber in VWMAC_MV_X, but
I don't think this has any effect since we use pseudos for regalloc.



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