[all-commits] [llvm/llvm-project] 1bf31c: [MLIR][XeGPU] Update XeGPU create_tdesc, update_of...

[Sang Ik Lee via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1bf31c3cd01e946103eddf08b5b52a1c6fad96a4
      https://github.com/llvm/llvm-project/commit/1bf31c3cd01e946103eddf08b5b52a1c6fad96a4
  Author: Sang Ik Lee <sang.ik.lee at intel.com>
  Date:   2025-08-22 (Fri, 22 Aug 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
    M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
    M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
    M mlir/test/Dialect/XeGPU/invalid.mlir
    M mlir/test/Dialect/XeGPU/ops.mlir

  Log Message:
  -----------
  [MLIR][XeGPU] Update XeGPU create_tdesc, update_offset, load, store and prefetch. (#154653)

This PR tightens some loose ends in some XeGPU op definitions.
Changes are backward compatible except for

- Enforcing previous implicit assumption of load/store/prefetch offsets
is required if source/dest is not a scatter tensor descriptor.
- Likewise, enforce offsets is not allowed if source/dest is a scatter
tensor descriptor.
- Additionally, allow i64, i32 and ui32 as source/dest for
load/store/prefetch. This matches behavior of tensor descriptor which
allows i64, i32 and ui32 base address in addition to ui64
- Explicitly state that create_tdesc and update_offset ops are not valid
in SIMT mode. create_tdesc and update_offset ops are still available for
subgroup level non SIMT mode.
- prefetch op adds attribute offset_align_byte to be used with integer
 pointer source to enable address calculation with offsets.

New test cases are added for the new enforced checks.

Other minor implementation change:
XeGPU scatter tensor descriptor only allows 1D base memref. This was
check in op verify() method. Now moved to tablegen - ODS - definition.



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