[all-commits] [llvm/llvm-project] 84841c: DAG: Handle half spanning extract_subvector in typ...

[Matt Arsenault via All-commits]

  Branch: refs/heads/users/arsenm/issue153808/fix-assert-extract-subvector-uses-both-pieces
  Home:   https://github.com/llvm/llvm-project
  Commit: 84841c0506e16a88912058eed094df4d967a25b0
      https://github.com/llvm/llvm-project/commit/84841c0506e16a88912058eed094df4d967a25b0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2025-08-19 (Tue, 19 Aug 2025)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/AMDGPU/issue153808-extract-subvector-legalize.ll

  Log Message:
  -----------
  DAG: Handle half spanning extract_subvector in type legalization

Previously it would just assert if the extract needed elements from
both halves. Extract the individual elements from both halves and
create a new vector, as the simplest implementation. This could
try to do better and create a partial extract or shuffle (or
maybe that's best left for the combiner to figure out later).

Fixes secondary issue noticed as part of #153808



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