[all-commits] [llvm/llvm-project] c00b04: [RISCV] Generate QC_INSB/QC_INSBI instructions fro...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c00b04a7e041bcf0aaf92cf9aacfe536458f1911
      https://github.com/llvm/llvm-project/commit/c00b04a7e041bcf0aaf92cf9aacfe536458f1911
  Author: Sudharsan Veeravalli <quic_svs at quicinc.com>
  Date:   2025-08-19 (Tue, 19 Aug 2025)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/test/CodeGen/RISCV/xqcibm-insert.ll

  Log Message:
  -----------
  [RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (#154023)

Generate QC_INSB/QC_INSBI from `or (and X, MaskImm), OrImm` iff the
value being inserted only sets known zero bits. This is based on a
similar DAG to DAG transform done in `AArch64`.



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