[all-commits] [llvm/llvm-project] f38c83: [AArch64][llvm] Disassemble instructions in `SYS` ...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f38c83c582cb9de04556c32bc6b18ad1aeda74af
      https://github.com/llvm/llvm-project/commit/f38c83c582cb9de04556c32bc6b18ad1aeda74af
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2025-08-18 (Mon, 18 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
    M llvm/test/MC/AArch64/arm64-aliases.s

  Log Message:
  -----------
  [AArch64][llvm] Disassemble instructions in `SYS` alias encoding space more correctly (#153905)

For instructions in the `SYS` alias encoding space which take no
register operands, and where the unused 5 register bits are not all set
(0x31, 0b11111), then disassemble to a `SYS` alias and not the
instruction, since it is not considered valid.

This is because it is specified in the Arm ARM in text similar to this
(e.g. page C5-1037 of DDI0487L.b for `TLBI ALLE1`, or page C5-1585 for
`GCSPOPX`):
```
  Rt should be encoded as 0b11111. If the Rt field is not set to 0b11111,
  it is CONSTRAINED UNPREDICTABLE whether:
    * The instruction is UNDEFINED.
    * The instruction behaves as if the Rt field is set to 0b11111.
```

Since we want to follow "should" directives, and not encourage undefined
behaviour, only assemble or disassemble instructions considered valid.
Add an extra test-case for this, and all existing test-cases are
continuing to pass.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications