[all-commits] [llvm/llvm-project] c6fe56: [AArch64][MachineCombiner] Combine sequences of ga...

[Jonathan Cohen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c6fe567064847ed3c8821422a4fc81eefc7f4291
      https://github.com/llvm/llvm-project/commit/c6fe567064847ed3c8821422a4fc81eefc7f4291
  Author: Jonathan Cohen <joncoh at apple.com>
  Date:   2025-08-18 (Mon, 18 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    A llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir
    A llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir
    A llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-uniform-cases.ll
    M llvm/test/CodeGen/AArch64/concat-vector.ll
    M llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
    M llvm/test/CodeGen/AArch64/fsh.ll
    M llvm/test/CodeGen/AArch64/llvm.frexp.ll
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/nontemporal.ll

  Log Message:
  -----------
  [AArch64][MachineCombiner] Combine sequences of gather patterns (#152979)

Reland of #142941

Squashed with fixes for #150004, #149585

This pattern matches gather-like patterns where
values are loaded per lane into neon registers, and 
replaces it with loads into 2 separate registers, which
will be combined with a zip instruction. This decreases
the critical path length and improves Memory Level
Parallelism.

rdar://151851094



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