[all-commits] [llvm/llvm-project] 0e9b6d: [IA][RISCV] Detecting gap mask from a mask assembl...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0e9b6d6c8a111e214a3907fe97ccadf8f438d854
      https://github.com/llvm/llvm-project/commit/0e9b6d6c8a111e214a3907fe97ccadf8f438d854
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2025-08-15 (Fri, 15 Aug 2025)

  Changed paths:
    M llvm/lib/CodeGen/InterleavedAccessPass.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

  Log Message:
  -----------
  [IA][RISCV] Detecting gap mask from a mask assembled by interleaveN intrinsics (#153510)

If the mask of a (fixed-vector) deinterleaved load is assembled by
`vector.interleaveN` intrinsic, any intrinsic arguments that are
all-zeros are regarded as gaps.



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