[all-commits] [llvm/llvm-project] 177f27: [VPlan] Add incoming_[blocks, values] iterators to ...

Iris Shi via All-commits all-commits at lists.llvm.org
Thu Aug 14 10:18:14 PDT 2025 

  Branch: refs/heads/users/el-ev/_CIR_Add_InlineAsmOp_lowering_to_LLVM
  Home:   https://github.com/llvm/llvm-project
  Commit: 177f27d22092cb64e871e6cd2f8981d24e823186
      https://github.com/llvm/llvm-project/commit/177f27d22092cb64e871e6cd2f8981d24e823186
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp

  Log Message:
  -----------
  [VPlan] Add incoming_[blocks,values] iterators to VPPhiAccessors (NFC)  (#138472)

Add 3 new iterator ranges to VPPhiAccessors

* incoming_values(): returns a range over the incoming
  values of a phi 
* incoming_blocks(): returns a range over the incoming 
  blocks of a phi
* incoming_values_and_blocks: returns a range over pairs of
   incoming values and blocks.

Depends on https://github.com/llvm/llvm-project/pull/124838.

PR: https://github.com/llvm/llvm-project/pull/138472


  Commit: d57ab276b659c960fda8c0bb349648c4d266796e
      https://github.com/llvm/llvm-project/commit/d57ab276b659c960fda8c0bb349648c4d266796e
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    A llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll

  Log Message:
  -----------
  [SLP] Recalculate cleared deps for potential control schedule data nodes

Need to recalculate the dependencies for all potential control data
schedule nodes to prevent compiler crash.

Fixes #153571


  Commit: ec237da212a4d2a18ddb82486a8b4cb170e98319
      https://github.com/llvm/llvm-project/commit/ec237da212a4d2a18ddb82486a8b4cb170e98319
  Author: Brox Chen <guochen2 at amd.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    A llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll

  Log Message:
  -----------
  [AMDGPU][True16][CodeGen] insert proper register for 16bit data type in vop3p insts (#153143)

In true16 flow, we cannot simply replace v2f16 to its Lo16 when Lo == Hi
in a vop3p packed inst, since the register size is mismatched. This
trigger functional errors in the downstream branch and this is caused by
illegal `VGPR_32 = COPY VGPR_16` created by ISel and hit the rewrite
virtual reg and coalescer pass

Correctly insert reg_sequence/s_mov in true16 flow


  Commit: 1945753700dc9e1ba526cc2078296518b7c93e8c
      https://github.com/llvm/llvm-project/commit/1945753700dc9e1ba526cc2078296518b7c93e8c
  Author: Boyana Norris <brnorris03 at gmail.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
    M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
    M mlir/test/Dialect/Linalg/roundtrip.mlir

  Log Message:
  -----------
  [mlir][linalg] Fix incorrect linalg short form printing (#153219)

Both `linalg.map` and `linalg.reduce` are sometimes printed in short
form incorrectly, resulting in a round-trip output with different
semantics. This patch adds additional `yield` operand checks to ensure
that all criteria for short-form printing are satisfied. Updated/added
comments and renamed the `findPayloadOp` function to `canUseShortForm`,
which more accurately reflects its purpose. A couple of new lit tests
check for the proper use of long form when short-form conditions are not
met.

Fixes #117528


  Commit: e2ae634cc1cf0c52993478053f248fa82aade3ec
      https://github.com/llvm/llvm-project/commit/e2ae634cc1cf0c52993478053f248fa82aade3ec
  Author: Matthias Springer <me at m-sp.org>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M mlir/include/mlir/Conversion/LLVMCommon/Pattern.h
    M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
    M mlir/lib/Conversion/LLVMCommon/Pattern.cpp

  Log Message:
  -----------
  [mlir][LLVM][NFC] Simplify `copyUnrankedDescriptors` (#153597)

Split the function into two: one that copies a single unranked
descriptor and one that copies multiple unranked descriptors. This is in
preparation of adding 1:N support to the Func->LLVM lowering patterns.


  Commit: ca4ebf95172d24f8c47655709b2c9eb85bda5cb2
      https://github.com/llvm/llvm-project/commit/ca4ebf95172d24f8c47655709b2c9eb85bda5cb2
  Author: Alexey Bataev <a.bataev at outlook.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/test/Transforms/SLPVectorizer/AArch64/alternate-vectorization-split-node.ll
    M llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
    M llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll

  Log Message:
  -----------
  [SLP]Support LShr as base for copyable elements

Added support for LShr instructions as base for copyable elements. Also,
added simple analysis for best base instruction selection, if multiple
candidates are available.

Reviewers: hiraditya, RKSimon

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/153393


  Commit: a5ba6067d619b0dd5f7b660ff4658f9af43db556
      https://github.com/llvm/llvm-project/commit/a5ba6067d619b0dd5f7b660ff4658f9af43db556
  Author: Pawan Nirpal <pawan.anil.nirpal at intel.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M compiler-rt/lib/builtins/cpu_model/x86.c
    M llvm/lib/TargetParser/Host.cpp

  Log Message:
  -----------
  [Clang][NFC] Use Hex Encoding for Intel CPU CPUID family (#153004)

Use Hex Encoding for CPUID family to match number format with Intel ISE
rev.58:
https://cdrdv2.intel.com/v1/dl/getContent/671368


  Commit: 28d5bc5649a9d004d7a91f4a3639aa6aa3b130b2
      https://github.com/llvm/llvm-project/commit/28d5bc5649a9d004d7a91f4a3639aa6aa3b130b2
  Author: Ian McInerney <mcianster at gmail.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M flang/lib/Frontend/CompilerInvocation.cpp
    A flang/test/Preprocessing/defines_pic_frontend.F90

  Log Message:
  -----------
  [Flang][Driver] Predefine pic/pie macros based on configured level (#153449)

Predefine the `__pic__/__pie__/__PIC__/__PIE__` macros based on the
configured relocation level. This logic mirrors that of the clang
driver, where `__pic__/__PIC__` are defined for both PIC and PIE modes,
but `__pie__/__PIE__` are only defined for PIE mode.

Fixes https://github.com/llvm/llvm-project/issues/135275


  Commit: 6961139ce9154d03c88b8d46c8742a1eaa569cd9
      https://github.com/llvm/llvm-project/commit/6961139ce9154d03c88b8d46c8742a1eaa569cd9
  Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M flang/module/cudadevice.f90
    M flang/test/Lower/CUDA/cuda-libdevice.cuf

  Log Message:
  -----------
  [flang][cuda] Add interfaces for __sinf and __tanf (#153609)


  Commit: 606173188bb9c50ab3ca5f3b8aa36f4b06a2e635
      https://github.com/llvm/llvm-project/commit/606173188bb9c50ab3ca5f3b8aa36f4b06a2e635
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp

  Log Message:
  -----------
  [CIR] Add `InlineAsmOp`


  Commit: 8e86b93f1e348169aa3c2eba75903bf33f154f97
      https://github.com/llvm/llvm-project/commit/8e86b93f1e348169aa3c2eba75903bf33f154f97
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    A clang/test/CIR/IR/inline-asm.cir

  Log Message:
  -----------
  add parsing test


  Commit: 0282e282f209d6ef782872efabe916c05f1e61c1
      https://github.com/llvm/llvm-project/commit/0282e282f209d6ef782872efabe916c05f1e61c1
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp

  Log Message:
  -----------
  Apply review suggestions

Co-authored-by: Andy Kaylor <akaylor at nvidia.com>


  Commit: 024a77e05434291d424ea7a8566d07fea96fc8f7
      https://github.com/llvm/llvm-project/commit/024a77e05434291d424ea7a8566d07fea96fc8f7
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-08-14 (Thu, 14 Aug 2025)

  Changed paths:
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp

  Log Message:
  -----------
  Update clang/lib/CIR/Dialect/IR/CIRDialect.cpp

Co-authored-by: Morris Hafner <mmha at users.noreply.github.com>


  Commit: abf9f5e5832f22be028bb55e6da691c5b2a2a6d2
      https://github.com/llvm/llvm-project/commit/abf9f5e5832f22be028bb55e6da691c5b2a2a6d2
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-08-15 (Fri, 15 Aug 2025)

  Changed paths:
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp

  Log Message:
  -----------
  Update clang/lib/CIR/Dialect/IR/CIRDialect.cpp

Co-authored-by: Andy Kaylor <akaylor at nvidia.com>


  Commit: 623e651f22dbb6112fef44f886c341c2cdd904ef
      https://github.com/llvm/llvm-project/commit/623e651f22dbb6112fef44f886c341c2cdd904ef
  Author: Iris Shi <0.0 at owo.li>
  Date:   2025-08-15 (Fri, 15 Aug 2025)

  Changed paths:
    M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
    M compiler-rt/lib/builtins/cpu_model/x86.c
    M flang/lib/Frontend/CompilerInvocation.cpp
    M flang/module/cudadevice.f90
    M flang/test/Lower/CUDA/cuda-libdevice.cuf
    A flang/test/Preprocessing/defines_pic_frontend.F90
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/TargetParser/Host.cpp
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    A llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/alternate-vectorization-split-node.ll
    A llvm/test/Transforms/SLPVectorizer/X86/control-deps-schedule-data-recalculate.ll
    M llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
    M llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
    M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
    M mlir/include/mlir/Conversion/LLVMCommon/Pattern.h
    M mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
    M mlir/lib/Conversion/FuncToLLVM/FuncToLLVM.cpp
    M mlir/lib/Conversion/LLVMCommon/Pattern.cpp
    M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
    M mlir/test/Dialect/Linalg/roundtrip.mlir

  Log Message:
  -----------
  Merge branch 'users/el-ev/08-13-_cir_add_inlineasmop_' into users/el-ev/_CIR_Add_InlineAsmOp_lowering_to_LLVM


Compare: https://github.com/llvm/llvm-project/compare/dec7dd8c9da3...623e651f22db

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